Commit Graph

63702 Commits

Author SHA1 Message Date
skrll
821cb88dda G/C VM_MAX_KERNEL_BUF 2017-02-13 09:46:29 +00:00
palle
a1ac020c5d sun4v: Revert previous - paddr_t is not a pointer... noted by nakayama@ 2017-02-12 19:35:54 +00:00
maxv
346f85091d Uninitialized var, found by Mootja; not tested, but obvious enough. 2017-02-12 18:21:50 +00:00
palle
c647103f61 sun4v: Fix calculation of mmu data fault address (pointer arithmetic) 2017-02-11 23:41:36 +00:00
christos
ef53c29f60 make this compile again. 2017-02-11 21:04:29 +00:00
maxv
57f70dc48f Put 2MB alignments between the kernel segments. This way the kernel image
is entirely mapped with large pages, which uniformizes performance and
reduces fluctuation. Sent on port-amd64.
2017-02-11 16:02:11 +00:00
maxv
1bae5b3506 Fix a few (unused) MSR values, and add some others that I believe are
relevant.

From Murray Armfield (PR/42861).
2017-02-11 15:11:45 +00:00
maxv
2c9e85a3d4 Remove VM_MAX_KERNEL_BUF (unused). Looks like several other ports could
do the same.
2017-02-11 15:05:15 +00:00
maxv
ac670b3099 Instead of using a global array with per-cpu indexes, embed the tmp VAs
into cpu_info directly. This concerns only {i386, Xen-i386, Xen-amd64},
because amd64 already has a direct map that is way faster than that.

There are two major issues with the global array: maxcpus entries are
allocated while it is unlikely that common i386 machines have so many
cpus, and the base VA of these entries is not cache-line-aligned, which
mostly guarantees cache-line-thrashing each time the VAs are entered.

Now the number of tmp VAs allocated is proportionate to the number of CPUs
attached (which therefore reduces memory consumption), and the base is
properly aligned.

On my 3-core AMD, the number of DC_refills_L2 events triggered when
performing 5x10^6 calls to pmap_zero_page on two dedicated cores is on
average divided by two with this patch.

Discussed on tech-kern a little.
2017-02-11 14:11:24 +00:00
maxv
28a7f20c99 As the XXX implicitly suggests, this line is wrong. Many other families
support PMCs (like my 10h amd). While here, put a warning in a comment.
2017-02-11 13:22:58 +00:00
nonaka
2e88f6a9fb Added efiboot TODO. 2017-02-11 10:33:44 +00:00
nonaka
0ecf94e076 PR/51953: fix unable to boot on some AMD machine.
Delayed the timing to copy the kernel to actual address.
copy routine from common/lib/libc/arch/x86_64/string/bcopy.S
2017-02-11 10:23:39 +00:00
nonaka
1549c4d69d efiboot: Copy bootinfo to safe arena. 2017-02-11 10:18:10 +00:00
nonaka
167dd5f117 efiboot: don't call WaitForSingleEvent after ExitBootServices is called. 2017-02-11 10:15:55 +00:00
nonaka
990bc068a4 efiboot: pass memory map after ExitBootService is called to kernel. 2017-02-11 10:13:46 +00:00
palle
88429e4286 sun4v: Added handling of trap type 0x034 (address alignment error) + fixed typo mmfsa -> mmufsa. Verified for both sun4u and sun4v using qemu. 2017-02-10 23:26:23 +00:00
tnn
20f5a8dc9c remove misleading comment about version 3.0 microcode
The last known microcode to work is 2.4. Version 3.0 changes
the header signature and fails with "block too big for NPE memory".
Provide a backup download URL since intel removed version < 3.0.
2017-02-10 23:11:30 +00:00
tnn
337034d0bf update firmware download URL 2017-02-10 20:30:39 +00:00
maxv
6bc9aa3b62 If the segment list is full, print a warning on the console and launch the
system with the available segments.

High memory systems may have more than VM_PHYSSEG_MAX segments; it is
better to truncate the memory and allow the system to work rather than
just panicking. The user can still increase VM_PHYSSEG_MAX (or ask us to).

Fixes issues such as PR/47093.

Note: the warning is logged but does not appear in dmesg, this too needs
to be fixed for the rest of the bootstrap procedure.
2017-02-10 10:39:36 +00:00
maxv
61cd43dcab Use macros instead of hard-coded constants. By the way, I don't think this
code is correct, but whatever.
2017-02-10 10:02:26 +00:00
maxv
edffb1dd15 Import iomem_ex locally. 2017-02-10 09:57:04 +00:00
christos
74761b40ce kill variable stack allocation 2017-02-10 04:00:48 +00:00
maxv
7d7daa84ad If the preloaded modules cannot be mapped with the initial amount of VA,
discard the associated bootinfo entry. Otherwise the machine faults and
reboots immediately.

I spotted this bug more than a year ago, but I recently saw that there is
already PR/42645 (7 years old), so just fix it. The size has been increased
in the meantime, so the limit is unlikely to be reached anyway.
2017-02-09 19:30:56 +00:00
joerg
69a2ab8761 Bump the ram disk and miniroot size slightly for clang. 2017-02-09 18:15:07 +00:00
joerg
5a64c2ee91 Give clang a bit more space on the RAM disk. 2017-02-09 15:24:08 +00:00
nonaka
0238774f0d efi_md::md_virt always uses uint64_t. 2017-02-09 11:56:40 +00:00
maxv
929132b4a7 No, do not just copy code from i386 and expect it to work on amd64. There
are several structural differences. At least two issues here: segment
registers that could fault in kernel mode with userland TLS, and a non-
canonical %eip on iret.

Not even tested, but just obvious. By the way, I believe this function is
still buggy since we don't call cpu_fsgs_reload while %fs/%gs could have
been reloaded.
2017-02-09 08:38:25 +00:00
maxv
74eedc014a Restore %ds before swapgs. Movs to segment registers are allowed to fault
in kernel mode but simply cause a signal to be sent to userland. The thing
is, in this case %gs is not restored when entering the trap routine, which
means the kernel uses userland's TLS instead of using its own. Which in
short makes it easy to escalate privileges.

Currently, this bug is triggered only in one place, which I am about to
fix too.
2017-02-09 08:23:46 +00:00
msaitoh
a6c7aa60cf Supress verbose message "This pci host supports neither MSI nor MSI-X."
on VMware and KVM. OK'd by k-nakahara.
2017-02-09 03:38:01 +00:00
rin
b765dc9992 Shrink the ramdisk of INSTALL kernel for zaurus in order to fit within 5MB.
Now free spaces of the main kernel and ramdisk are about 62KB and 215KB for
INSTALL, respectively.

OK christos
2017-02-08 20:11:18 +00:00
kre
0dcb58b5ac Analagous fix to that just committed to the equiv amd64 sources.
Note: this one has yet to be compile tested, so anything is possible...
2017-02-08 18:53:01 +00:00
kre
4f1bfb58c6 All bow down before the Great Code Compiler.
Specifically, it has been commanded that unused-functions is a warning,
and, as all should know, all warnings be errors.

Hence, since XEN kernels do not call set_sys_gdt(), that function
may not be included (and the XEN kernel  saves a few tens of bytes.)

An alternate fix would be to just remove "static" - but that would be
the equivalent to just giving the compiler the finger ...   hmm, maybe
that would have been a better fix...
2017-02-08 18:50:51 +00:00
christos
d9093907a5 __empty -> __nothing 2017-02-08 18:01:12 +00:00
christos
e3abb3c383 don't define __empty. 2017-02-08 16:14:08 +00:00
maxv
6d5f205475 Remove gdt_reload_cpu. GDTR takes a VA as base, and in our x86
implementation this VA is per-cpu and does not change; there is therefore
no need to remotely reload GDTR.
2017-02-08 10:08:26 +00:00
maxv
e6ed7762a4 Localify, add a comment and merge some others. 2017-02-08 09:39:32 +00:00
maxv
44542be787 In cpu_mcontext32_validate, allow the registers to have different locations
if the LDT is user-set.

I am intentionally not allowing this in check_sigcontext32, because I don't
think Wine uses it.
2017-02-06 16:34:37 +00:00
maxv
54f03c77cf Add the USER_LDT sysarch options in netbsd32. We don't translate 'desc',
since if we ever implement USER_LDT we will only allow 8-byte-sized
entries, which have the same layout on amd64 and i386.
2017-02-06 16:02:17 +00:00
nonaka
3595ccfb7d Remove unnecessary flag. 2017-02-06 10:32:35 +00:00
palle
9634b3fd38 sun4v: update TODO list to reflect the current state - TRAP_SETUP() was adapted to handle both sun4u and sun4v systems in version 1.404 of locore.s 2017-02-05 20:08:35 +00:00
maxv
6c9d31ed8a Rename ldt->ldtstore and gdt->gdtstore on i386. It reduces the diff with
amd64, and makes it easier to track down these variables on nxr - 'ldt'
and 'gdt' being common keywords.
2017-02-05 10:42:21 +00:00
joerg
3a551b58b2 Be a bit nicer to outdated compilers and use __unreachable(). 2017-02-05 10:13:43 +00:00
joerg
1ca42661a2 Unbreak clang again. 2017-02-05 10:13:18 +00:00
maxv
173e2026e3 Remove misleading comment; these macros should not be used if a user LDT
is active.
2017-02-05 08:58:39 +00:00
maxv
549eebb1a2 Remove #if 0 on USER_LDT. 2017-02-05 08:52:11 +00:00
maxv
c4d9b79654 Now that valid_user_selector only checks for LDT selectors, remove it. A
user may legitimately want to have one register in the GDT, and another in
the LDT.

Pass 2/2.
2017-02-05 08:36:08 +00:00
maxv
33f2d3769e In cpu_mcontext_validate, treat %cs differently depending on whether a user
LDT is set; just check the permission without checking the location (which
may change).

In valid_user_selector, don't check the length of the LDT. This is racy
because pm_ldt_len could be updated by another thread, and useless since
the length is already referenced in ldtr (ldt_alloc), which means that any
overflow will fault in userland.

Also, don't check the permission of the segment pointed to; this too is
racy, and we don't care either since the permissions are checked earlier
in x86_set_ldt1.

Pass 1/2.
2017-02-05 08:19:05 +00:00
maya
dfbac43682 Remove duplicate check. uvm_physseg_valid_p(upm) == false is also
our for loop exit condition, and will never happen. NFC
2017-02-05 06:26:06 +00:00
maya
482c927acf Fix off by one.
Fixes PR port-amd64/51944: sparse core dumps do not work
2017-02-05 06:13:53 +00:00
maya
2675f23497 Match the iterator in sys/uvm/uvm_page.c:1866. NFC.
No matching KASSERT - this case is covered by the above
if (uvm_physseg_valid_p(upm) == false) break;
2017-02-05 06:12:33 +00:00