5f3a256833
Allocate the DMA windows out of the PCI memory extent map after
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DMA is initialized.
2000-11-29 06:30:09 +00:00
96294f7b26
Do the additional PCI memory initialization after configuring DMA.
2000-11-29 06:29:10 +00:00
8f20972db2
Revert previous -- we'll do it differently.
2000-11-29 06:21:12 +00:00
d615083897
The AMD 751 doesn't have DMA windows, so allocate the RAM out of the
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PCI memory extent map. Bad things will happen if we try to assign
a device where RAM is mapped into PCI space.
2000-11-29 05:56:49 +00:00
8ebabb1aae
Increase the number of static extent descriptors from 8 to 16,
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and add a means for calling a chip-specific init hook.
2000-11-29 05:53:29 +00:00
73265fa0c9
Duh, don't need SGMAP-related includes on this chipset.
2000-11-18 05:56:20 +00:00
d760e0b407
Add code to read the EISA configuration NVRAM as set up by
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an EISA Configuration Utility. Code to access this data
is forthcoming.
XXX This could probably be made MI at some point.
2000-07-29 23:18:46 +00:00
1204c1faaf
Oops, treat 2100A_A500 just like 2100_A500 in every place necessary.
2000-07-12 21:02:14 +00:00
249773b538
Deal with another odd need of the Sable/Lynx systems, which need to
...
have an ISA chipset present before the PCI-EISA bridge has been
attached (because the STDIO module has an ISA DMA-using device,
the floppy controller, connected to it).
2000-07-12 20:50:00 +00:00
c88e94a407
remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h>
2000-06-29 08:58:45 +00:00
69a6fe113c
Garbage-collect CHIP_PHYSADDR().
2000-06-26 19:46:24 +00:00
cc9dfe871b
Do the previously slightly differently, to avoid confusing the internal
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space extent maps. Pointed out by msaitoh@netbsd.org . (Someone should
send me an EV6 machine!)
2000-06-26 18:19:26 +00:00
9a2d9ff68b
Because of the Cool sign-extension hack we use to access PCI space,
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the `get window' method ends up with the wrong physical address to
pass onto userspace (which wants to mmap the space).
Compensate by adding a CHIP_PHYSADDR() macro which un-hacks the address
suitably for mapping with other-than-KSEG.
2000-06-26 02:42:10 +00:00
a2318e49a0
G/c unused include.
2000-06-25 19:33:01 +00:00
167094d31a
Implement mcpcia_bus_get_window().
2000-06-25 19:32:19 +00:00
865004842f
Implement tsp_bus_get_window().
2000-06-25 19:17:39 +00:00
fe8841f18a
Some platforms, like the Sable, hook EISA and ISA interrupts
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up Very Differently. Handle this.
2000-06-13 16:40:37 +00:00
75975dd6c5
G/c some unneeded prototypes (functions don't exist).
2000-06-11 22:47:00 +00:00
f3d9d1ac8a
Use the common 82c693 access functions to read/write the ELCR.
2000-06-06 03:10:13 +00:00
f65502fc36
Report which compatibility IRQ the PCI IDE gets.
2000-06-06 00:50:15 +00:00
b0ce38fd8a
Switch to the new `evcnt' mechanism for counting interrupts. Maintain
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a per-CPU interrupt counter for clock, device, and interprocessor
interrupts.
2000-06-05 21:47:26 +00:00
2668e3b213
Switch to the new `evcnt' mechanism for counting interrupts. Maintain
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a per-CPU interrupt counter for clock, device, and interprocessor
interrupts.
2000-06-05 21:47:10 +00:00
cffb580806
Implement the more flexiable `evcnt' interface as discussed (briefly) on
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tech-kern and now documented in evcnt(9).
2000-06-04 19:14:14 +00:00
9851571246
Add support for the Alpha Processor, Inc. UP1000 EV6 system.
2000-06-01 20:30:28 +00:00
13c9f8d398
implement bus_space_vaddr()
2000-04-17 17:24:48 +00:00
156114a02f
Use the new cpu_amask variable rather than calling alpha_implver() and
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alpha_amask() ourselves.
2000-04-03 01:48:07 +00:00
f785596e75
Add support for mapping the OHCI USB controller interrupt (which is wired toan ISA IRQ because it's in the same package as the PCI-ISA bridge).
2000-03-19 02:25:29 +00:00
c10a9d31ea
Put the code that enables/disables Pyxis interrupt lines in
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cia_pyxis_intr_enable().
2000-03-19 01:43:25 +00:00
cf3085176e
Nuke all the code associated with the INITIALLY_LEVEL_TRIGGERED() lossage, and
...
instead register a shutdownhook to restore the PIC state.
2000-02-27 02:50:31 +00:00
df88882d80
- Add a bus space method for getting the translation for a window.
...
- Add sysarch methods for "get bus window count", "get bus window",
and "pci conf read/write".
These are a hack, but they're what's necessary in order to make
XFree86 work in its current state.
2000-02-26 18:53:10 +00:00
de974ff82d
Add an internal bus space method alpha_bus_space_translate(), which
...
provides a method to translate an address on an I/O bus into a sysBus
address, along with acccess method information.
2000-02-25 00:45:04 +00:00
9621e6be50
Reset maxstray count if we get a good interrupt for a level.
2000-02-10 07:45:43 +00:00
4821b5ae2f
Guard against trying to disable an interrupt where we'd dereference a
...
bad pointer.
2000-02-10 04:31:36 +00:00
f9e531f1e4
Don't force BWX on Pyxis by default; it's just not reliable enough.
2000-02-09 01:39:20 +00:00
17c346b9e1
Changed cacheable -> prefetchable. [sync w/ swiz]
2000-02-06 04:07:18 +00:00
28bdaf37d9
Changed cacheable -> prefetchable.
2000-02-06 03:52:27 +00:00
97eba73a40
If we have a Pyxis with the DMA page crossing bug, don't allow coalescing
...
of adjacent DMA segments.
XXX This is still not perfect... but making it perfect will probably
require additions to the bus_dma interface and the ISA autoconfiguration
interface.
2000-02-06 01:26:50 +00:00
0cf304bb45
Always use BWX for bus access on Pyxis chips.
2000-02-01 19:29:28 +00:00
35f3518a91
Fix a fatal typo in a Pyxis SGMAP TLB bug workaround. Noticed by
...
Jeff Roberson <nomad@nop.aliensystems.com>.
2000-01-25 03:32:36 +00:00
a5b316c4d5
Key off NSIO and NPCEB for (E)ISA interrupt support.
...
XXX Can probably nuke the SIO test; don't all of the Noritake-class systems
XXX have EISA?
1999-12-15 22:31:04 +00:00
4f580f447c
Key off NSIO and NPCEB for (E)ISA interrupt support.
...
XXX Can probably nuke the SIO test; don't all of the Mikasa-class systems
XXX have EISA?
1999-12-15 22:30:40 +00:00
58a51e3b72
Key off NSIO and NPCEB for (E)ISA interrupt support.
...
XXX Can probably nuke the SIO test; don't all of the ALCOR-class systems
XXX have EISA?
1999-12-15 22:28:15 +00:00
c557690acc
Key off NSIO and NPCEB for (E)ISA interrupt support.
...
XXX Can probably nuke the SIO test; don't all of the Rawhide-class systems
XXX have EISA?
1999-12-15 22:25:21 +00:00
3ffe65b597
Use alpha_shared_intr_{get,set}_private().
1999-12-15 22:21:45 +00:00
deed2b3b4b
Fix a botch in stray interrupt reporting; report the kn300 IRQ, not the
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interrupt enable bit on the MCPCIA the interrupt is mapped to.
1999-12-15 20:10:04 +00:00
781149bb12
Handle the case where PCI dense memory and PCI sparse memory don't
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overlap; don't require allocation from the dense extent if the PCI
memory address isn't mapped into dense space.
Also, make sure to return an error if a liner mapping is requested
and dense space is not available (not just not requested).
1999-12-08 01:48:39 +00:00
9beb275ae8
Oops, committed the wrong version of this file previously.
1999-12-08 00:35:43 +00:00
ac20942bc5
Some systems don't have dense space; don't require it.
1999-12-07 07:04:39 +00:00
51f4c69ad4
Clarify what appear to the untrained eye to be two magic constants (the
...
address shift and access size shift), and allow them to be overridden
by chip-specific code, if necessary.
1999-12-07 05:44:57 +00:00
d5e85e61cf
Fixes PR#8836. Some changes made by somebody else were a tad incomplete so
...
configuring w/o SIO broke compilation. I forget why, but there was at one
point (and may still be) a dependency between SIO and EISA. This change
just makes things compile sensibly again. It may make no sense to build
a kernel w/o sio in this case. I can't test this conveniently because I
haven't got a 4100 with a video card in it at the moment.
1999-12-04 20:29:02 +00:00
thorpej