"ifconfig ixgN media none" drpos link. Not all interface can do link down.
Tested:
82598 AT2 (T)
92599 SF+(SFI) (X520-DA2)
X540
X550-T1
X550EM_x (X10SDV-8C-TLN4F)
X550EM_a (A2SDi-H-TP4F port 0, 1 (T))
Doesn't work:
X550EM_a (A2SDi-H-TP4F port 2, 3 (SFP+ (KR)))
X550EM_a (MA10-ST0 port 2, 3 (SFP+ (SFI)))
(Denverton SFP+ can't force link down because SFP+'s TX_DISABLE pin is
pull down. Is there a way to shutdown SFP+ cage's power?)
Not tested:
82598 fiber.
- Change some functions static.
In ixgbe_msix_que(), que->eitr_setting is limited to IXGBE_MIN_RSC_EITR_10G1G
when link_speed is 1Gbps or 10Gbps. However, que->eitr_setting is set to EITR
register in the *next* Tx/Rx interrupt. If link_speed changes from 100Mbps to
1Gbps ro 10Gbps, que->eitr_setting which is not limited can be set to EITR
register, that is, the problem fixed by ixgbe.c:r1.124 can occur in this case.
To fix this case, que->eitr_setting should be clear when link_speed is changed
or link state is changed.
Furthermore, expand the variants used for AIM (txr->bytes, txr->packets,
rxr->bytes and rxr->packets) from u32 to u64 to avoid wraparound which causes
que->eitr_setting calculation mistake.
XXX pullup-8
into a header for reuse in crt0.o for static ifunc support. Change the
existing logic for sparc64 to use the Bicc variant of ba,a as it allows
+-8MB displacement compared to the BPcc variant's +-1MB. Teach the sparc
variant the same trick for using ba,a and not sethi+jmp when possible.
Different operations are performed during context transitions:
user->kernel: IBRS <- 1
kernel->user: IBRS <- 0
And during context switches:
user->user: IBPB <- 0
kernel->user: IBPB <- 0
[user->kernel:IBPB <- 0 this one may not be needed]
We use two macros, IBRS_ENTER and IBRS_LEAVE, to set the IBRS bit. The
thing is hotpatched for better performance, like SVS.
The idea is that IBRS is a "privileged" bit, which is set to 1 in kernel
mode and 0 in user mode. To protect the branch predictor between user
processes (which are of the same privilege), we use the IBPB barrier.
The Intel manual also talks about (MWAIT/HLT)+HyperThreading, and says
that when using either of the two instructions IBRS must be disabled for
better performance on the core. I'm not totally sure about this part, so
I'm not adding it now.
IBRS is available only when the Intel microcode update is applied. The
mitigation must be enabled manually with machdep.spectreV2.mitigated.
Tested by msaitoh a week ago (but I adapted a few things since). Probably
more changes to come.
* Replace idiotic diagnostic check by KASSERT. max_linkhdr+tlen<=MCLBYTES
is a widespread assumption.
* Improve initialization of 'tp'.
* Put panics in dead branches.
* Merge two switches.
