status from 10 seconds to 250 milli seconds for the second and subsequent
attempts to determine the link status. This prevents unnecessary long
stalls after the device attach routines have completed.
Tested on a dual port QLogic 3212. Approved by mjacob@feral.com.
GPIO interrupt, check the GPIO interrupt status register after clearing
it down to see if the interrupt source has disappeared. If it does,
assume it was a spurious event. Otherwise, panic.
- Move board-specific PCI/GPIO initialisation to its rightful place.
- Handle clearing down latched GPIO interrupts in a board-independent way.
- Use MI com(4) driver for on-chip UARTs.
- Misc. tidying up.
Tested on IXDP425.
http://mail-index.netbsd.org/tech-kern/2003/09/25/0007.html
We now have:
acardide* at pci? dev ? function ? # Acard IDE controllers
aceride* at pci? dev ? function ? # Acer Lab IDE controllers
cmdide* at pci? dev ? function ? # CMD tech IDE controllers
cypide* at pci? dev ? function ? # Cypress IDE controllers
hptide* at pci? dev ? function ? # Triones/HighPoint IDE controllers
optiide* at pci? dev ? function ? # Opti IDE controllers
piixide* at pci? dev ? function ? # Intel IDE controllers
pdcide* at pci? dev ? function ? # Promise IDE controllers
siside* at pci? dev ? function ? # SiS IDE controllers
slide* at pci? dev ? function ? # Symphony Labs IDE controllers
viaide* at pci? dev ? function ? # VIA/AMD/Nvidia IDE controllers
pciide* at pci? dev ? function ? flags 0x0000 # GENERIC pciide driver
serverworks driver not commited yet; there are still copyright issues about
it.