Commit Graph

18 Commits

Author SHA1 Message Date
simonb 6f485abe93 Add a prototype for set_busreg(), fix a couple of white space nits. 2002-11-08 07:01:26 +00:00
augustss 2dce9e8e5e Number PCI busses using a simple pre-order numbering instead of
some strange binary split numbering that doesn't work with multiple
bridges on the same bus, nor with deeply nested bridges.
2002-07-30 15:00:03 +00:00
briggs bea68a808c Change a 'continue' to a 'break' in switch configuring 64-bit devices.
Add a little more debugging code.
2002-06-27 00:59:21 +00:00
kleink e9dc13b243 As discussed with Jason Thorpe: while the `cacheline_size\' argument is
a byte-size quantity, the CacheLine Size configuration register specifies
the system cacheline size in units of 32-bit words; per PCI Local Bus
Specification, rev. 2.1, section 6.2.4.
2002-02-21 20:22:48 +00:00
thorpej 636e9cd08b Add a "cacheline_size" argument to pci_configure_bus(). It is used
to set the cacheline size in the BHLC register.  This should be the
size of the largest D-cache line on a system.
2001-11-28 23:48:34 +00:00
lukem 9048aaae21 add RCSID 2001-11-13 07:48:40 +00:00
thorpej b1ec255377 Add a "firstbus" argument to pci_configure_bus(), indicating the
first bus number to use, rather than always assuming that we should
start at bus #0.
2001-11-09 19:29:12 +00:00
thorpej 716af300ee In query_bus(), use the parent pciconf_bus_t's PCI chipset tag,
not the new bus's (which is potentially uninitialized when some
calls are made).
2001-11-09 19:20:19 +00:00
thorpej a73a7f44bd Bump MAX_CONF_DEV to 32, add some missing newlines in error
messages, and add a TODO item (allocate all metadata dynamically).
2001-09-03 03:46:26 +00:00
briggs e6ca9b3514 Fix use of uninitialized variable. Missed by gcc, spotted by enami. 2001-08-31 01:00:16 +00:00
briggs e4f8f2f2da Respect __PCI_BUS_DEVORDER.
If all devices can handle 66MHz, then use 66MHz.
Triple the number of configured I/O ranges that we can handle on a bus
  (8 was insufficient--originally didn't consider multifunction devices)
Allow one to specify which types of memory to configure, I/O, ROM, or
  MEM--for example, one could configure only ROM or only non-ROM.
Ensure that the ROM is disabled if we're not configuring it.
Only set PCI_COMMAND_IO_ENABLE/PCI_COMMAND_MEM_ENABLE if there are valid
  memory ranges configured.
2001-08-30 02:52:41 +00:00
thorpej 2e4bdfe678 Add a TODO item: Do this in 2 passes. One pass that configures the
bus (and optionally maps expansion ROMs), and an optional second
pass to disable expansion ROMs that are mapped.  This would allow
MD code to possibly execute the expansion ROMs (possibly in an x86
emulator) to configure a device (e.g. a VGA card, which pretty much
needs to be configured by its ROM).
2001-08-28 15:13:48 +00:00
thorpej cdf824bfb6 If MD code doesn't provide pci_conf_hook(), then default to not mapping
the expansion ROMs on cards, since address decoders may be shared between
the ROM and PCI memory space on some cards (i.e. "only map the ROM if you're
going to use it, and then unmap it when you're done" is the intended
usage).
2001-08-28 15:09:10 +00:00
thorpej 3078a3d26d It's pretty questionable to printf a PCI tag, but if we're going to
do so, at least make the printf compile across the board.
2001-06-14 01:06:56 +00:00
simonb 18b2f7e6a1 Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
 - New pmap and revised trap handler.
 - Support on-chip timers, PCI controller, UARTs
 - Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
 - Add in-kernel PPC floating point emulation
 - New in{,4}_cksum that is between 1.5 and 5 times faster than the
   old version depending on CPU type.
General changes:
 - Kernel support for generic dbsym-style symbols.
2001-06-13 06:01:44 +00:00
thorpej ce289cc293 Handle non-contiguous BARs. Needed to be able to configure e.g.
IDE and USB on a PIIX3.
2001-05-27 17:50:40 +00:00
briggs 433553dc94 Deal with a lack of the proper type of memory. For example, if a bridge
only supports 16-bit I/O addresses, do not configure it with addresses
having the upper 16-bits non-zero.
2001-02-12 06:24:24 +00:00
briggs c6daae9b79 Add an option (defopt) PCI_NETBSD_CONFIGURE that provides PCI bus
configuration (assignment of bus numbers, BARs, timer values,
interrupt lines, etc.).
The interface must be called from m.d. code prior to probing the bus.
It is meant to be called once for each primary (bus == 0) PCI bus in
the system.  It will configure any busses behind PCI-PCI bridges.
Section 9 man page for pci_configure_bus() will come soon.
In the meantime, sample usage is in arch/sandpoint/sandpoint/mainbus.c.
[ Reviewed by thorpej ]
2001-02-09 14:33:15 +00:00