kiyohara
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258d35a1f0
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Add ATTR_AXI_DDR.
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2017-01-09 14:06:35 +00:00 |
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kiyohara
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fa071fd5eb
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Add 88AP510.
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2016-10-04 15:02:27 +00:00 |
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hsuenaga
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149ad0c83b
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reduce magic numbers. SDRAM address space attribute register has cache coherency
control bits. this bit is important for AURORA_IO_CACHE_COHERENCY.
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2015-06-03 04:00:06 +00:00 |
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kiyohara
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1fc9bc43dd
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Add some Armada 370 IDs.
And fix comment-out-ed ID for Discovery VI. (from Marvell USP)
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2014-03-15 10:40:39 +00:00 |
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rkujawa
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e97aea6084
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Add IDs for Marvell Armada XP and ATTR_SDRAM registers used with IO cache coherency.
Obtained from Marvell, Semihalf.
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2013-05-01 12:23:24 +00:00 |
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kiyohara
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ea897a5d7b
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Add 88f6282.
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2012-07-12 09:39:53 +00:00 |
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kiyohara
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24eff00c48
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Remove some attribute macros. Its specifically for Orion.
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2010-07-20 12:01:33 +00:00 |
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kiyohara
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88f9b614ac
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Add macro MARVELL_ORION_1_88F6183.
Add some comments.
Product ID of Discovery V maybe 0x6450.
Product ID of Discovery VI maybe 0x6490.
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2010-07-20 11:56:47 +00:00 |
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kiyohara
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9cccbb6195
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Add Kirkwood/Discovery Innovation macros.
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2010-07-13 14:00:07 +00:00 |
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kiyohara
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fca22c5f5d
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Use macro PCI_PRODUCT_MARVELL_MV64[34]60.
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2010-05-07 14:25:07 +00:00 |
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kiyohara
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a748aedcb5
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Clean up gt and peripherals.
This change tested compile only.
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2010-04-28 13:51:55 +00:00 |
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