- set the ADC time according to clock speed, not some magic number
- move some mtspr()s which we really only need to do once
- make our envsys_data_t static, this should fix PR 39411
store the SDA status into softc and enable it once after
DIR() is changed to OUTPUT in gpiic_set_dir()
- remove "Read in output mode" warning in gpiic_read_bits()
since it's a vaild operation (to read SCL during SDA output is low)
Tested by kiyohara@ on OPENBLOCKS266.
vectors at 0xfff00000), and trap_subr.S allows the kernel to be in a memory
region which is not reachable by absolute branch instructions (ba and bla).
High-vector support can be enabled by option PPC_HIGH_VEC, and long-branches
to the kernel are enabled by the option DISTANT_KERNEL.
we no longer need to guard against access from hardware interrupt handlers.
Additionally, if cloning a process with CLONE_SIGHAND, arrange to have the
child process share the parent's lock so that signal state may be kept in
sync. Partially addresses PR kern/37437.
proclist_mutex and proclist_lock into a single adaptive mutex (proc_lock).
Implications:
- Inspecting process state requires thread context, so signals can no longer
be sent from a hardware interrupt handler. Signal activity must be
deferred to a soft interrupt or kthread.
- As the proc state locking is simplified, it's now safe to take exit()
and wait() out from under kernel_lock.
- The system spends less time at IPL_SCHED, and there is less lock activity.
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:
Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.
required, because this function will be called for display-consoles only,
and it allows SmartFirmware to attach a rascons console.
Approved by garbled.
