chipset functions acordingly. Initialize timing registers (for now to
the slowest possible setting).
Add some debug output. XXX - clean this up.
This is not ready for prime time, but I can attach ray0 and wi0 now in my
LX.
Distinguish between 2312 and 2300 cards (they *are* different). Enable
RIO (Reduced Interrupt Operation) for the LVD cards (hey- I've seen
batched completions of the 30 commands at a time with this,....)...
If we get a Port Logout on local loop topologies, we have to force the
f/w to log back in. The easiest way (for us) to do this is to force
a LIP. This also will wake up the disk that probably just had a f/w crash.
Implement mailbox 'continuations'- this allows interrupts to re-drive
a mailbox command if it's one that just essentially repeats the previous
mailbox command (e.g., f/w download). This saves a boatload of sleep/wakeup
twitches.
If we're not a 2300 and we're about to return with a 'bogus interrupt'- check
the semaphore register to be non-zero at all and outgoing mailbox 0- this
seems to be where some of the lost ISP1080 commands came from.
the response queue. Instead of the ad hoc ISP_SWIZZLE_REQUEST, we now have
a complete set of inline functions in isp_inline.h. Each platform is
responsible for providing just one of a set of ISP_IOX_{GET,PUT}{8,16,32}
macros.
The reason this needs to be done is that we need to have a single set of
functions that will work correctly on multiple architectures for both little
and big endian machines. It also needs to work correctly in the case that
we have the request or response queues in memory that has to be treated
specially (e.g., have ddi_dma_sync called on it for Solaris after we update
it or before we read from it).
One thing that falls out of this is that we no longer build requests in the
request queue itself. Instead, we build the request locally (e.g., on the
stack) and then as part of the swizzling operation, copy it to the request
queue entry we've allocated. I thought long and hard about whether this was
too expensive a change to make as it in a lot of cases requires an extra
copy. On balance, the flexbility is worth it. With any luck, the entry that
we build locally stays in a processor writeback cache (after all, it's only
64 bytes) so that the cost of actually flushing it to the memory area that is
the shared queue with the PCI device is not all that expensive. We may examine
this again and try to get clever in the future to try and avoid copies.
Another change that falls out of this is that MEMORYBARRIER should be taken
a lot more seriously. The macro ISP_ADD_REQUEST does a MEMORYBARRIER on the
entry being added. But there had been many other places this had been missing.
It's now very important that it be done.
For NetBSD, it does a ddi_dmamap_sync as appropriate. This gets us out of
the explicit ddi_dmamap_sync on the whole response queue that we did for SBus
cards at each interrupt.
Set things up so that platforms that cannot have an SBus don't get a lot of
the SBus code checks (dead coded out).
Additional changes:
Fix a longstanding buglet of sorts. When we get an entry via isp_getrqentry,
the iptr value that gets returned is the value we intend to eventually plug
into the ISP registers as the entry *one past* the last one we've written-
*not* the current entry we're updating. All along we've been calling sync
functions on the wrong index value. Argh. The 'fix' here is to rename all
'iptr' variables as 'nxti' to remember that this is the 'next' pointer-
not the current pointer.
Devote a single bit to mboxbsy- and set aside bits for output mbox registers
that we need to pick up- we can have at least one command which does not
have any defined output registers (MBOX_EXECUTE_FIRMWARE).
Explicitly decode GetAllNext SNS Response back *as* a GetAllNext response.
Otherwise, we won't unswizzle it correctly.
Nuke some additional __P macros.
We shouldn't try to configure it in that case.
This will make serial console work. completes fix to PR#14213
(Private email determined PR author was using serial console.)
in how interrupts are down- the 23XX has not only a different place to check
for an interrupt, but unlike all other QLogic cards, you have to read the
status as a 32 bit word- not 16 bit words. Rather than have device specific
functions as called from the core module (in isp_intr), it makes more sense
to have the platform/bus modules do the gruntwork of splitting out the
isr, semaphore register and the first outgoing mailbox register (if needed)
*prior* to calling isp_intr (if calling isp_intr is necessary at all).
This is a completely rewritten scsipi_xfer execution engine, and the
associated changes to HBA drivers. Overview of changes & features:
- All xfers are queued in the mid-layer, rather than doing so in an
ad-hoc fashion in individual adapter drivers.
- Adapter/channel resource management in the mid-layer, avoids even trying
to start running an xfer if the adapter/channel doesn't have the resources.
- Better communication between the mid-layer and the adapters.
- Asynchronous event notification mechanism from adapter to mid-layer and
peripherals.
- Better peripheral queue management: freeze/thaw, sorted requeueing during
recovery, etc.
- Clean separation of peripherals, adapters, and adapter channels (no more
scsipi_link).
- Kernel thread for each scsipi_channel makes error recovery much easier
(no more dealing with interrupt context when recovering from an error).
- Mid-layer support for tagged queueing: commands can have the tag type
set explicitly, tag IDs are allocated in the mid-layer (thus eliminating
the need to use buggy tag ID allocation schemes in many adapter drivers).
- support for QUEUE FULL and CHECK CONDITION status in mid-layer; the command
will be requeued, or a REQUEST SENSE will be sent as appropriate.
Just before the merge syssrc has been tagged with thorpej_scsipi_beforemerge
saves about 2.2MB under /usr/include/dev/. Discussed on tech-kern@
recently.
I HOPE to get the list right. The headers I left in are ones
used for MI tools and those whose usage I discovered by grep over tree sources.
Feel free to put needed includes back in if you encounter anything which
should not be removed from lists.
to last time.
It turns out that in fact, sparc64 was *not* working. There is a discussion
within the tech-kern@netbsd.org mail list as of just prior to this date
that contains the details.
Suffice to say that for sparc64 we have to add back in the usage
of BUS_DMA_COHERENT again to the call to bus_dmamap_load_raw. PK
added the usage of bus_dmamap_load_raw- which agrees with the
man page description of it- but now does not match what the
original BusDma author seems to think it's supposed to do.
While we're at it, do a specific set of steps for setting up and,
if necessary, tearing down, mailbox dma mappings.
right thing, don't use the illegal and "just worked by chance" addition
of BUS_DMA_COHERENT to bus_dmamap_load_raw. There still is a necessity
to add to the architecture to allow one to hint that this should be
a cache coherent mapping.
Fix offset argument to be zero for flushing data tranfers. Kudos to Izumi
for spotting this.
use interrupting mailbox commands for isp_init. Set default HBA role.
Rename request/response dma maps to be more consistent with PCI version.
Enable bus_dmamap_sync on request queue- we already do this for response
queue- better do it for the request queue as well.
Checked to be working against a Sparc10.
martin