- TSO support.
- fix some error handling.
- remove mysterious RTK_NTXSEGS and use more appropriate values
for bus_dmamap_create.
- if we need more than all of our tx descriptors in order to transmit a packet,
just drop it rather than retrying infinitely.
1) After setting an input or output channel to pause, watch for DCH (DMA
halted) to be set before resetting the registers. The manual says this is
required. This *may* fix random auich lockups.
2) Add auich_{trigger,intr,halt}_pipe(), which can operate on any of the
input and output channels. This reduces code duplication quite a bit.
While I'm at it, fill in the mic interrupt handling.
3) The mic in interrupt is MINT, not MIINT. (The latter is modem input.)
* Only futz with the done list in the soft interrupt handler. In the hard
interrupt handler, do nothing except mask WDH and queue the soft interrupt.
This simplifies a bunch of code, removes two O(n^2) queue manipulations,
and gets rid of some really sketchy stuff around the queue head access.
* Use the auto-masking code at the end of the interrupt handler for both WDH
and RHSC interrupts. Again, this reduces the code a little, and avoids
multiple writebacks to the chip registers.
field of the IP header (ip->ip-len) indicates they should be. This handles
the case where an ethernet frame has been padded to meet the minimum ethernet
frame length or erroneously (my cisco switch unnecessarily adds 4 bytes to its
SYN). This padding will be included in the hardware checksum and may be
non-zero, thus making it incorrect.
Also, clear csum_flags when we want a s/w checksum, since we may have started
down the h/w checksum path and determined that it was not usable.
While here, clean-up a few WS nits and ifdef INET the hardware checksum code.
field of the IP header (ip->ip-len) indicates they should be. This handles
the case where an ethernet frame has been padded to meet the minimum ethernet
frame length or erroneously (my cisco switch unnecessarily adds 4 bytes to its
SYN). This padding will be included in the hardware checksum and may be
non-zero, thus making it incorrect.
number of mbuf clusters; also don't free the original mbuf chain
simplify vge_encap() and make error reporting more consistent
normalize vge_start() (including use of IFQ_* macros), and handle the case
when the input mbuf chain is defragmented
JUMBO packets seem to work fine now
Fix the work-around for the NIC bug where it skips to rx
descriptor 0. The driver used to skip to rx descriptor 1.
Hopefully this stops the out-of-order packet reception that
Charles Hannum saw.
When debugging is enabled, print rx-descriptor status flags
before printing the rx bit rate.
Add a debug message for when a beacon tx buffer reclamation.
Reset IFF_OACTIVE when we reset the transmitter.
Pass the consolidated LED state, a struct rtw_led_state,
to rtw_led_attach.
Choose the bit-rate for management frames (1Mb/s) at the
same place we choose for all other frames.
Do not use the NIC's short preamble or RTS options for
management frames. Label beacons for the NIC.
Following a Linux driver, take care not to zero arbitrary
bits in the TPPOLL register.
Use the new idiom for IBSS merges: disable transmitter,
kick the state machine.
Add a second descriptor to the beacon ring. The NIC seems
to like this much better.
with aif_get_mailbox(). Make it return uint32_t instead of 'int'.
* Add an AAC_GET_MAILBOX() macro and change AAC_GET_MAILBOXSTATUS() to use
that.
* Update the Dell PERC 2QC quirk code to use AAC_GET_MAILBOX instead of the
StrongARM-specific code. While StrongARM access is correct for that card,
it's a bad example of how to access the mailbox registers.
* Add the GETINFO command and use it to get and display the card's
supported options at a verbose level during attachment.
