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47774 Commits

Author SHA1 Message Date
ad d3b40a28c7 - lapic_map: if we have an APIC MSR, ignore the supplied address and ask the 
hardware where it is mapped. At least one ACPI implementation seems to lie
  about the physical address of the lapic.

- lapic_initclocks: be paranoid and issue an EOI.
 2008-05-12 23:46:01 +00:00
ad ce85d1b2a3 Some defs to describe the IA32_APIC_BASE MSR. 2008-05-12 18:36:20 +00:00
he 80dcfefbc7 Bump SYMTAB_SPACE so that it fits again. 2008-05-12 18:28:20 +00:00
tsutsui 6f98953d90 Remove one more dup line. I should have a cup of coffee before hasty commit.. 
XXX maybe it's better to sort by cai_desc to sync with the Intel docs.
 2008-05-12 16:41:15 +00:00
ad a1ba1eadd5 - Make cpu_number() return MI index, otherwise the pmap cannot work on 
systems with lapic IDs > X86_MAXPROCS.
- Kill cpu_info[] array and use MI cpu_lookup_byindex().
 2008-05-12 14:41:07 +00:00
ad 02ce2ed48b Don't crash if more than 32 cpus. Hopefully the boot processor will be 
within the first 32 attached.
 2008-05-12 14:29:06 +00:00
ad 453d5d4dc1 - Complain if unable to reset the lapic ID. 
- Minor clean up.
 2008-05-12 14:19:33 +00:00
ad 094788ba6d cpu_hatch: hack around problem with multiple CPUs spinning in i8254_delay. 2008-05-12 11:58:10 +00:00
nisimura ba7dbc0c82 CAL cache alignment band-aid for BMR register. 2008-05-12 11:56:15 +00:00
mlelstv 17740d28a4 add support for booting a kernel by tftp. Syntax is similar 
to other systems, e.g.: boot net tftp:netbsd
 2008-05-12 11:16:31 +00:00
nisimura 21ef04a5a6 sprincle volatile attribute for struct desc on memory to ease the 
target HW dependency on cache characteristic and load-store
serialization, and GCC compile time optimization strength.
 2008-05-12 09:58:36 +00:00
nisimura 3352c438fc Assign copyright notices. 2008-05-12 09:29:56 +00:00
simonb ce7bd7383b Only need to add some of the new cache descriptors once(!). 2008-05-12 03:58:47 +00:00
he d565d6ce16 Bump SYMTAB_SPACE so it fits again. 2008-05-11 23:34:40 +00:00
cegger 79c3bfd61b remove one indent level. No functional change. 2008-05-11 23:05:45 +00:00
yamt bf5accf9f6 tprof_backend_estimate_freq: ci_tsc_freq -> ci_data.cpu_cc_freq 2008-05-11 22:51:02 +00:00
ad 31c3804afc - Decouple the APIC ID from cpu_info[]. 
- Probe TSC frequency on each AP when hatching.
 2008-05-11 22:26:59 +00:00
ad 0dc71691a0 Fix the qemu (?) problem. 2008-05-11 22:18:08 +00:00
ad fff73dae94 splclock -> splhigh 2008-05-11 21:50:06 +00:00
ad 704c817f7a Use ci_cpumask. 2008-05-11 21:48:02 +00:00
cegger c094da181a print L3 and TLB cache information for AMD Barcelona/Phenom 2008-05-11 21:19:17 +00:00
tsutsui f256c15ff3 Update intel_cpuid_cache_info as per Intel's application note: 
"AP-485 Intel(R) Processor Identification and the CPUID Instruction"
http://www.intel.com/design/processor/applnots/241618.htm

XXX1: should sort by cai_index or cai_desc?
XXX2: should also check L3CACHE for coloring?
 2008-05-11 18:29:42 +00:00
tsutsui ce7c3e5d1c Fix an indent. 2008-05-11 18:21:28 +00:00
ad 9188c0738a Wrap stuff in #ifdef _KERNEL 2008-05-11 16:57:43 +00:00
ad a034c1c5e1 MP + apics are needed now so kill the #ifdefs 2008-05-11 16:26:56 +00:00
ad bfff830416 Fix typo. 2008-05-11 16:25:46 +00:00
ad b698c03c2c Don't reload LDTR unless a new value, which only happens for USER_LDT. 2008-05-11 16:23:05 +00:00
ad 5e605a64f7 Disable preemption across LDT mods. 2008-05-11 16:17:38 +00:00
ad 8250c8f097 Disable preemption over LDT modifications. 2008-05-11 16:13:34 +00:00
ad 3cd3c8ccbc Stop using APIC IDs to identify CPUs for software purposes. Allows for 
APIC IDs beyond 31, which has been possible for some time now.
 2008-05-11 15:59:50 +00:00
ad f674d9678b Share cpu.h between the x86 ports. 2008-05-11 15:32:20 +00:00
ad c5fb1571ad Update xen for identcpu changes. 2008-05-11 15:02:34 +00:00
ad 50d8ae9d14 Simplify x86 identcpu code, and share between i386/amd64. 2008-05-11 14:44:53 +00:00
ad 454ba0bbef Don't abuse ci_cpuid - in particular, ci_cpuid != ci_signature. 2008-05-11 14:39:49 +00:00
ad f9a4f0750a Don't use ci_apicid to identify cpus in debug output. 2008-05-11 14:25:02 +00:00
ad 058b47f572 Re-base the cpu types at 0 so they can be used as an array index. 2008-05-11 13:36:33 +00:00
ad da5bd37a49 Expose the 'cpu' variable.: 2008-05-11 13:33:54 +00:00
joerg 1ae05b2bbf Don't use the legacy interrupt when deciding how to route IOAPIC pins. 
On some modern systems not all devices have the PCI interrupt line
set, typically the cardbus bridge is affected and it would result in
different interrupt vectors used for the same IOAPIC pin.
To allow this, simplify the code by checking for an existing match first
and only allocate a new entry if that doesn't exist. For the IOAPIC case
don't bother with the reserveration on the primary CPU for ISA
interrupts, just use them.
 2008-05-11 13:18:25 +00:00
ad cc7aa65fd4 +END(tsc_get_timecount) 2008-05-11 12:43:35 +00:00
ad bd06c33f6e Fix a potential hang during skew detection (not observed). 2008-05-11 12:41:13 +00:00
chris e4ea82cddb Add support to pxeboot to allow the loading of modules. Changes to main.c 
are taken from boot/boot2.c.

This allows an install to be started by running:
load tftp:miniroot.kmod
boot tftp:netbsd-GENERIC

Note that the change to dev_net.c to comment out the network shutdown,
suggests we need to hook the network shutdown in the the common exec code.
If the network is shutdown, it fails to reinitialise and so fails to load
the module.
 2008-05-11 11:42:02 +00:00
isaki e33e7d58fd Increase ramdisk size. 2008-05-11 09:35:53 +00:00
cegger 2a9c1861c0 aprint_normal -> aprint_normal_dev 
sizeof line -> sizeof(line)
 2008-05-11 09:31:49 +00:00
kiyohara 2438bca8bf Split device_t/softc. 2008-05-11 08:23:17 +00:00
wrstuden 97003b024b Oops. These are supposed to come alive on the branch, not the head. 2008-05-11 00:18:09 +00:00
wrstuden dbbab92bc9 Initial checkin of re-adding SA. Everything except kern_sa.c 
compiles in GENERIC for i386. This is still a work-in-progress, but
this checkin covers most of the mechanical work (changing signalling
to be able to accomidate SA's process-wide signalling and re-adding
includes of sys/sa.h and savar.h). Subsequent changes will be much
more interesting.

Also, kern_sa.c has received partial cleanup. There's still more
to do, though.
 2008-05-10 23:48:44 +00:00
skrll 06decd2786 Add a cdboot prog. 
Derived from OpenBSD.
 2008-05-10 19:11:58 +00:00
skrll a4c3fd710b Fix some debug printfs. 2008-05-10 19:05:59 +00:00
ad bd60b91d0a If the boot processor's lapic has the wrong ID, reset it. 2008-05-10 17:23:54 +00:00
ad 47f99407d1 Assume that TSC is stable on P-II and P-III Xeons, since systems with those 
CPUs are likely to have a TSC-friendly configuration.
 2008-05-10 16:44:00 +00:00