same interrupt, and something isn't quite right with the mace interrupt
dispatcher. Disable for now.
Pointed out by Tillman Hodgson and confirmed by ozone on port-sgimips.
drivers that attach to it. This allows for other host interface chips
that use the same keyboards and mice, such as the ones in the ARM
IOMD20, ARM7500, and SA-1111. The PC-compatible driver is still
called pckbc(4), and the new abstraction layer is "pckbport", so the
child devices have moved from sys/dev/pckbc to sys/dev/pckbport, which
also contains some code shared between all host controllers. To avoid
incompatibility, pckbdreg.h is still installed in
/usr/include/dev/pckbc.
In theory, this shouldn't cause any behavioural changes in the drivers
concerned. Thy just use rather more function pointers than before. Tested
on i386 and (with a new host driver) acorn32. Compiled on several other
affected architectures.
interrupts and timer calibration yet is also attached at mainbus).
Introduce the INDY_R4600_CACHE config option, which more accurately describes
the code enabled by this option.
This renders #ifdef IPxx completely obsolete, thus we theoretically can unify
the GENERIC files if a workable load address relocation scheme can be found.
mace devices to their own mace/ directory. Alter conf/files.sgimips to
reflect this change in a sane manner (i.e., pull in dev/files.dev and
mace/files.mace when appropriate).
At the same time, allow crime_intr_establish() to fall through to
mace_intr_establish(). mace devices now call cpu_intr_establish().
(with several cosmetic changes by me) which fixes O2 (IP32) support.
Now my R5000 O2 works fine in multiuser with on-board AIC7880 SCSIs
and several PCI network cards (but only on serial console yet).
L2 cache on R5000/Rm5200 is still disabled for now, but it will be
fixed later, hopefully.
See recent discussion on port-sgimips for details.
which is automatically included during kernel config, and add comments
to individual machine-dependant majors.* files to assign new MI majors
in MI file.
Range 0-191 is reserved for machine-specific assignments, range
192+ are MI assignments.
Follows recent discussion on tech-kern@
