Commit Graph

392 Commits

Author SHA1 Message Date
toshii
4866f1a22b Fix typo. s/extention/extension/ 2001-07-05 08:38:24 +00:00
thorpej
5291142217 Determine the size of the B-Cache earier, and initialize the
number of page colors accordingly.
2001-05-02 01:24:29 +00:00
ross
2df695b1e4 o IEEE 754 floating-point completion code.
o Implement the architected FP_C "Floating Point Control Quadword"
2001-04-26 03:10:44 +00:00
thorpej
a51a1d8cdd - Get rid of the prot bits in the mem_clusters[] array when
reserving RAM in the bus_mem extent map.  Problem pointed
  out by Artur Grabowski.
- Work around a slightly annoying bit of behavior exhibited by
  the UP1000 firmware.  The UP1000 firmware reports the space
  consumed by the "ISA hole" in the same MDDT entry as two
  chunks of RAM (on either side of the hole) used by the PALcode,
  all as one "reserved for PALcode" chunk.  We must take this
  into account when reserving RAM in the bus_mem extent map.
2001-04-17 21:52:00 +00:00
ross
e84bc939c9 On alternate Tuesdays, SRM uses a different method of identifying
PCI interrupts routed to the ISA ICU.
2001-03-27 01:39:51 +00:00
ross
5b36d84a9c Don't panic until DEFCON 1. 2001-03-25 06:38:50 +00:00
cgd
82f3142780 fix NetBSD RCS id tags 2001-02-27 19:04:39 +00:00
thorpej
db36913c87 The code that creates/destroys SGMAP DMA maps is the same; put it
in a common place and share it.
2001-01-03 19:15:59 +00:00
sommerfeld
851de295eb Change pci_intr_map to get interrupt source information from a "struct
pci_attach_args *" instead of from four separate parameters which in
all cases were extracted from the same "struct pci_attach_args".

This both simplifies the driver api, and allows for alternate PCI
interrupt mapping schemes, such as one using the tables described in
the Intel Multiprocessor Spec which describe interrupt wirings for
devices behind pci-pci bridges based on the device's location rather
the bridge's location.

Tested on alpha and i386; welcome to 1.5Q
2000-12-28 22:59:06 +00:00
thorpej
f363b73f87 Add support for the AlphaServer 2100 (Sable) and the AlphaServer 2100A
(Lynx), written from scratch by me over a year ago, but never committed
to the tree because there was a bug I could never quite find.  I have
fixed a few problems in the code, but still don't know if that bug is
quite fixed.  Since I don't have access to the hardware directly, I'll
have to call for testers again.
2000-12-21 20:51:53 +00:00
thorpej
ad4f387a4c Put back the INITIALLY_{ENABLED,LEVEL_TRIGGERED}() PROM brain-damage
work-around.  It's required in order for the DEC Multia (a very
brain-damaged little machine) to work properly.

Submitted by Juergen Weiss <weiss@uni-mainz.de>, addresses
port-alpha/11202.
2000-12-18 21:49:08 +00:00
thorpej
5f3a256833 Allocate the DMA windows out of the PCI memory extent map after
DMA is initialized.
2000-11-29 06:30:09 +00:00
thorpej
96294f7b26 Do the additional PCI memory initialization after configuring DMA. 2000-11-29 06:29:10 +00:00
thorpej
8f20972db2 Revert previous -- we'll do it differently. 2000-11-29 06:21:12 +00:00
thorpej
d615083897 The AMD 751 doesn't have DMA windows, so allocate the RAM out of the
PCI memory extent map.  Bad things will happen if we try to assign
a device where RAM is mapped into PCI space.
2000-11-29 05:56:49 +00:00
thorpej
8ebabb1aae Increase the number of static extent descriptors from 8 to 16,
and add a means for calling a chip-specific init hook.
2000-11-29 05:53:29 +00:00
thorpej
73265fa0c9 Duh, don't need SGMAP-related includes on this chipset. 2000-11-18 05:56:20 +00:00
thorpej
d760e0b407 Add code to read the EISA configuration NVRAM as set up by
an EISA Configuration Utility.  Code to access this data
is forthcoming.

XXX This could probably be made MI at some point.
2000-07-29 23:18:46 +00:00
thorpej
1204c1faaf Oops, treat 2100A_A500 just like 2100_A500 in every place necessary. 2000-07-12 21:02:14 +00:00
thorpej
249773b538 Deal with another odd need of the Sable/Lynx systems, which need to
have an ISA chipset present before the PCI-EISA bridge has been
attached (because the STDIO module has an ISA DMA-using device,
the floppy controller, connected to it).
2000-07-12 20:50:00 +00:00
mrg
c88e94a407 remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h> 2000-06-29 08:58:45 +00:00
thorpej
69a6fe113c Garbage-collect CHIP_PHYSADDR(). 2000-06-26 19:46:24 +00:00
thorpej
cc9dfe871b Do the previously slightly differently, to avoid confusing the internal
space extent maps.  Pointed out by msaitoh@netbsd.org.  (Someone should
send me an EV6 machine!)
2000-06-26 18:19:26 +00:00
thorpej
9a2d9ff68b Because of the Cool sign-extension hack we use to access PCI space,
the `get window' method ends up with the wrong physical address to
pass onto userspace (which wants to mmap the space).

Compensate by adding a CHIP_PHYSADDR() macro which un-hacks the address
suitably for mapping with other-than-KSEG.
2000-06-26 02:42:10 +00:00
thorpej
a2318e49a0 G/c unused include. 2000-06-25 19:33:01 +00:00
thorpej
167094d31a Implement mcpcia_bus_get_window(). 2000-06-25 19:32:19 +00:00
thorpej
865004842f Implement tsp_bus_get_window(). 2000-06-25 19:17:39 +00:00
thorpej
fe8841f18a Some platforms, like the Sable, hook EISA and ISA interrupts
up Very Differently.  Handle this.
2000-06-13 16:40:37 +00:00
thorpej
75975dd6c5 G/c some unneeded prototypes (functions don't exist). 2000-06-11 22:47:00 +00:00
thorpej
f3d9d1ac8a Use the common 82c693 access functions to read/write the ELCR. 2000-06-06 03:10:13 +00:00
thorpej
f65502fc36 Report which compatibility IRQ the PCI IDE gets. 2000-06-06 00:50:15 +00:00
thorpej
b0ce38fd8a Switch to the new `evcnt' mechanism for counting interrupts. Maintain
a per-CPU interrupt counter for clock, device, and interprocessor
interrupts.
2000-06-05 21:47:26 +00:00
thorpej
2668e3b213 Switch to the new `evcnt' mechanism for counting interrupts. Maintain
a per-CPU interrupt counter for clock, device, and interprocessor
interrupts.
2000-06-05 21:47:10 +00:00
cgd
cffb580806 Implement the more flexiable `evcnt' interface as discussed (briefly) on
tech-kern and now documented in evcnt(9).
2000-06-04 19:14:14 +00:00
thorpej
9851571246 Add support for the Alpha Processor, Inc. UP1000 EV6 system. 2000-06-01 20:30:28 +00:00
drochner
13c9f8d398 implement bus_space_vaddr() 2000-04-17 17:24:48 +00:00
thorpej
156114a02f Use the new cpu_amask variable rather than calling alpha_implver() and
alpha_amask() ourselves.
2000-04-03 01:48:07 +00:00
thorpej
f785596e75 Add support for mapping the OHCI USB controller interrupt (which is wired toan ISA IRQ because it's in the same package as the PCI-ISA bridge). 2000-03-19 02:25:29 +00:00
thorpej
c10a9d31ea Put the code that enables/disables Pyxis interrupt lines in
cia_pyxis_intr_enable().
2000-03-19 01:43:25 +00:00
mycroft
cf3085176e Nuke all the code associated with the INITIALLY_LEVEL_TRIGGERED() lossage, and
instead register a shutdownhook to restore the PIC state.
2000-02-27 02:50:31 +00:00
thorpej
df88882d80 - Add a bus space method for getting the translation for a window.
- Add sysarch methods for "get bus window count", "get bus window",
  and "pci conf read/write".

These are a hack, but they're what's necessary in order to make
XFree86 work in its current state.
2000-02-26 18:53:10 +00:00
thorpej
de974ff82d Add an internal bus space method alpha_bus_space_translate(), which
provides a method to translate an address on an I/O bus into a sysBus
address, along with acccess method information.
2000-02-25 00:45:04 +00:00
mjacob
9621e6be50 Reset maxstray count if we get a good interrupt for a level. 2000-02-10 07:45:43 +00:00
mjacob
4821b5ae2f Guard against trying to disable an interrupt where we'd dereference a
bad pointer.
2000-02-10 04:31:36 +00:00
thorpej
f9e531f1e4 Don't force BWX on Pyxis by default; it's just not reliable enough. 2000-02-09 01:39:20 +00:00
thorpej
17c346b9e1 Changed cacheable -> prefetchable. [sync w/ swiz] 2000-02-06 04:07:18 +00:00
elric
28bdaf37d9 Changed cacheable -> prefetchable. 2000-02-06 03:52:27 +00:00
thorpej
97eba73a40 If we have a Pyxis with the DMA page crossing bug, don't allow coalescing
of adjacent DMA segments.

XXX This is still not perfect... but making it perfect will probably
require additions to the bus_dma interface and the ISA autoconfiguration
interface.
2000-02-06 01:26:50 +00:00
thorpej
0cf304bb45 Always use BWX for bus access on Pyxis chips. 2000-02-01 19:29:28 +00:00
thorpej
35f3518a91 Fix a fatal typo in a Pyxis SGMAP TLB bug workaround. Noticed by
Jeff Roberson <nomad@nop.aliensystems.com>.
2000-01-25 03:32:36 +00:00