Commit Graph

3332 Commits

Author SHA1 Message Date
manu af39a49700 iWorkaround panic: fpudna from userland
i386 Xen PV domU get spurious fpudna traps from userland. Older eager FPU
contact switching code took care of ignoring them. When transitioning
from eager switching to awlays switching, this special handling was
removed, causing "fpudna from userland" panics.

This change restores the previosu behavior where fpudna traps from
userland are ignored on Xen PV domU.
2024-05-17 00:37:14 +00:00
msaitoh 8db4a15828 s/RPMQUERY/RMPQUERY/ 2024-05-12 23:41:10 +00:00
pho 3dc92541ec port-arm/58194: Resurrect vmt(4) from bitrot
On this architecture vmt(4) used to search for a node "/hypervisor" in the
FDT and probed the VMware hypervisor call only when the node was
found. However, things appear to have changed and VMware no longer provides
the FDT node.

Since vmt(4) doesn't actually need to read anything from FDT, and the
hypervisor call logically resides in virtual CPUs themselves, it would be
better to attach it directly to cpu, just like how it's probed on x86.
2024-05-09 12:09:58 +00:00
andvar 4412324be5 viac7temp(4): rewrite temperature sensor to read value from MSR instead of using
documented cpuid instruction and eax register.

This approach is adapted from linux via-cputemp.c, no official documentation is
currently available. However, msr value seems to work on all tested CPUs while
documented cpuid instruction typically reports 0, even for my C7-D CPU.
msr value seems to have temperature in Celsius in lower 24-bits without fraction
(thus "msr & 0xffffff;" is used).

Tested on my personal systems based on CPUs below (i386 and amd64):
C7-D 1.6GHz (i386 only), Nano X2 L4350E, Nano X2 U4300, U2300 Nano, KX-U6580.
Also got one response via email which was based on Nano X2 L4050 (VE-900).
Nano reports independent values for each core.
KX-U6580 seems to show the same value for all cores but more testing is needed.

Since it works on amd64 capable CPUs, adding driver to GENERIC kernel config.
Also moving viac7temp man page to x86 instead of i386 (with updates).
In theory the change should add support for all VIA Nano CPUs and Zhaoxin CPUs
 at least up to KX-6000(G) series.

In the future I may need to introduce amd64 kernel module as well.

Plan to pullup to at least netbsd-10.

Patch mainly reviewed by riastradh.
2024-04-30 19:35:28 +00:00
andvar f1e8be7f86 Make dwiic_pci compile without ACPI option. 2024-04-29 21:29:48 +00:00
andvar 1f05e87cf6 Surround full mp_cpu_start() method with NLAPIC > 0 guard.
Initialization is based on x86_ipi* functions, which are implemented only
when lapic flag is enabled.
2024-04-22 23:07:47 +00:00
andvar ac38f996f2 Add opt_pci.h include to fix NO_PCI_MSI_MSIX build.
(Path from Paolo Pisati in current_users@)

While here:
Simplify mp_cpu_start() ifdefs. MULTIPROCESSOR and HYPERV code falls under
NLAPIC > 0, thus just combine all blocks under this guard.
Rearrange opt_acpi.h include alphabetically.
2024-04-22 22:29:28 +00:00
andvar 75ed7a9075 viac7temp(4): define module metadata using MODULE() macro and implement
viac7temp_modcmd() to handle module load/unload events.

Fixes PR kern/58148. Look OK by mrg@.

XXX pullup-10, -9, -8
2024-04-13 09:12:09 +00:00
gutteridge 868624973a coretemp.c: don't accept impossibly low TjMax values
r. 1.39 introduced a regression where instead of applying a reasonable
default maximum (as was done prior to that change), incorrect values
were accepted and applied, as failures to retrieve an expected MSR
value weren't accounted for.

Apply different logic for unexpectedly low vs. high maximums, with
distinct warnings for each. Also add another warning about a retrieval
failure right at the outset (which also just uses the default, then).

This change fundamentally doesn't address the fact that
__SHIFTOUT(msr, MSR_TEMP_TARGET_READOUT)
doesn't necessarily return a valid value. It just restores prior
behaviour, which is more reasonable than applying a zero value, which
started happening on some older hardware. (I infer this is most likely
an issue with dated generations of Intel hardware with this feature.)
The challenge is that this evidently isn't all documented properly
anywhere. Various "magic values" in this driver need further
investigation.

While here, also fix output so warnings are cleanly formatted, rather
than the slightly scrambled way they were appearing.

Tested on older Intel hardware I had on hand:
E7500 (now falls back to default 100 rather than 0)
E5540 (successfully retrieves 97, as before)
i5-3340M (successfully retrieves 105, as before)
2024-03-12 02:26:16 +00:00
rillig 88b554245c cpuctl: fix i386 bit descriptions for CPUID_SEF_FLAGS1
warning: non-printing character '\31' in description
    'BUS_LOCK_DETECT""b\31' [363]
2024-03-08 20:29:17 +00:00
andvar bfb11cbc46 Remove duplicate "when" word in comments. 2024-03-05 20:58:05 +00:00
gutteridge 3a6a773486 coretemp.c: fix grammar in a warning message
(I get several of these warnings on boot on a particular machine. Now,
it also seems that the code isn't retrieving the correct value, either;
TBD.)
2024-02-29 01:59:11 +00:00
andvar 45f271b64e s/asynchronious/asynchronous/ in comment. 2024-02-25 18:27:54 +00:00
mrg 0eb69f6831 remove unintended printf() in previous. (thx dh) 2024-02-19 20:10:09 +00:00
mrg 45b5946451 make TSC get a quality of -100 on AMD Family 15h and 16h
this should "fix" PR#56322 and is known as AMD errata
"778: Processor Core Time Stamp Counters May Experience Drift"
2024-02-19 09:22:31 +00:00
andvar 7715c10d42 s/musn't/mustn't/ in comments. 2024-02-10 09:24:17 +00:00
andvar 100a3398b8 fix spelling mistakes, mainly in comments and log messages. 2024-02-09 22:08:30 +00:00
christos c37dd69b0b use sized types 2024-01-02 19:28:25 +00:00
dholland ba8892948d {x86,m68k}/float.h: document LDBL_MIN behavior
It seems that even though both these platforms have 12-byte floats
that are pretty much the same representation and both allegedly
IEEE-compliant, they manifest the top bit of the mantissa and then
differ slightly in the behavior of the extra encodings this permits.

Thanks to riastradh@ for helping sort this out.
2023-12-31 04:20:40 +00:00
andvar 5e4abe6a3f fix triple s typos in comments. 2023-12-08 21:46:02 +00:00
mlelstv 3bcce0b38e Fix use-after-free (source->is_type) when detecting unsharable
interrupts. Doesn't solve the interrupt conflict itself, but
avoids a panic.
2023-11-29 11:40:37 +00:00
gutteridge 0a4cb760d3 pci_machdep.c & pci_msi_machdep.c: comment fixes
Correct spelling and grammar in some comments.
2023-11-21 23:22:23 +00:00
mrg 77154681c3 add MSR stuff for AMD errata 1474. 2023-10-27 06:31:48 +00:00
mrg cb3c2134d1 x86: handle AMD errata 1474: A CPU core may hang after about 1044 days
from the new comment:

 * This requires disabling CC6 power level, which can be a performance
 * issue since it stops full turbo in some implementations (eg, half the
 * cores must be in CC6 to achieve the highest boost level.)  Set a timer
 * to fire in 1000 days -- except NetBSD timers end up having a signed
 * 32-bit hz-based value, which rolls over in under 25 days with HZ=1000,
 * and doing xcall(9) or kthread(9) from a callout is not allowed anyway,
 * so just have a kthread wait 1 day for 1000 times.

documented in:

 https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/revision-guides/56323-PUB_1_01.pdf
2023-10-27 05:45:00 +00:00
mrg f802e6d8ff x86: add names for errata that don't have actual numbers
zenbleed is reported as "erratum 65535" currently, this adds a name
for it, and enables the name for any others as well.

pull logging into a function with a tag message.
2023-10-27 03:06:04 +00:00
bouyer 8fc4e4bb10 Move definition of acpi_md_vesa_modenum to acpi_wakeup.c; allows building
kernels without framebuffer devices.
Problem reported by John D. Baker on current-users@
2023-10-19 14:59:46 +00:00
bouyer 40f65bebd2 XENPVH option is not used. Fix consinit.c to use XENPVHVM as intended
and XENPVH from defflag
2023-10-17 16:06:36 +00:00
riastradh cdc4815373 Revert "x86: Panic early if fpu save size is too large, take 2."
Apparently this is too early to print anything useful, so it just
causes a reboot loop.

PR kern/57661
2023-10-17 14:17:42 +00:00
bouyer 4a96dd4fc2 Support non-VGA framebuffers for Xen dom0. This is mandatory for graphic
console on EFI-only hardware.
Add a xen_genfb_getbtinfo() function which will return a btinfo_framebuffer
    structure, filled in with parameters provided by Xen
when runing as a Xen dom0, call xen_genfb_getbtinfo() instead of
    lookup_bootinfo(BTINFO_FRAMEBUFFER) when adding properties to the
    PCI graphic device (when genfb is attached) and in x86_genfb_init()
    when genfb is used as console.
x86/x86/consinit.c: If running as a Xen dom0, use xen_genfb_getbtinfo()
    to check if we have a genfb console
xen/x86/consinit.c: support genfb as possible console
xen/x86/consinit.c: use the hypervior IO as console until a better one
    is found. If the hypervisor is using a serial port for boot messages,
    we'll get NetBSD's boot message on the serial port too until
    the real console takes over.
xen/x86/autoconf.c: rework device_register() to be closer to the x86 version.
    Especially make sure that device_pci_register() is called.
2023-10-17 12:07:42 +00:00
riastradh bc3e6261c6 x86: Panic early if fpu save size is too large, take 2.
This shouldn't break any existing systems (for real this time), but
it should make the failure mode more obvious on systems that are
already broken.

PR kern/57661

XXX pullup-10
XXX pullup-9
XXX pullup-8
2023-10-17 11:12:33 +00:00
riastradh 5fc6b35a2a x86: Remove incomplete fpu save size check.
Will fix it later, but this makes pullups easier.
2023-10-17 11:11:49 +00:00
bouyer 98f1f45391 Declare
int acpi_md_vesa_modenum;
int acpi_md_vbios_reset;
struct vcons_screen x86_genfb_console_screen;

in genfb_machdep.h instead of locally as extern in various .c files.
2023-10-16 17:27:02 +00:00
riastradh f43d314ebb x86: Disable savefpu size check for now.
This is apparently so broken that the error check for what should
have been a safe size fails, which is breaking boot on x86 all the
way back to Sandy Bridge at this point.  Grrr.

We need to expand savefpu so that it supports the maximum size
instead.
2023-10-15 16:11:22 +00:00
riastradh 7cc2cc1249 x86: Panic if cpuid's fpu save size is larger than we support.
Ideally this wouldn't panic, but the alternative right now is to
crash in a memset later -- or silently corrupt kernel memory -- so
this doesn't make the situation worse than it was before.

PR kern/57661

XXX pullup-10
XXX pullup-9
XXX pullup-8
2023-10-15 13:13:22 +00:00
skrll d40146f873 Convert the l2->l_md.md_astpending assignments into KASSERTs.
l_md is zeroised by lwp_create with

         memset(&l2->l_startzero, 0, sizeof(*l2) -
                    offsetof(lwp_t, l_startzero));
2023-10-06 11:53:26 +00:00
ad 68fa584377 Arrange to update cached LWP credentials in userret() rather than during
syscall/trap entry, eliminating a test+branch on every syscall/trap.

This wasn't possible in the 3.99.x timeframe when l->l_cred came about
because there wasn't a reliable/timely way to force an ONPROC LWP running on
a remote CPU into the kernel (which is just about the only new thing in
this scheme).
2023-10-05 19:41:03 +00:00
ad a355028fa4 Eliminate l->l_ncsw and l->l_nivcsw. From memory think they were added
before we had per-LWP struct rusage; the same is now tracked there.
2023-10-04 20:28:05 +00:00
christos 5652437218 protect against multiple inclusion 2023-09-16 13:37:10 +00:00
ad e5d38798d7 tsc_get_timecount(): cover the backwards check by DIAGNOSTIC since it has
proven the point by now.
2023-09-09 18:37:03 +00:00
riastradh 77901f27b5 xen: Provide definitions or ifdefs to make drm build in XEN3_DOM0.
No idea if it works, but it builds now.

PR port-xen/49330
2023-08-25 08:05:18 +00:00
msaitoh 3001bf9234 Update /proc/cpuinfo.
- Move "ssbd" to an unused Linux mapping.
 - Update unused Linux mappings.
2023-08-07 09:27:14 +00:00
msaitoh 690f64d68b Fix detection of availability of MSI/MSI-X on some systems.
Try to find all functions on bus 0, device 0 to find a PCI host bridge.
Some CPU's host bridge is at 0:0.4. Tested by Intel Snow Ridge.
2023-08-07 06:23:39 +00:00
riastradh 762dda02dd xen: Report when hardclock jump exceeds timecounter(9) limit. 2023-08-01 19:36:57 +00:00
mrg ae65bbf7c0 x86: make the CPUID list for errata be far less confusing
the 0x80000001 CPUID result needs some parsing to match against
actual family/model/stepping values.  4-bit 'family' values of
15 or 6 change how to parse the 4-bit extended model and 8-bit
extended family value - for family 6 or 15, the extended model
bits (4) are concatenated with the base 4-bits to create an
8-bit value, and for family 15, the family value is addition
of the family value and the 8-bit extended-family value, giving
a range of 0 to 15 + 0xff aka 270.

use a CPUREV(family, model, stepping) macro that builds the
relevant bit-representation of a CPUID, making it far easier
to understand what each entry means, and to add new ones too.

i have confirmed that the emitted cpurevs[] array has the same
values before/after this change, ie, NFCI or observed.
2023-07-28 05:02:13 +00:00
msaitoh 1b9c9e4ea1 Add Zen4 Phoenix support. 2023-07-28 02:28:33 +00:00
msaitoh b39e984dd8 Add Zen2 Mendocino APU support. 2023-07-28 02:05:26 +00:00
msaitoh f2d8fd5032 Add Zen4 Ryzen "Phoenix" support. 2023-07-28 00:11:15 +00:00
msaitoh 3a03d8aff6 Add AMD IBPB_RET and BusLockThreshold. 2023-07-27 00:34:07 +00:00
riastradh fcc4e284a5 x86/pmap: Print quantities in failed assertions in pmap_load. 2023-07-26 21:45:28 +00:00
mrg c26e77ddaa fix the cpuids for the zen2 client CPUs.
i'm not exactly how i came up with the values i had, though one
of them was still valid and matched my test systems.

XXX: pullup-*
2023-07-26 00:19:04 +00:00