Commit Graph

5 Commits

Author SHA1 Message Date
simonb 1b968d3ccf #define<tab>
Nuke trailing whitespace.
2020-07-26 08:08:41 +00:00
simonb 8101407b8a Define Octeon Cavium cache layouts for various cnMIPS cores. 2020-06-14 08:43:07 +00:00
simonb 991dc94f90 Fix tyop. 2019-04-11 09:18:55 +00:00
matt d7e78fcfd1 Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
2016-07-11 16:15:35 +00:00
hikaru f693c92206 Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.
2015-04-29 08:32:00 +00:00