6 Commits

Author	SHA1	Message	Date
simonb	1b968d3ccf	#define<tab> ... Nuke trailing whitespace.	2020-07-26 08:08:41 +00:00
matt	d7e78fcfd1	Change MIPS to use the common pmap code. ... Switch to 8KB pages on CPUs with a R4K MMU. Simplify cache code. Merge in most of changes from matt-mips64 branch	2016-07-11 16:15:35 +00:00
simonb	8883b06039	No need to protect headers with #ifdef _KERNEL if they're never installed ... in /usr/include.	2003-02-17 11:35:01 +00:00
simonb	12c35ee2d2	New generic way-aware MIPS32/64 range-index cache functions with proper ... handling for phyiscally-indexed caches where the way size is greater than the page size. These work fine with pass 1 SB1 cores, so g/c those workarounds. Much thanks to Chris Demetriou for many suggestions and helping me get my head around all this.	2002-11-24 07:41:29 +00:00
simonb	67fd901d75	Include 2way cache ops for mips{32,64} CPUs.	2002-04-03 03:51:00 +00:00
simonb	cae6e0e516	Prototypes for MIPS32/64 cache ops.	2002-03-05 15:41:48 +00:00