From ffb2012cee6f87d08aff54e86bf890bb5ffe7b17 Mon Sep 17 00:00:00 2001 From: cgd Date: Thu, 3 Aug 1995 00:52:00 +0000 Subject: [PATCH] MB -> wbflush --- sys/arch/alpha/tc/asic.c | 10 ++--- sys/arch/alpha/tc/esp.c | 89 +++++++++++++++++++------------------- sys/arch/alpha/tc/espvar.h | 6 +-- sys/arch/alpha/tc/if_le.c | 10 ++--- sys/arch/alpha/tc/scc.c | 12 ++--- sys/arch/alpha/tc/sccvar.h | 4 +- 6 files changed, 66 insertions(+), 65 deletions(-) diff --git a/sys/arch/alpha/tc/asic.c b/sys/arch/alpha/tc/asic.c index 7a3c61cae196..f571c4732fae 100644 --- a/sys/arch/alpha/tc/asic.c +++ b/sys/arch/alpha/tc/asic.c @@ -1,4 +1,4 @@ -/* $NetBSD: asic.c,v 1.4 1995/06/28 01:03:57 cgd Exp $ */ +/* $NetBSD: asic.c,v 1.5 1995/08/03 00:52:00 cgd Exp $ */ /* * Copyright (c) 1994, 1995 Carnegie-Mellon University. @@ -140,7 +140,7 @@ asicattach(parent, self, aux) if (cputype == ST_DEC_3000_300) { *(volatile u_int *)ASIC_REG_CSR(sc->sc_base) |= ASIC_CSR_FASTMODE; - MB(); + wbflush(); printf(": slow mode\n"); } else #endif @@ -243,9 +243,9 @@ asic_intr(val) gifound = 0; do { ifound = 0; - MB(); + wbflush(); MAGIC_READ; - MB(); + wbflush(); sir = *sirp; for (i = 0; i < ASIC_MAX_NSLOTS; i++) @@ -285,7 +285,7 @@ flamingo_set_leds(value) */ *(volatile u_int *)ASIC_REG_CSR(sc->sc_base) &= ~0x7f; *(volatile u_int *)ASIC_REG_CSR(sc->sc_base) |= value & 0x7f; - MB(); + wbflush(); DELAY(10000); } #endif diff --git a/sys/arch/alpha/tc/esp.c b/sys/arch/alpha/tc/esp.c index 0647f2f1de4c..f2518cf558c0 100644 --- a/sys/arch/alpha/tc/esp.c +++ b/sys/arch/alpha/tc/esp.c @@ -1,4 +1,4 @@ -/* $NetBSD: esp.c,v 1.4 1995/07/24 07:18:27 cgd Exp $ */ +/* $NetBSD: esp.c,v 1.5 1995/08/03 00:52:06 cgd Exp $ */ /* * Copyright (c) 1994 Peter Galbavy @@ -142,9 +142,9 @@ espreadregs(sc) s = splhigh(); /* Only the stepo bits are of interest. */ - sc->sc_espstep = RR(esp->esp_step) & ESPSTEP_MASK; MB(); - sc->sc_espstat = RR(esp->esp_stat); MB(); - sc->sc_espintr = RR(esp->esp_intr); MB(); + sc->sc_espstep = RR(esp->esp_step) & ESPSTEP_MASK; wbflush(); + sc->sc_espstat = RR(esp->esp_stat); wbflush(); + sc->sc_espintr = RR(esp->esp_intr); wbflush(); /* Clear the TCDS interrupt bit. */ (void)tcds_scsi_isintr(sc->sc_dev.dv_unit, 1); @@ -166,7 +166,7 @@ espgetbyte(sc) u_int esp_fflag, esp_fifo; ESP_TRACE(("esp_getbyte ")); - esp_fflag = RR(esp->esp_fflag); MB(); + esp_fflag = RR(esp->esp_fflag); wbflush(); if (!(esp_fflag & ESPFIFO_FF)) { xxx: ESPCMD(sc, ESPCMD_TRANS); @@ -178,12 +178,12 @@ xxx: */ espreadregs(sc); } - esp_fflag = RR(esp->esp_fflag); MB(); + esp_fflag = RR(esp->esp_fflag); wbflush(); if (!(esp_fflag & ESPFIFO_FF)) { printf("error...\n"); goto xxx; } - esp_fifo = RR(esp->esp_fifo); MB(); + esp_fifo = RR(esp->esp_fifo); wbflush(); return esp_fifo; } @@ -210,20 +210,20 @@ espselect(sc, target, lun, cmd, clen) * The docs say the target register is never reset, and I * can't think of a better place to set it */ - esp->esp_id = target; MB(); - esp->esp_syncoff = sc->sc_tinfo[target].offset; MB(); - esp->esp_synctp = 250 / sc->sc_tinfo[target].period; MB(); + esp->esp_id = target; wbflush(); + esp->esp_syncoff = sc->sc_tinfo[target].offset; wbflush(); + esp->esp_synctp = 250 / sc->sc_tinfo[target].period; wbflush(); /* * Who am I. This is where we tell the target that we are * happy for it to disconnect etc. */ - esp->esp_fifo = ESP_MSG_IDENTIFY(lun); MB(); + esp->esp_fifo = ESP_MSG_IDENTIFY(lun); wbflush(); /* Now the command into the FIFO */ for (i = 0; i < clen; i++) { esp->esp_fifo = (u_int)*cmd++; - MB(); + wbflush(); } /* And get the targets attention */ @@ -398,27 +398,27 @@ espattach(parent, self, aux) #ifdef SPARC_DRIVER sc->sc_cfg2 = ESPCFG2_SCSI2 | ESPCFG2_RSVD; sc->sc_cfg3 = ESPCFG3_CDB; - sc->sc_reg->esp_cfg2 = sc->sc_cfg2; MB(); + sc->sc_reg->esp_cfg2 = sc->sc_cfg2; wbflush(); - esp_cfg2 = RR(sc->sc_reg->esp_cfg2); MB(); + esp_cfg2 = RR(sc->sc_reg->esp_cfg2); wbflush(); if ((esp_cfg2 & ~ESPCFG2_RSVD) != (ESPCFG2_SCSI2 | ESPCFG2_RPE)) { printf(": ESP100"); sc->sc_rev = ESP100; } else { sc->sc_cfg2 = 0; - sc->sc_reg->esp_cfg2 = sc->sc_cfg2; MB(); + sc->sc_reg->esp_cfg2 = sc->sc_cfg2; wbflush(); sc->sc_cfg3 = 0; - sc->sc_reg->esp_cfg3 = sc->sc_cfg3; MB(); + sc->sc_reg->esp_cfg3 = sc->sc_cfg3; wbflush(); sc->sc_cfg3 = 5; - sc->sc_reg->esp_cfg3 = sc->sc_cfg3; MB(); - esp_cfg3 = RR(sc->sc_reg->esp_cfg3); MB(); + sc->sc_reg->esp_cfg3 = sc->sc_cfg3; wbflush(); + esp_cfg3 = RR(sc->sc_reg->esp_cfg3); wbflush(); if (esp_cfg3 != 5) { printf(": ESP100A"); sc->sc_rev = ESP100A; } else { sc->sc_cfg3 = 0; - sc->sc_reg->esp_cfg3 = sc->sc_cfg3; MB(); + sc->sc_reg->esp_cfg3 = sc->sc_cfg3; wbflush(); printf(": ESP200"); sc->sc_rev = ESP200; } @@ -507,30 +507,30 @@ esp_reset(sc) /* ESP: do these backwards, and fall through */ switch (sc->sc_rev) { case NCR53C94: - esp->esp_cfg1 = sc->sc_cfg1; MB(); - esp->esp_cfg2 = sc->sc_cfg2; MB(); - esp->esp_cfg3 = sc->sc_cfg3; MB(); - esp->esp_ccf = sc->sc_ccf; MB(); - esp->esp_syncoff = 0; MB(); - esp->esp_timeout = sc->sc_timeout; MB(); + esp->esp_cfg1 = sc->sc_cfg1; wbflush(); + esp->esp_cfg2 = sc->sc_cfg2; wbflush(); + esp->esp_cfg3 = sc->sc_cfg3; wbflush(); + esp->esp_ccf = sc->sc_ccf; wbflush(); + esp->esp_syncoff = 0; wbflush(); + esp->esp_timeout = sc->sc_timeout; wbflush(); break; case ESP200: - esp->esp_cfg3 = sc->sc_cfg3; MB(); + esp->esp_cfg3 = sc->sc_cfg3; wbflush(); case ESP100A: - esp->esp_cfg2 = sc->sc_cfg2; MB(); + esp->esp_cfg2 = sc->sc_cfg2; wbflush(); case ESP100: - esp->esp_cfg1 = sc->sc_cfg1; MB(); - esp->esp_ccf = sc->sc_ccf; MB(); - esp->esp_syncoff = 0; MB(); - esp->esp_timeout = sc->sc_timeout; MB(); + esp->esp_cfg1 = sc->sc_cfg1; wbflush(); + esp->esp_ccf = sc->sc_ccf; wbflush(); + esp->esp_syncoff = 0; wbflush(); + esp->esp_timeout = sc->sc_timeout; wbflush(); break; default: printf("%s: unknown revision code, assuming ESP100\n", sc->sc_dev.dv_xname); - esp->esp_cfg1 = sc->sc_cfg1; MB(); - esp->esp_ccf = sc->sc_ccf; MB(); - esp->esp_syncoff = 0; MB(); - esp->esp_timeout = sc->sc_timeout; MB(); + esp->esp_cfg1 = sc->sc_cfg1; wbflush(); + esp->esp_ccf = sc->sc_ccf; wbflush(); + esp->esp_syncoff = 0; wbflush(); + esp->esp_timeout = sc->sc_timeout; wbflush(); } } @@ -720,7 +720,7 @@ espphase(sc) return BUSFREE_PHASE; if (sc->sc_rev != ESP100) { - esp_stat = RR(sc->sc_reg->esp_stat); MB(); + esp_stat = RR(sc->sc_reg->esp_stat); wbflush(); return (esp_stat & ESPSTAT_PHASE); } @@ -1143,10 +1143,10 @@ esp_msgin(sc) |= (1<lun); esp->esp_syncoff = sc->sc_tinfo[sc_link->target].offset; - MB(); + wbflush(); esp->esp_synctp = 250 / sc->sc_tinfo[sc_link->target].period; - MB(); + wbflush(); ESP_MISC(("... found ecb")); sc->sc_state = ESP_HASNEXUS; } @@ -1325,7 +1325,7 @@ espintr(__sc) || sc->sc_espstat & ESPSTAT_GE) { /* SCSI Reset */ if (sc->sc_espintr & ESPINTR_SBR) { - esp_fflag = RR(esp->esp_fflag); MB(); + esp_fflag = RR(esp->esp_fflag); wbflush(); if (esp_fflag & ESPFIFO_FF) { ESPCMD(sc, ESPCMD_FLUSH); DELAY(1); @@ -1338,7 +1338,7 @@ espintr(__sc) if (sc->sc_espstat & ESPSTAT_GE) { /* no target ? */ - esp_fflag = RR(esp->esp_fflag); MB(); + esp_fflag = RR(esp->esp_fflag); wbflush(); if (esp_fflag & ESPFIFO_FF) { ESPCMD(sc, ESPCMD_FLUSH); DELAY(1); @@ -1357,7 +1357,7 @@ espintr(__sc) /* illegal command, out of sync ? */ printf("%s: illegal command\n", sc->sc_dev.dv_xname); - esp_fflag = RR(esp->esp_fflag); MB(); + esp_fflag = RR(esp->esp_fflag); wbflush(); if (esp_fflag & ESPFIFO_FF) { ESPCMD(sc, ESPCMD_FLUSH); DELAY(1); @@ -1400,7 +1400,7 @@ espintr(__sc) if (sc->sc_espintr & ESPINTR_DIS) { ESP_MISC(("disc ")); - esp_fflag = RR(esp->esp_fflag); MB(); + esp_fflag = RR(esp->esp_fflag); wbflush(); if (esp_fflag & ESPFIFO_FF) { ESPCMD(sc, ESPCMD_FLUSH); DELAY(1); @@ -1510,7 +1510,8 @@ espintr(__sc) break; } else if (sc->sc_espintr & ESPINTR_FC) { if (sc->sc_espstep != ESPSTEP_DONE) { - esp_fflag = RR(esp->esp_fflag); MB(); + esp_fflag = RR(esp->esp_fflag); + wbflush(); if (esp_fflag & ESPFIFO_FF) { ESPCMD(sc, ESPCMD_FLUSH); DELAY(1); @@ -1551,7 +1552,7 @@ espintr(__sc) /* well, this means send the command again */ ESP_PHASE(("COMMAND_PHASE 0x%02x (%d) ", ecb->cmd.opcode, ecb->clen)); - esp_fflag = RR(esp->esp_fflag); MB(); + esp_fflag = RR(esp->esp_fflag); wbflush(); if (esp_fflag & ESPFIFO_FF) { ESPCMD(sc, ESPCMD_FLUSH); DELAY(1); diff --git a/sys/arch/alpha/tc/espvar.h b/sys/arch/alpha/tc/espvar.h index 9ac9e0217e0b..b1ef9b9c8944 100644 --- a/sys/arch/alpha/tc/espvar.h +++ b/sys/arch/alpha/tc/espvar.h @@ -1,4 +1,4 @@ -/* $NetBSD: espvar.h,v 1.1 1995/02/13 23:08:58 cgd Exp $ */ +/* $NetBSD: espvar.h,v 1.2 1995/08/03 00:52:10 cgd Exp $ */ /* * Copyright (c) 1994 Peter Galbavy. All rights reserved. @@ -305,9 +305,9 @@ struct esp_softc { #if ESP_DEBUG > 1 #define ESPCMD(sc, cmd) \ - printf("cmd:0x%02x ", sc->sc_reg->esp_cmd = cmd); MB(); + printf("cmd:0x%02x ", sc->sc_reg->esp_cmd = cmd); wbflush(); #else -#define ESPCMD(sc, cmd) sc->sc_reg->esp_cmd = cmd; MB(); +#define ESPCMD(sc, cmd) sc->sc_reg->esp_cmd = cmd; wbflush(); #endif #define SAME_ESP(sc, bp, ca) \ diff --git a/sys/arch/alpha/tc/if_le.c b/sys/arch/alpha/tc/if_le.c index ea7bdd5fb097..8bcd86157ff9 100644 --- a/sys/arch/alpha/tc/if_le.c +++ b/sys/arch/alpha/tc/if_le.c @@ -1,4 +1,4 @@ -/* $NetBSD: if_le.c,v 1.6 1995/06/28 02:30:25 cgd Exp $ */ +/* $NetBSD: if_le.c,v 1.7 1995/08/03 00:52:13 cgd Exp $ */ /*- * Copyright (c) 1995 Charles M. Hannum. All rights reserved. @@ -68,7 +68,7 @@ /* access LANCE registers */ void lewritereg(); -#define LERDWR(cntl, src, dst) { (dst) = (src); MB(); } +#define LERDWR(cntl, src, dst) { (dst) = (src); wbflush(); } #define LEWREG(src, dst) lewritereg(&(dst), (src)) #define LE_OFFSET_RAM 0x0 @@ -192,7 +192,7 @@ leattach(parent, self, aux) (((u_int64_t)le_iomem >> 29) & 0x1f); *(volatile u_int *)ASIC_REG_CSR(asic_base) |= ASIC_CSR_DMAEN_LANCE; - MB(); + wbflush(); } else { /* It's on the turbochannel proper */ sc->sc_r1 = (struct lereg1 *) @@ -226,7 +226,7 @@ leattach(parent, self, aux) BUS_INTR_ESTABLISH(ca, leintr, sc); /* XXX YEECH!!! */ *(volatile u_int *)ASIC_REG_IMSK(asic_base) |= ASIC_INTR_LANCE; - MB(); + wbflush(); } /* @@ -243,7 +243,7 @@ lewritereg(regptr, val) while (*regptr != val) { *regptr = val; - MB(); + wbflush(); if (++i > 10000) { printf("le: Reg did not settle (to x%x): x%x\n", val, *regptr); diff --git a/sys/arch/alpha/tc/scc.c b/sys/arch/alpha/tc/scc.c index d01658f6d33d..5128c33c2803 100644 --- a/sys/arch/alpha/tc/scc.c +++ b/sys/arch/alpha/tc/scc.c @@ -1,4 +1,4 @@ -/* $NetBSD: scc.c,v 1.8 1995/06/28 04:30:34 cgd Exp $ */ +/* $NetBSD: scc.c,v 1.9 1995/08/03 00:52:17 cgd Exp $ */ /* * Copyright (c) 1991,1990,1989,1994,1995 Carnegie Mellon University @@ -248,7 +248,7 @@ scc_alphaintr(onoff) ASIC_CSR_DMAEN_T2 | ASIC_CSR_DMAEN_R2); #endif } - MB(); + wbflush(); } void @@ -804,7 +804,7 @@ sccintr(xxxunit) dp = &sc->scc_pdma[chan]; if (dp->p_mem < dp->p_end) { SCC_WRITE_DATA(regs, chan, *dp->p_mem++); - MB(); + wbflush(); } else { tp->t_state &= ~TS_BUSY; if (tp->t_state & TS_FLUSH) @@ -825,7 +825,7 @@ sccintr(xxxunit) cc = sc->scc_wreg[chan].wr1 & ~ZSWR1_TIE; SCC_WRITE_REG(regs, chan, SCC_WR1, cc); sc->scc_wreg[chan].wr1 = cc; - MB(); + wbflush(); } } } else if (rr2 == SCC_RR2_A_RECV_DONE || @@ -1011,7 +1011,7 @@ sccstart(tp) #endif SCC_WRITE_DATA(regs, chan, *dp->p_mem++); } - MB(); + wbflush(); out: splx(s); } @@ -1214,7 +1214,7 @@ sccPutc(dev, c) * Send the char. */ SCC_WRITE_DATA(regs, line, c); - MB(); + wbflush(); splx(s); return; diff --git a/sys/arch/alpha/tc/sccvar.h b/sys/arch/alpha/tc/sccvar.h index 35f8db0b8dba..c00d71420775 100644 --- a/sys/arch/alpha/tc/sccvar.h +++ b/sys/arch/alpha/tc/sccvar.h @@ -1,4 +1,4 @@ -/* $NetBSD: sccvar.h,v 1.1 1995/02/13 23:09:05 cgd Exp $ */ +/* $NetBSD: sccvar.h,v 1.2 1995/08/03 00:52:23 cgd Exp $ */ /* * Copyright (c) 1991,1990,1989,1994,1995 Carnegie Mellon University @@ -97,7 +97,7 @@ typedef struct { #define scc_get_datum(d, v) \ do { (v) = ((d) >> 8) & 0xff; } while (0) #define scc_set_datum(d, v) \ - do { (d) = (volatile unsigned int)(v) << 8; MB(); } while (0) + do { (d) = (volatile unsigned int)(v) << 8; wbflush(); } while (0) /* * Minor device numbers for scc. Weird because B channel comes first and