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Remove iavc(4).

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This commit is contained in:
maxv 2018-09-21 18:38:25 +00:00
parent f14e814470
commit ff948ad040
13 changed files with 14 additions and 2164 deletions
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8
distrib/sets/lists/man/mi
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@ -1,4 +1,4 @@
# $NetBSD: mi,v 1.1619 2018/09/21 08:43:18 maxv Exp $
# $NetBSD: mi,v 1.1620 2018/09/21 18:38:25 maxv Exp $
#
# Note: don't delete entries from here - mark them as "obsolete" instead.
#
@ -1287,7 +1287,7 @@
./usr/share/man/cat4/i4btel.0 man-obsolete obsolete
./usr/share/man/cat4/i4btrc.0 man-obsolete obsolete
./usr/share/man/cat4/i915drm.0 man-sys-catman .cat
./usr/share/man/cat4/iavc.0 man-sys-catman .cat
./usr/share/man/cat4/iavc.0 man-obsolete obsolete
./usr/share/man/cat4/ibmcd.0 man-sys-catman .cat
./usr/share/man/cat4/ibmhawk.0 man-sys-catman .cat
./usr/share/man/cat4/ichlpcib.0 man-obsolete obsolete
@ -4408,7 +4408,7 @@
./usr/share/man/html4/i386/vesafb.html man-obsolete obsolete
./usr/share/man/html4/i386/viac7temp.html man-sys-htmlman html
./usr/share/man/html4/i915drm.html man-sys-htmlman html
./usr/share/man/html4/iavc.html man-sys-htmlman html
./usr/share/man/html4/iavc.html man-obsolete obsolete
./usr/share/man/html4/ibmcd.html man-sys-htmlman html
./usr/share/man/html4/ibmhawk.html man-sys-htmlman html
./usr/share/man/html4/ichlpcib.html man-obsolete obsolete
@ -7361,7 +7361,7 @@
./usr/share/man/man4/i4btel.4 man-obsolete obsolete
./usr/share/man/man4/i4btrc.4 man-obsolete obsolete
./usr/share/man/man4/i915drm.4 man-sys-man .man
./usr/share/man/man4/iavc.4 man-sys-man .man
./usr/share/man/man4/iavc.4 man-obsolete obsolete
./usr/share/man/man4/ibmcd.4 man-sys-man .man
./usr/share/man/man4/ibmhawk.4 man-sys-man .man
./usr/share/man/man4/ichlpcib.4 man-obsolete obsolete

4
share/man/man4/Makefile
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@ -1,4 +1,4 @@
# $NetBSD: Makefile,v 1.667 2018/09/19 13:58:27 maxv Exp $
# $NetBSD: Makefile,v 1.668 2018/09/21 18:38:25 maxv Exp $
# @(#)Makefile 8.1 (Berkeley) 6/18/93
MAN= aac.4 ac97.4 acardide.4 aceride.4 acphy.4 \
@ -146,7 +146,7 @@ MAN+= faith.4 gif.4 inet6.4 icmp6.4 ip6.4 ipsec.4 ipsecif.4 stf.4
# ISDN devices
MAN+= isdntrc.4 isdntel.4 isdnbchan.4 ippp.4 irip.4 isdnctl.4 isdn.4 \
ifpci.4 isic.4 iwic.4 isdncapi.4 iavc.4
ifpci.4 isic.4 iwic.4 isdncapi.4
# onewire bus and devices
MAN+= gpioow.4 onewire.4 owtemp.4

76
share/man/man4/iavc.4
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@ -1,76 +0,0 @@
.\" $NetBSD: iavc.4,v 1.5 2014/03/18 18:20:39 riastradh Exp $
.\"
.\" Copyright (c) 2001, 2002 Hellmuth Michaelis. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
.\" $FreeBSD: src/usr.sbin/i4b/man/iavc.4,v 1.3 2002/07/28 18:21:48 hm Exp $
.\"
.\" last edit-date: [Sun Jul 28 16:37:51 2002]
.\"
.Dd July 28, 2002
.Dt IAVC 4
.Os
.Sh NAME
.Nm iavc
.Nd isdn4bsd AVM B1 driver
.Sh SYNOPSIS
.Cd "iavc* at pci?"
.Sh DESCRIPTION
The
.Nm
driver is used to glue the AVM family of active cards to the
.Xr isdncapi 4
driver and the
.Em isdn4bsd
package.
Currently only the AVM B1 PCI is supported.
Support for the AVM B1 ISA and the AVM T1 PCI cards should be quite
easy to add, since support already exists in the
.Fx
version of the driver.
.Pp
To use this driver, you must first fetch the firmware file
.Nm b1.t4
from
.Lk ftp://ftp.avm.de/
and load it to the card using
.Xr isdnd 8 .
.Sh SEE ALSO
.Xr isdncapi 4 ,
.Xr isdnd 8
.Sh STANDARDS
.Lk http://www.capi.org/ "CAPI 2.0"
.Sh AUTHORS
.An -nosplit
The
.Nm
device driver was written by
.An Juha-Matti Liukkonen Aq Mt jml@cubical.fi
(Cubical Solutions Ltd, Finland) for
.Fx
and ported to
.Nx
by
.An Antti Kantee Aq Mt pooka@cubical.fi .
This manpage was written by
.An Hellmuth Michaelis Aq Mt hm@FreeBSD.org .

7
sys/arch/amd64/conf/ALL
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@ -1,4 +1,4 @@
# $NetBSD: ALL,v 1.101 2018/09/06 05:36:49 maxv Exp $
# $NetBSD: ALL,v 1.102 2018/09/21 18:38:25 maxv Exp $
# From NetBSD: GENERIC,v 1.787 2006/10/01 18:37:54 bouyer Exp
#
# ALL machine description file
@ -17,7 +17,7 @@ include "arch/amd64/conf/std.amd64"
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
#ident "ALL-$Revision: 1.101 $"
#ident "ALL-$Revision: 1.102 $"
maxusers 64 # estimated number of users
@ -1762,9 +1762,6 @@ ifpci* at pci?
# AVM Fritz!PCI V2 card
ifritz* at pci?
# AVM B1/T1 PCI card
iavc* at pci?
#
#---------------------------------------------------------------------
# Supported PCMCIA cards:

7
sys/arch/i386/conf/ALL
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@ -1,4 +1,4 @@
# $NetBSD: ALL,v 1.451 2018/09/06 05:36:50 maxv Exp $
# $NetBSD: ALL,v 1.452 2018/09/21 18:38:25 maxv Exp $
# From NetBSD: GENERIC,v 1.787 2006/10/01 18:37:54 bouyer Exp
#
# ALL machine description file
@ -17,7 +17,7 @@ include "arch/i386/conf/std.i386"
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
#ident "ALL-$Revision: 1.451 $"
#ident "ALL-$Revision: 1.452 $"
maxusers 64 # estimated number of users
@ -1908,9 +1908,6 @@ ifpci* at pci?
# AVM Fritz!PCI V2 card
ifritz* at pci?
# AVM B1/T1 PCI card
iavc* at pci?
#
#---------------------------------------------------------------------
# Supported PCMCIA cards:

5
sys/arch/i386/conf/GENERIC_ISDN
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@ -1,4 +1,4 @@
# $NetBSD: GENERIC_ISDN,v 1.16 2010/01/03 03:53:34 dholland Exp $
# $NetBSD: GENERIC_ISDN,v 1.17 2018/09/21 18:38:25 maxv Exp $
#
# GENERIC kernel with all supported ISDN devices and drivers
@ -60,9 +60,6 @@ ifpci* at pci?
# AVM Fritz!PCI V2 card
ifritz* at pci?
# AVM B1/T1 PCI card
iavc* at pci?
#
#---------------------------------------------------------------------
# Supported PCMCIA cards:

7
sys/conf/files
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@ -1,4 +1,4 @@
# $NetBSD: files,v 1.1208 2018/09/19 13:58:27 maxv Exp $
# $NetBSD: files,v 1.1209 2018/09/21 18:38:25 maxv Exp $
# @(#)files.newconf 7.5 (Berkeley) 5/10/93
version 20171118
@ -1382,11 +1382,6 @@ file dev/ic/isic_l1fsm.c isic|ifpci|ifritz
file dev/ic/hscx.c isic
file dev/ic/isic_bchan.c isic
# AWM B1/T1
# XXX: passive_isdn
device iavc: isdndev, isdncapi, passive_isdn
file dev/ic/iavc.c iavc
# Broadcom AirForce / Apple Airport Extreme
device bwi: arp, ifnet, firmload, wlan
file dev/ic/bwi.c bwi

3
sys/dev/DEVNAMES
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@ -1,4 +1,4 @@
# $NetBSD: DEVNAMES,v 1.313 2018/09/19 13:58:27 maxv Exp $
# $NetBSD: DEVNAMES,v 1.314 2018/09/21 18:38:25 maxv Exp $
#
# This file contains all used device names and defined attributes in
# alphabetical order. New devices added to the system somewhere should first
@ -612,7 +612,6 @@ i2cbus MI Attribute
i2c_eeprom MI Attribute
i8042 shark Attribute
i82586 MI Attribute
iavc MI
ibmcd MI
ibus pmax
ibus vax

1090
sys/dev/ic/iavc.c
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File diff suppressed because it is too large Load Diff

483
sys/dev/ic/iavcreg.h
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@ -1,483 +0,0 @@
/* $NetBSD: iavcreg.h,v 1.4 2006/02/16 20:17:16 perry Exp $ */
/*
* Copyright (c) 2001-2003 Cubical Solutions Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* capi/iavc/iavc.h The AVM ISDN controllers' common declarations.
*
* $FreeBSD: src/sys/i4b/capi/iavc/iavc.h,v 1.1.2.1 2001/08/10 14:08:34 obrien Exp $
*/
/*
// AMCC_{READ,WRITE}
// Routines to access the memory mapped registers of the
// S5933 DMA controller.
*/
static __inline u_int32_t AMCC_READ(iavc_softc_t *sc, int off)
{
return bus_space_read_4(sc->sc_mem_bt, sc->sc_mem_bh, off);
}
static __inline void AMCC_WRITE(iavc_softc_t *sc, int off, u_int32_t value)
{
bus_space_write_4(sc->sc_mem_bt, sc->sc_mem_bh, off, value);
}
/*
// amcc_{put,get}_{byte,word}
// Routines to access the DMA buffers byte- or wordwise.
*/
static __inline u_int8_t* amcc_put_byte(u_int8_t *buf, u_int8_t value)
{
*buf++ = value;
return buf;
}
static __inline u_int8_t* amcc_get_byte(u_int8_t *buf, u_int8_t *value)
{
*value = *buf++;
return buf;
}
static __inline u_int8_t* amcc_put_word(u_int8_t *buf, u_int32_t value)
{
*buf++ = (value & 0xff);
*buf++ = (value >> 8) & 0xff;
*buf++ = (value >> 16) & 0xff;
*buf++ = (value >> 24) & 0xff;
return buf;
}
static __inline u_int8_t* amcc_get_word(u_int8_t *buf, u_int32_t *value)
{
*value = *buf++;
*value |= (*buf++ << 8);
*value |= (*buf++ << 16);
*value |= (*buf++ << 24);
return buf;
}
/*
// Controller LLI message numbers.
*/
#define SEND_POLL 0x72
#define SEND_INIT 0x11
#define SEND_REGISTER 0x12
#define SEND_DATA_B3_REQ 0x13
#define SEND_RELEASE 0x14
#define SEND_MESSAGE 0x15
#define SEND_CONFIG 0x71
#define SEND_POLLACK 0x73
#define RECEIVE_POLL 0x32
#define RECEIVE_INIT 0x27
#define RECEIVE_MESSAGE 0x21
#define RECEIVE_DATA_B3_IND 0x22
#define RECEIVE_START 0x23
#define RECEIVE_STOP 0x24
#define RECEIVE_NEW_NCCI 0x25
#define RECEIVE_FREE_NCCI 0x26
#define RECEIVE_RELEASE 0x26
#define RECEIVE_TASK_READY 0x31
#define RECEIVE_DEBUGMSG 0x71
#define RECEIVE_POLLDWORD 0x75
/* Operation constants */
#define WRITE_REGISTER 0x00
#define READ_REGISTER 0x01
/* Port offsets in I/O space */
#define B1_READ 0x00
#define B1_WRITE 0x01
#define B1_INSTAT 0x02
#define B1_OUTSTAT 0x03
#define B1_ANALYSE 0x04
#define B1_REVISION 0x05
#define B1_RESET 0x10
#define T1_FASTLINK 0x00
#define T1_SLOWLINK 0x08
#define T1_READ B1_READ
#define T1_WRITE B1_WRITE
#define T1_INSTAT B1_INSTAT
#define T1_OUTSTAT B1_OUTSTAT
#define T1_IRQENABLE 0x05
#define T1_FIFOSTAT 0x06
#define T1_RESETLINK 0x10
#define T1_ANALYSE 0x11
#define T1_IRQMASTER 0x12
#define T1_IDENT 0x17
#define T1_RESETBOARD 0x1f
#define T1F_IREADY 0x01
#define T1F_IHALF 0x02
#define T1F_IFULL 0x04
#define T1F_IEMPTY 0x08
#define T1F_IFLAGS 0xf0
#define T1F_OREADY 0x10
#define T1F_OHALF 0x20
#define T1F_OEMPTY 0x40
#define T1F_OFULL 0x80
#define T1F_OFLAGS 0xf0
#define FIFO_OUTBSIZE 256
#define FIFO_INPBSIZE 512
#define HEMA_VERSION_ID 0
#define HEMA_PAL_ID 0
/*
// S5933 DMA controller register offsets in memory, and bitmasks.
*/
#define AMCC_RXPTR 0x24
#define AMCC_RXLEN 0x28
#define AMCC_TXPTR 0x2c
#define AMCC_TXLEN 0x30
#define AMCC_INTCSR 0x38
#define EN_READ_TC_INT 0x00008000
#define EN_WRITE_TC_INT 0x00004000
#define EN_TX_TC_INT EN_READ_TC_INT
#define EN_RX_TC_INT EN_WRITE_TC_INT
#define AVM_FLAG 0x30000000
#define ANY_S5933_INT 0x00800000
#define READ_TC_INT 0x00080000
#define WRITE_TC_INT 0x00040000
#define TX_TC_INT READ_TC_INT
#define RX_TC_INT WRITE_TC_INT
#define MASTER_ABORT_INT 0x00100000
#define TARGET_ABORT_INT 0x00200000
#define BUS_MASTER_INT 0x00200000
#define ALL_INT 0x000c0000
#define AMCC_MCSR 0x3c
#define A2P_HI_PRIORITY 0x00000100
#define EN_A2P_TRANSFERS 0x00000400
#define P2A_HI_PRIORITY 0x00001000
#define EN_P2A_TRANSFERS 0x00004000
#define RESET_A2P_FLAGS 0x04000000
#define RESET_P2A_FLAGS 0x02000000
/*
// (B1IO_WAIT_MAX * B1IO_WAIT_DLY) is the max wait in us for the card
// to become ready after an I/O operation. The default is 1 ms.
*/
#define B1IO_WAIT_MAX 1000
#define B1IO_WAIT_DLY 1
/*
// b1io_outp
// Diagnostic output routine, returns the written value via
// the device's analysis register.
//
// b1io_rx_full
// Returns nonzero if data is readable from the card via the
// I/O ports.
//
// b1io_tx_empty
// Returns nonzero if data can be written to the card via the
// I/O ports.
*/
static __inline u_int8_t b1io_outp(iavc_softc_t *sc, int off, u_int8_t val)
{
bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, off, val);
DELAY(1);
return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_ANALYSE);
}
static __inline int b1io_rx_full(iavc_softc_t *sc)
{
u_int8_t val = bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_INSTAT);
return (val & 0x01);
}
static __inline int b1io_tx_empty(iavc_softc_t *sc)
{
u_int8_t val = bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_OUTSTAT);
return (val & 0x01);
}
/*
// b1io_{get,put}_{byte,word}
// Routines to read and write the device I/O registers byte- or
// wordwise.
//
// b1io_{get,put}_slice
// Routines to read and write sequential bytes to the device
// I/O registers.
*/
static __inline u_int8_t b1io_get_byte(iavc_softc_t *sc)
{
int spin = 0;
while (!b1io_rx_full(sc) && spin < B1IO_WAIT_MAX) {
spin++; DELAY(B1IO_WAIT_DLY);
}
if (b1io_rx_full(sc))
return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_READ);
printf("iavc%d: rx not completed\n", sc->sc_unit);
return 0xff;
}
static __inline int b1io_put_byte(iavc_softc_t *sc, u_int8_t val)
{
int spin = 0;
while (!b1io_tx_empty(sc) && spin < B1IO_WAIT_MAX) {
spin++; DELAY(B1IO_WAIT_DLY);
}
if (b1io_tx_empty(sc)) {
bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, B1_WRITE, val);
return 0;
}
printf("iavc%d: tx not emptied\n", sc->sc_unit);
return -1;
}
static __inline int b1io_save_put_byte(iavc_softc_t *sc, u_int8_t val)
{
int spin = 0;
while (!b1io_tx_empty(sc) && spin < B1IO_WAIT_MAX) {
spin++; DELAY(B1IO_WAIT_DLY);
}
if (b1io_tx_empty(sc)) {
b1io_outp(sc, B1_WRITE, val);
return 0;
}
printf("iavc%d: tx not emptied\n", sc->sc_unit);
return -1;
}
static __inline u_int32_t b1io_get_word(iavc_softc_t *sc)
{
u_int32_t val = 0;
val |= b1io_get_byte(sc);
val |= (b1io_get_byte(sc) << 8);
val |= (b1io_get_byte(sc) << 16);
val |= (b1io_get_byte(sc) << 24);
return val;
}
static __inline void b1io_put_word(iavc_softc_t *sc, u_int32_t val)
{
b1io_put_byte(sc, (val & 0xff));
b1io_put_byte(sc, (val >> 8) & 0xff);
b1io_put_byte(sc, (val >> 16) & 0xff);
b1io_put_byte(sc, (val >> 24) & 0xff);
}
static __inline int b1io_get_slice(iavc_softc_t *sc, u_int8_t *dp)
{
int len, i;
len = i = b1io_get_word(sc);
while (i--) *dp++ = b1io_get_byte(sc);
return len;
}
static __inline void b1io_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
{
b1io_put_word(sc, len);
while (len--) b1io_put_byte(sc, *dp++);
}
/*
// b1io_{read,write}_reg
// Routines to read and write the device registers via the I/O
// ports.
*/
static __inline u_int32_t b1io_read_reg(iavc_softc_t *sc, int reg)
{
b1io_put_byte(sc, READ_REGISTER);
b1io_put_word(sc, reg);
return b1io_get_word(sc);
}
static __inline u_int32_t b1io_write_reg(iavc_softc_t *sc, int reg, u_int32_t val)
{
b1io_put_byte(sc, WRITE_REGISTER);
b1io_put_word(sc, reg);
b1io_put_word(sc, val);
return b1io_get_word(sc);
}
/*
// t1io_outp
// I/O port write operation for the T1, which does not seem
// to have the analysis port.
*/
static __inline void t1io_outp(iavc_softc_t *sc, int off, u_int8_t val)
{
bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, off, val);
}
static __inline u_int8_t t1io_inp(iavc_softc_t *sc, int off)
{
return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, off);
}
static __inline int t1io_isfastlink(iavc_softc_t *sc)
{
return ((bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, T1_IDENT) & ~0x82) == 1);
}
static __inline u_int8_t t1io_fifostatus(iavc_softc_t *sc)
{
return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, T1_FIFOSTAT);
}
static __inline int t1io_get_slice(iavc_softc_t *sc, u_int8_t *dp)
{
int len, i;
len = i = b1io_get_word(sc);
if (t1io_isfastlink(sc)) {
int status;
while (i) {
status = t1io_fifostatus(sc) & (T1F_IREADY|T1F_IHALF);
if (i >= FIFO_INPBSIZE) status |= T1F_IFULL;
switch (status) {
case T1F_IREADY|T1F_IHALF|T1F_IFULL:
bus_space_read_multi_1(sc->sc_io_bt, sc->sc_io_bh,
T1_READ, dp, FIFO_INPBSIZE);
dp += FIFO_INPBSIZE;
i -= FIFO_INPBSIZE;
break;
case T1F_IREADY|T1F_IHALF:
bus_space_read_multi_1(sc->sc_io_bt, sc->sc_io_bh,
T1_READ, dp, i);
dp += i;
i = 0;
break;
default:
*dp++ = b1io_get_byte(sc);
i--;
}
}
} else { /* not fastlink */
if (i--) *dp++ = b1io_get_byte(sc);
}
return len;
}
static __inline void t1io_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
{
int i = len;
b1io_put_word(sc, i);
if (t1io_isfastlink(sc)) {
int status;
while (i) {
status = t1io_fifostatus(sc) & (T1F_OREADY|T1F_OHALF);
if (i >= FIFO_OUTBSIZE) status |= T1F_OFULL;
switch (status) {
case T1F_OREADY|T1F_OHALF|T1F_OFULL:
bus_space_write_multi_1(sc->sc_io_bt, sc->sc_io_bh,
T1_WRITE, dp, FIFO_OUTBSIZE);
dp += FIFO_OUTBSIZE;
i -= FIFO_OUTBSIZE;
break;
case T1F_OREADY|T1F_OHALF:
bus_space_write_multi_1(sc->sc_io_bt, sc->sc_io_bh,
T1_WRITE, dp, i);
dp += i;
i = 0;
break;
default:
b1io_put_byte(sc, *dp++);
i--;
}
}
} else {
while (i--) b1io_put_byte(sc, *dp++);
}
}
/*
// An attempt to bring it all together:
// ------------------------------------
//
// iavc_{read,write}_reg
// Routines to access the device registers via the I/O port.
//
// iavc_{read,write}_port
// Routines to access the device I/O ports.
//
// iavc_tx_empty, iavc_rx_full
// Routines to check when the device has drained the last written
// byte, or produced a full byte to read.
//
// iavc_{get,put}_byte
// Routines to read/write byte values to the device via the I/O port.
//
// iavc_{get,put}_word
// Routines to read/write 32-bit words to the device via the I/O port.
//
// iavc_{get,put}_slice
// Routines to read/write {length, data} pairs to the device via the
// ubiquituous I/O port. Uses the HEMA FIFO on a T1.
*/
#define iavc_read_reg(sc, reg) b1io_read_reg(sc, reg)
#define iavc_write_reg(sc, reg, val) b1io_write_reg(sc, reg, val)
#define iavc_read_port(sc, port) \
bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, (port))
#define iavc_write_port(sc, port, val) \
bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, (port), (val))
#define iavc_tx_empty(sc) b1io_tx_empty(sc)
#define iavc_rx_full(sc) b1io_rx_full(sc)
#define iavc_get_byte(sc) b1io_get_byte(sc)
#define iavc_put_byte(sc, val) b1io_put_byte(sc, val)
#define iavc_get_word(sc) b1io_get_word(sc)
#define iavc_put_word(sc, val) b1io_put_word(sc, val)
static __inline u_int32_t iavc_get_slice(iavc_softc_t *sc, u_int8_t *dp)
{
if (sc->sc_t1) return t1io_get_slice(sc, dp);
else return b1io_get_slice(sc, dp);
}
static __inline void iavc_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
{
if (sc->sc_t1) t1io_put_slice(sc, dp, len);
else b1io_put_slice(sc, dp, len);
}

127
sys/dev/ic/iavcvar.h
View File

@ -1,127 +0,0 @@
/* $NetBSD: iavcvar.h,v 1.5 2012/10/27 17:18:20 chs Exp $ */
/*
* Copyright (c) 2001-2003 Cubical Solutions Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* capi/iavc/iavc.h The AVM ISDN controllers' common declarations.
*
* $FreeBSD: src/sys/i4b/capi/iavc/iavc.h,v 1.1.2.1 2001/08/10 14:08:34 obrien Exp $
*/
#include <netisdn/i4b_capi.h>
/*
// iavc_softc_t
// The software context of one AVM T1 controller.
*/
#define IAVC_IO_BASES 1
#define IAVC_DMA_SIZE (128 + 2048)
typedef struct iavc_softc {
device_t sc_dev;
capi_softc_t sc_capi;
bus_space_handle_t sc_mem_bh;
bus_space_tag_t sc_mem_bt;
bus_space_handle_t sc_io_bh;
bus_space_tag_t sc_io_bt;
bus_dma_tag_t dmat;
bus_dmamap_t tx_map;
bus_dmamap_t rx_map;
bus_dma_segment_t txseg;
bus_dma_segment_t rxseg;
int ntxsegs, nrxsegs;
uint32_t sc_unit;
uint32_t sc_intr;
int32_t sc_state;
#define IAVC_DOWN 0
#define IAVC_POLL 1
#define IAVC_INIT 2
#define IAVC_UP 3
uint32_t sc_blocked;
uint32_t sc_dma;
uint32_t sc_t1;
u_int32_t sc_csr;
void * sc_sendbuf;
void * sc_recvbuf;
u_int32_t sc_recv1;
struct ifqueue sc_txq;
} iavc_softc_t;
/*
// {b1,b1dma,t1}_{detect,reset}
// Routines to detect and manage the specific type of card.
*/
int iavc_b1_detect(iavc_softc_t *sc);
void iavc_b1_disable_irq(iavc_softc_t *sc);
void iavc_b1_reset(iavc_softc_t *sc);
int iavc_b1dma_detect(iavc_softc_t *sc);
void iavc_b1dma_reset(iavc_softc_t *sc);
int iavc_t1_detect(iavc_softc_t *sc);
void iavc_t1_disable_irq(iavc_softc_t *sc);
void iavc_t1_reset(iavc_softc_t *sc);
/*
// iavc_handle_intr
// Interrupt handler, called by the bus specific interrupt routine
// in iavc_<bustype>.c module.
//
// iavc_load
// CAPI callback. Resets device and loads firmware.
//
// iavc_register
// CAPI callback. Registers an application id.
//
// iavc_release
// CAPI callback. Releases an application id.
//
// iavc_send
// CAPI callback. Sends a CAPI message. A B3_DATA_REQ message has
// m_next point to a data mbuf.
*/
int iavc_handle_intr(iavc_softc_t *);
int iavc_load(capi_softc_t *, int, u_int8_t *);
int iavc_register(capi_softc_t *, int, int);
int iavc_release(capi_softc_t *, int);
int iavc_send(capi_softc_t *, struct mbuf *);
#ifdef notyet
extern void b1isa_setup_irq(struct iavc_softc *sc);
#endif

6
sys/dev/pci/files.pci
View File

@ -1,4 +1,4 @@
# $NetBSD: files.pci,v 1.401 2018/09/06 05:36:51 maxv Exp $
# $NetBSD: files.pci,v 1.402 2018/09/21 18:38:25 maxv Exp $
#
# Config file and device description for machine-independent PCI code.
# Included by ports that need it. Requires that the SCSI files be
@ -813,10 +813,6 @@ file dev/pci/isic_pci.c isic_pci
file dev/pci/isic_pci_elsa_qs1p.c isic_pci
# AVM T1/B1
attach iavc at pci with iavc_pci
file dev/pci/iavc_pci.c iavc_pci
device ifpci: isdndev, passive_isdn, nisac
attach ifpci at pci
file dev/pci/ifpci.c ifpci

355
sys/dev/pci/iavc_pci.c
View File

@ -1,355 +0,0 @@
/* $NetBSD: iavc_pci.c,v 1.17 2016/07/11 11:31:51 msaitoh Exp $ */
/*
char intrbuf[PCI_INTRSTR_LEN];
* Copyright (c) 2001-2003 Cubical Solutions Ltd.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* capi/iavc/iavc_pci.c
* The AVM ISDN controllers' PCI bus attachment handling.
*
* $FreeBSD: src/sys/i4b/capi/iavc/iavc_pci.c,v 1.1.2.1 2001/08/10 14:08:34 obrien Exp $
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: iavc_pci.c,v 1.17 2016/07/11 11:31:51 msaitoh Exp $");
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/mbuf.h>
#include <sys/callout.h>
#include <sys/socket.h>
#include <sys/device.h>
#include <net/if.h>
#include <sys/bus.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcidevs.h>
#include <netisdn/i4b_ioctl.h>
#include <netisdn/i4b_l3l4.h>
#include <netisdn/i4b_capi.h>
#include <dev/ic/iavcvar.h>
#include <dev/ic/iavcreg.h>
struct iavc_pci_softc {
struct iavc_softc sc_iavc;
bus_addr_t mem_base;
bus_size_t mem_size;
bus_addr_t io_base;
bus_size_t io_size;
pci_chipset_tag_t sc_pc;
void *sc_ih; /* interrupt handler */
};
#define IAVC_PCI_IOBA 0x14
#define IAVC_PCI_MMBA 0x10
/* PCI driver linkage */
static const struct iavc_pci_product *find_cardname(struct pci_attach_args *);
static int iavc_pci_probe(device_t, cfdata_t, void *);
static void iavc_pci_attach(device_t, device_t, void *);
int iavc_pci_intr(void *);
CFATTACH_DECL_NEW(iavc_pci, sizeof(struct iavc_pci_softc),
iavc_pci_probe, iavc_pci_attach, NULL, NULL);
static const struct iavc_pci_product {
pci_vendor_id_t npp_vendor;
pci_product_id_t npp_product;
const char *name;
} iavc_pci_products[] = {
{ PCI_VENDOR_AVM, PCI_PRODUCT_AVM_B1, "AVM B1 PCI" },
{ PCI_VENDOR_AVM, PCI_PRODUCT_AVM_T1, "AVM T1 PCI" },
{ 0, 0, NULL },
};
static const struct iavc_pci_product *
find_cardname(struct pci_attach_args * pa)
{
const struct iavc_pci_product *pp = NULL;
for (pp = iavc_pci_products; pp->npp_vendor; pp++) {
if (PCI_VENDOR(pa->pa_id) == pp->npp_vendor &&
PCI_PRODUCT(pa->pa_id) == pp->npp_product)
return pp;
}
return NULL;
}
static int
iavc_pci_probe(device_t parent, cfdata_t match, void *aux)
{
struct pci_attach_args *pa = aux;
if (find_cardname(pa))
return 1;
return 0;
}
static void
iavc_pci_attach(device_t parent, device_t self, void *aux)
{
struct iavc_pci_softc *psc = device_private(self);
struct iavc_softc *sc = &psc->sc_iavc;
struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
const struct iavc_pci_product *pp;
pci_intr_handle_t ih;
const char *intrstr;
int ret;
char intrbuf[PCI_INTRSTR_LEN];
pp = find_cardname(pa);
if (pp == NULL)
return;
sc->sc_dev = self;
sc->sc_t1 = 0;
sc->sc_dma = 0;
sc->dmat = pa->pa_dmat;
if (pci_mapreg_map(pa, IAVC_PCI_IOBA, PCI_MAPREG_TYPE_IO, 0,
&sc->sc_io_bt, &sc->sc_io_bh, &psc->io_base, &psc->io_size)) {
aprint_error(": unable to map i/o registers\n");
return;
}
if (pci_mapreg_map(pa, IAVC_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0,
&sc->sc_mem_bt, &sc->sc_mem_bh, &psc->mem_base, &psc->mem_size)) {
aprint_error(": unable to map mem registers\n");
return;
}
aprint_normal(": %s\n", pp->name);
iavc_b1dma_reset(sc);
if (pp->npp_product == PCI_PRODUCT_AVM_T1) {
aprint_error_dev(self, "sorry, PRI not yet supported\n");
return;
#if 0
sc->sc_capi.card_type = CARD_TYPEC_AVM_T1_PCI;
sc->sc_capi.sc_nbch = NBCH_PRI;
ret = iavc_t1_detect(sc);
if (ret) {
if (ret < 6) {
aprint_error_dev(self, "no card detected?\n");
} else {
aprint_error_dev(self, "black box not on\n");
}
return;
} else {
sc->sc_dma = 1;
sc->sc_t1 = 1;
}
#endif
} else if (pp->npp_product == PCI_PRODUCT_AVM_B1) {
sc->sc_capi.card_type = CARD_TYPEC_AVM_B1_PCI;
sc->sc_capi.sc_nbch = NBCH_BRI;
ret = iavc_b1dma_detect(sc);
if (ret) {
ret = iavc_b1_detect(sc);
if (ret) {
aprint_error_dev(self, "no card detected?\n");
return;
}
} else {
sc->sc_dma = 1;
}
}
if (sc->sc_dma)
iavc_b1dma_reset(sc);
#if 0
/*
* XXX: should really be done this way, but this freezes the card
*/
if (sc->sc_t1)
iavc_t1_reset(sc);
else
iavc_b1_reset(sc);
#endif
if (pci_intr_map(pa, &ih)) {
aprint_error_dev(self, "couldn't map interrupt\n");
return;
}
intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, iavc_pci_intr, psc);
if (psc->sc_ih == NULL) {
aprint_error_dev(self, "couldn't establish interrupt");
if (intrstr != NULL)
aprint_error(" at %s", intrstr);
aprint_error("\n");
return;
}
psc->sc_pc = pc;
aprint_normal_dev(self, "interrupting at %s\n", intrstr);
memset(&sc->sc_txq, 0, sizeof(struct ifqueue));
sc->sc_txq.ifq_maxlen = sc->sc_capi.sc_nbch * 4;
sc->sc_intr = 0;
sc->sc_state = IAVC_DOWN;
sc->sc_blocked = 0;
/* setup capi link */
sc->sc_capi.load = iavc_load;
sc->sc_capi.reg_appl = iavc_register;
sc->sc_capi.rel_appl = iavc_release;
sc->sc_capi.send = iavc_send;
sc->sc_capi.ctx = (void *) sc;
/* lock & load DMA for TX */
if ((ret = bus_dmamem_alloc(sc->dmat, IAVC_DMA_SIZE, PAGE_SIZE, 0,
&sc->txseg, 1, &sc->ntxsegs, BUS_DMA_ALLOCNOW)) != 0) {
aprint_error_dev(self,
"can't allocate tx DMA memory, error = %d\n", ret);
goto fail1;
}
if ((ret = bus_dmamem_map(sc->dmat, &sc->txseg, sc->ntxsegs,
IAVC_DMA_SIZE, &sc->sc_sendbuf, BUS_DMA_NOWAIT)) != 0) {
aprint_error_dev(self, "can't map tx DMA memory, error = %d\n",
ret);
goto fail2;
}
if ((ret = bus_dmamap_create(sc->dmat, IAVC_DMA_SIZE, 1,
IAVC_DMA_SIZE, 0, BUS_DMA_ALLOCNOW | BUS_DMA_NOWAIT,
&sc->tx_map)) != 0) {
aprint_error_dev(self, "can't create tx DMA map, error = %d\n",
ret);
goto fail3;
}
if ((ret = bus_dmamap_load(sc->dmat, sc->tx_map, sc->sc_sendbuf,
IAVC_DMA_SIZE, NULL, BUS_DMA_WRITE | BUS_DMA_NOWAIT)) != 0) {
aprint_error_dev(self, "can't load tx DMA map, error = %d\n",
ret);
goto fail4;
}
/* do the same for RX */
if ((ret = bus_dmamem_alloc(sc->dmat, IAVC_DMA_SIZE, PAGE_SIZE, 0,
&sc->rxseg, 1, &sc->nrxsegs, BUS_DMA_ALLOCNOW)) != 0) {
aprint_error_dev(self,
"can't allocate rx DMA memory, error = %d\n", ret);
goto fail5;
}
if ((ret = bus_dmamem_map(sc->dmat, &sc->rxseg, sc->nrxsegs,
IAVC_DMA_SIZE, &sc->sc_recvbuf, BUS_DMA_NOWAIT)) != 0) {
aprint_error_dev(self,
"can't map rx DMA memory, error = %d\n", ret);
goto fail6;
}
if ((ret = bus_dmamap_create(sc->dmat, IAVC_DMA_SIZE, 1, IAVC_DMA_SIZE,
0, BUS_DMA_ALLOCNOW | BUS_DMA_NOWAIT, &sc->rx_map)) != 0) {
aprint_error_dev(self, "can't create rx DMA map, error = %d\n",
ret);
goto fail7;
}
if ((ret = bus_dmamap_load(sc->dmat, sc->rx_map, sc->sc_recvbuf,
IAVC_DMA_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) {
aprint_error_dev(self, "can't load rx DMA map, error = %d\n",
ret);
goto fail8;
}
if (capi_ll_attach(&sc->sc_capi, device_xname(sc->sc_dev), pp->name)) {
aprint_error_dev(self, "capi attach failed\n");
goto fail9;
}
return;
/* release resources in case of failed attach */
fail9:
bus_dmamap_unload(sc->dmat, sc->rx_map);
fail8:
bus_dmamap_destroy(sc->dmat, sc->rx_map);
fail7:
bus_dmamem_unmap(sc->dmat, sc->sc_recvbuf, IAVC_DMA_SIZE);
fail6:
bus_dmamem_free(sc->dmat, &sc->rxseg, sc->nrxsegs);
fail5:
bus_dmamap_unload(sc->dmat, sc->tx_map);
fail4:
bus_dmamap_destroy(sc->dmat, sc->tx_map);
fail3:
bus_dmamem_unmap(sc->dmat, sc->sc_sendbuf, IAVC_DMA_SIZE);
fail2:
bus_dmamem_free(sc->dmat, &sc->txseg, sc->ntxsegs);
fail1:
pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
return;
}
int
iavc_pci_intr(void *arg)
{
struct iavc_softc *sc = arg;
return iavc_handle_intr(sc);
}
#if 0
static int
iavc_pci_detach(device_t self, int flags)
{
struct iavc_pci_softc *psc = device_private(self);
bus_space_unmap(psc->sc_iavc.sc_mem_bt, psc->sc_iavc.sc_mem_bh,
psc->mem_size);
bus_space_free(psc->sc_iavc.sc_mem_bt, psc->sc_iavc.sc_mem_bh,
psc->mem_size);
bus_space_unmap(psc->sc_iavc.sc_io_bt, psc->sc_iavc.sc_io_bh,
psc->io_size);
bus_space_free(psc->sc_iavc.sc_io_bt, psc->sc_iavc.sc_io_bh,
psc->io_size);
pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
/* XXX: capi detach?!? */
return 0;
}
#endif