Change the ISA DMA API to take an isa_chipset_tag_t rather than
a struct device * corresponding to the ISA bus device. The ISA DMA controller driver functions have been renamed and now take a struct isa_dma_state *, and are called indirectly by machine-dependent code which provides the DMA state. These changes allow e.g. `ofisa' (the OpenFirmware configuration mechanism for the ISA bus, used by e.g. Sharks) to use the MI ISA DMA controller code.
This commit is contained in:
thorpej
parent
8dedb90f13
commit
ff76b8e96b
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@ -1,4 +1,4 @@
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/* $NetBSD: isa.c,v 1.100 1998/05/05 21:41:18 drochner Exp $ */
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/* $NetBSD: isa.c,v 1.101 1998/06/09 00:00:21 thorpej Exp $ */
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/*-
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* Copyright (c) 1993, 1994 Charles Hannum. All rights reserved.
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@ -85,14 +85,9 @@ isaattach(parent, self, aux)
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sc->sc_ic = iba->iba_ic;
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/*
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* Map the registers used by the ISA DMA controller.
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* Initialize our DMA state.
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*/
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if (bus_space_map(sc->sc_iot, IO_DMA1, DMA1_IOSIZE, 0, &sc->sc_dma1h))
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panic("isaattach: can't map DMA controller #1");
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if (bus_space_map(sc->sc_iot, IO_DMA2, DMA2_IOSIZE, 0, &sc->sc_dma2h))
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panic("isaattach: can't map DMA controller #2");
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if (bus_space_map(sc->sc_iot, IO_DMAPG, 0xf, 0, &sc->sc_dmapgh))
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panic("isaattach: can't map DMA page registers");
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isa_dmainit(sc->sc_ic, sc->sc_iot, sc->sc_dmat, self);
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TAILQ_INIT(&sc->sc_subdevs);
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@ -1,4 +1,4 @@
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/* $NetBSD: isadma.c,v 1.33 1998/02/04 05:14:35 thorpej Exp $ */
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/* $NetBSD: isadma.c,v 1.34 1998/06/09 00:00:21 thorpej Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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@ -45,6 +45,7 @@
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#include <sys/systm.h>
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#include <sys/proc.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <vm/vm.h>
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@ -55,16 +56,7 @@
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#include <dev/isa/isadmavar.h>
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#include <dev/isa/isadmareg.h>
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/* Used by isa_malloc() */
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#include <sys/malloc.h>
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struct isa_mem {
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struct device *isadev;
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int chan;
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bus_size_t size;
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bus_addr_t addr;
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caddr_t kva;
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struct isa_mem *next;
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} *isa_mem_head = 0;
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struct isa_mem *isa_mem_head;
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/*
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* High byte of DMA address is stored in this DMAPG register for
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@ -82,97 +74,143 @@ static u_int8_t dmamode[4] = {
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DMA37MD_WRITE | DMA37MD_SINGLE | DMA37MD_LOOP
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};
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static inline void isa_dmaunmask __P((struct isa_softc *, int));
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static inline void isa_dmamask __P((struct isa_softc *, int));
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static inline void _isa_dmaunmask __P((struct isa_dma_state *, int));
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static inline void _isa_dmamask __P((struct isa_dma_state *, int));
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static inline void
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isa_dmaunmask(sc, chan)
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struct isa_softc *sc;
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_isa_dmaunmask(ids, chan)
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struct isa_dma_state *ids;
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int chan;
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{
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int ochan = chan & 3;
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/* set dma channel mode, and set dma channel mode */
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if ((chan & 4) == 0)
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bus_space_write_1(sc->sc_iot, sc->sc_dma1h,
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bus_space_write_1(ids->ids_bst, ids->ids_dma1h,
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DMA1_SMSK, ochan | DMA37SM_CLEAR);
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else
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bus_space_write_1(sc->sc_iot, sc->sc_dma2h,
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bus_space_write_1(ids->ids_bst, ids->ids_dma2h,
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DMA2_SMSK, ochan | DMA37SM_CLEAR);
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}
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static inline void
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isa_dmamask(sc, chan)
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struct isa_softc *sc;
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_isa_dmamask(ids, chan)
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struct isa_dma_state *ids;
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int chan;
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{
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int ochan = chan & 3;
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/* set dma channel mode, and set dma channel mode */
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if ((chan & 4) == 0) {
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bus_space_write_1(sc->sc_iot, sc->sc_dma1h,
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bus_space_write_1(ids->ids_bst, ids->ids_dma1h,
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DMA1_SMSK, ochan | DMA37SM_SET);
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bus_space_write_1(sc->sc_iot, sc->sc_dma1h,
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bus_space_write_1(ids->ids_bst, ids->ids_dma1h,
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DMA1_FFC, 0);
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} else {
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bus_space_write_1(sc->sc_iot, sc->sc_dma2h,
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bus_space_write_1(ids->ids_bst, ids->ids_dma2h,
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DMA2_SMSK, ochan | DMA37SM_SET);
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bus_space_write_1(sc->sc_iot, sc->sc_dma2h,
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bus_space_write_1(ids->ids_bst, ids->ids_dma2h,
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DMA2_FFC, 0);
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}
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}
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/*
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* isa_dmacascade(): program 8237 DMA controller channel to accept
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* _isa_dmainit(): Initialize the isa_dma_state for this chipset.
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*/
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void
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_isa_dmainit(ids, bst, dmat, dev)
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struct isa_dma_state *ids;
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bus_space_tag_t bst;
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bus_dma_tag_t dmat;
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struct device *dev;
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{
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ids->ids_dev = dev;
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if (ids->ids_initialized) {
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/*
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* Some systems may have e.g. `ofisa' (OpenFirmware
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* configuration of ISA bus) and a regular `isa'.
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* We allow both to call the initialization function,
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* and take the device name from the last caller
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* (assuming it will be the indirect ISA bus). Since
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* `ofisa' and `isa' are the same bus with different
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* configuration mechanisms, the space and dma tags
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* must be the same!
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*/
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if (ids->ids_bst != bst || ids->ids_dmat != dmat)
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panic("_isa_dmainit: inconsistent ISA tags");
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} else {
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ids->ids_bst = bst;
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ids->ids_dmat = dmat;
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/*
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* Map the registers used by the ISA DMA controller.
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*/
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if (bus_space_map(ids->ids_bst, IO_DMA1, DMA1_IOSIZE, 0,
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&ids->ids_dma1h))
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panic("_isa_dmainit: unable to map DMA controller #1");
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if (bus_space_map(ids->ids_bst, IO_DMA2, DMA2_IOSIZE, 0,
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&ids->ids_dma2h))
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panic("_isa_dmainit: unable to map DMA controller #2");
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if (bus_space_map(ids->ids_bst, IO_DMAPG, 0xf, 0,
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&ids->ids_dmapgh))
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panic("_isa_dmainit: unable to map DMA page registers");
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ids->ids_initialized = 1;
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}
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}
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/*
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* _isa_dmacascade(): program 8237 DMA controller channel to accept
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* external dma control by a board.
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*/
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void
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isa_dmacascade(isadev, chan)
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struct device *isadev;
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_isa_dmacascade(ids, chan)
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struct isa_dma_state *ids;
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int chan;
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{
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struct isa_softc *sc = (struct isa_softc *)isadev;
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int ochan = chan & 3;
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if (chan < 0 || chan > 7) {
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printf("%s: bogus drq %d\n", sc->sc_dev.dv_xname, chan);
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printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan);
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goto lose;
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}
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if (ISA_DRQ_ISFREE(sc, chan) == 0) {
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printf("%s: DRQ %d is not free\n", sc->sc_dev.dv_xname, chan);
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if (ISA_DMA_DRQ_ISFREE(ids, chan) == 0) {
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printf("%s: DRQ %d is not free\n", ids->ids_dev->dv_xname,
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chan);
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goto lose;
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}
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ISA_DRQ_ALLOC(sc, chan);
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ISA_DMA_DRQ_ALLOC(ids, chan);
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/* set dma channel mode, and set dma channel mode */
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if ((chan & 4) == 0)
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bus_space_write_1(sc->sc_iot, sc->sc_dma1h,
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bus_space_write_1(ids->ids_bst, ids->ids_dma1h,
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DMA1_MODE, ochan | DMA37MD_CASCADE);
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else
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bus_space_write_1(sc->sc_iot, sc->sc_dma2h,
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bus_space_write_1(ids->ids_bst, ids->ids_dma2h,
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DMA2_MODE, ochan | DMA37MD_CASCADE);
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isa_dmaunmask(sc, chan);
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_isa_dmaunmask(ids, chan);
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return;
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lose:
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panic("isa_dmacascade");
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panic("_isa_dmacascade");
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}
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int
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isa_dmamap_create(isadev, chan, size, flags)
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struct device *isadev;
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_isa_dmamap_create(ids, chan, size, flags)
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struct isa_dma_state *ids;
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int chan;
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bus_size_t size;
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int flags;
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{
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struct isa_softc *sc = (struct isa_softc *)isadev;
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bus_size_t maxsize;
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if (chan < 0 || chan > 7) {
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printf("%s: bogus drq %d\n", sc->sc_dev.dv_xname, chan);
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printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan);
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goto lose;
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}
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@ -184,54 +222,54 @@ isa_dmamap_create(isadev, chan, size, flags)
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if (size > maxsize)
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return (EINVAL);
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if (ISA_DRQ_ISFREE(sc, chan) == 0) {
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printf("%s: drq %d is not free\n", sc->sc_dev.dv_xname, chan);
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if (ISA_DMA_DRQ_ISFREE(ids, chan) == 0) {
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printf("%s: drq %d is not free\n", ids->ids_dev->dv_xname,
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chan);
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goto lose;
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}
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ISA_DRQ_ALLOC(sc, chan);
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ISA_DMA_DRQ_ALLOC(ids, chan);
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return (bus_dmamap_create(sc->sc_dmat, size, 1, size, maxsize,
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flags, &sc->sc_dmamaps[chan]));
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return (bus_dmamap_create(ids->ids_dmat, size, 1, size, maxsize,
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flags, &ids->ids_dmamaps[chan]));
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lose:
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panic("isa_dmamap_create");
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panic("_isa_dmamap_create");
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}
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void
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isa_dmamap_destroy(isadev, chan)
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struct device *isadev;
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_isa_dmamap_destroy(ids, chan)
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struct isa_dma_state *ids;
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int chan;
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{
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struct isa_softc *sc = (struct isa_softc *)isadev;
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if (chan < 0 || chan > 7) {
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printf("%s: bogus drq %d\n", sc->sc_dev.dv_xname, chan);
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printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan);
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goto lose;
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}
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if (ISA_DRQ_ISFREE(sc, chan)) {
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if (ISA_DMA_DRQ_ISFREE(ids, chan)) {
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printf("%s: drq %d is already free\n",
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sc->sc_dev.dv_xname, chan);
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ids->ids_dev->dv_xname, chan);
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goto lose;
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}
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ISA_DRQ_FREE(sc, chan);
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ISA_DMA_DRQ_FREE(ids, chan);
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bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamaps[chan]);
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bus_dmamap_destroy(ids->ids_dmat, ids->ids_dmamaps[chan]);
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return;
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lose:
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panic("isa_dmamap_destroy");
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panic("_isa_dmamap_destroy");
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}
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/*
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* isa_dmastart(): program 8237 DMA controller channel and set it
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* _isa_dmastart(): program 8237 DMA controller channel and set it
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* in motion.
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*/
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int
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isa_dmastart(isadev, chan, addr, nbytes, p, flags, busdmaflags)
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struct device *isadev;
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_isa_dmastart(ids, chan, addr, nbytes, p, flags, busdmaflags)
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struct isa_dma_state *ids;
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int chan;
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void *addr;
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bus_size_t nbytes;
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@ -239,7 +277,6 @@ isa_dmastart(isadev, chan, addr, nbytes, p, flags, busdmaflags)
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int flags;
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int busdmaflags;
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{
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struct isa_softc *sc = (struct isa_softc *)isadev;
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bus_dmamap_t dmam;
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bus_addr_t dmaaddr;
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int waport;
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@ -247,12 +284,12 @@ isa_dmastart(isadev, chan, addr, nbytes, p, flags, busdmaflags)
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int error;
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if (chan < 0 || chan > 7) {
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printf("%s: bogus drq %d\n", sc->sc_dev.dv_xname, chan);
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printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan);
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goto lose;
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}
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#ifdef ISADMA_DEBUG
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printf("isa_dmastart: drq %d, addr %p, nbytes 0x%lx, p %p, "
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printf("_isa_dmastart: drq %d, addr %p, nbytes 0x%lx, p %p, "
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"flags 0x%x, dmaflags 0x%x\n",
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chan, addr, nbytes, p, flags, busdmaflags);
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#endif
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@ -260,22 +297,22 @@ isa_dmastart(isadev, chan, addr, nbytes, p, flags, busdmaflags)
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if (chan & 4) {
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if (nbytes > (1 << 17) || nbytes & 1 || (u_long)addr & 1) {
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printf("%s: drq %d, nbytes 0x%lx, addr %p\n",
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sc->sc_dev.dv_xname, chan, nbytes, addr);
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ids->ids_dev->dv_xname, chan, nbytes, addr);
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goto lose;
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}
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} else {
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if (nbytes > (1 << 16)) {
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printf("%s: drq %d, nbytes 0x%lx\n",
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sc->sc_dev.dv_xname, chan, nbytes);
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ids->ids_dev->dv_xname, chan, nbytes);
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goto lose;
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}
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}
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dmam = sc->sc_dmamaps[chan];
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dmam = ids->ids_dmamaps[chan];
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if (dmam == NULL)
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panic("isa_dmastart: no DMA map for chan %d\n", chan);
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panic("_isa_dmastart: no DMA map for chan %d\n", chan);
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error = bus_dmamap_load(sc->sc_dmat, dmam, addr, nbytes,
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error = bus_dmamap_load(ids->ids_dmat, dmam, addr, nbytes,
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p, busdmaflags);
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if (error)
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return (error);
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@ -285,13 +322,13 @@ isa_dmastart(isadev, chan, addr, nbytes, p, flags, busdmaflags)
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#endif
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if (flags & DMAMODE_READ) {
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bus_dmamap_sync(sc->sc_dmat, dmam, 0, dmam->dm_mapsize,
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bus_dmamap_sync(ids->ids_dmat, dmam, 0, dmam->dm_mapsize,
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BUS_DMASYNC_PREREAD);
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sc->sc_dmareads |= (1 << chan);
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ids->ids_dmareads |= (1 << chan);
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} else {
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bus_dmamap_sync(sc->sc_dmat, dmam, 0, dmam->dm_mapsize,
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bus_dmamap_sync(ids->ids_dmat, dmam, 0, dmam->dm_mapsize,
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BUS_DMASYNC_PREWRITE);
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sc->sc_dmareads &= ~(1 << chan);
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ids->ids_dmareads &= ~(1 << chan);
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}
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dmaaddr = dmam->dm_segs[0].ds_addr;
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@ -302,93 +339,91 @@ isa_dmastart(isadev, chan, addr, nbytes, p, flags, busdmaflags)
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__asm(".globl isa_dmastart_aftersync ; isa_dmastart_aftersync:");
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#endif
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sc->sc_dmalength[chan] = nbytes;
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ids->ids_dmalength[chan] = nbytes;
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isa_dmamask(sc, chan);
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sc->sc_dmafinished &= ~(1 << chan);
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_isa_dmamask(ids, chan);
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ids->ids_dmafinished &= ~(1 << chan);
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if ((chan & 4) == 0) {
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/* set dma channel mode */
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bus_space_write_1(sc->sc_iot, sc->sc_dma1h, DMA1_MODE,
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bus_space_write_1(ids->ids_bst, ids->ids_dma1h, DMA1_MODE,
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ochan | dmamode[flags]);
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/* send start address */
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waport = DMA1_CHN(ochan);
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bus_space_write_1(sc->sc_iot, sc->sc_dmapgh,
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bus_space_write_1(ids->ids_bst, ids->ids_dmapgh,
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dmapageport[0][ochan], (dmaaddr >> 16) & 0xff);
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bus_space_write_1(sc->sc_iot, sc->sc_dma1h, waport,
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bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport,
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dmaaddr & 0xff);
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bus_space_write_1(sc->sc_iot, sc->sc_dma1h, waport,
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bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport,
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(dmaaddr >> 8) & 0xff);
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/* send count */
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bus_space_write_1(sc->sc_iot, sc->sc_dma1h, waport + 1,
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bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport + 1,
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(--nbytes) & 0xff);
|
||||
bus_space_write_1(sc->sc_iot, sc->sc_dma1h, waport + 1,
|
||||
bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport + 1,
|
||||
(nbytes >> 8) & 0xff);
|
||||
} else {
|
||||
/* set dma channel mode */
|
||||
bus_space_write_1(sc->sc_iot, sc->sc_dma2h, DMA2_MODE,
|
||||
bus_space_write_1(ids->ids_bst, ids->ids_dma2h, DMA2_MODE,
|
||||
ochan | dmamode[flags]);
|
||||
|
||||
/* send start address */
|
||||
waport = DMA2_CHN(ochan);
|
||||
bus_space_write_1(sc->sc_iot, sc->sc_dmapgh,
|
||||
bus_space_write_1(ids->ids_bst, ids->ids_dmapgh,
|
||||
dmapageport[1][ochan], (dmaaddr >> 16) & 0xff);
|
||||
dmaaddr >>= 1;
|
||||
bus_space_write_1(sc->sc_iot, sc->sc_dma2h, waport,
|
||||
bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport,
|
||||
dmaaddr & 0xff);
|
||||
bus_space_write_1(sc->sc_iot, sc->sc_dma2h, waport,
|
||||
bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport,
|
||||
(dmaaddr >> 8) & 0xff);
|
||||
|
||||
/* send count */
|
||||
nbytes >>= 1;
|
||||
bus_space_write_1(sc->sc_iot, sc->sc_dma2h, waport + 2,
|
||||
bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport + 2,
|
||||
(--nbytes) & 0xff);
|
||||
bus_space_write_1(sc->sc_iot, sc->sc_dma2h, waport + 2,
|
||||
bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport + 2,
|
||||
(nbytes >> 8) & 0xff);
|
||||
}
|
||||
|
||||
isa_dmaunmask(sc, chan);
|
||||
_isa_dmaunmask(ids, chan);
|
||||
return (0);
|
||||
|
||||
lose:
|
||||
panic("isa_dmastart");
|
||||
panic("_isa_dmastart");
|
||||
}
|
||||
|
||||
void
|
||||
isa_dmaabort(isadev, chan)
|
||||
struct device *isadev;
|
||||
_isa_dmaabort(ids, chan)
|
||||
struct isa_dma_state *ids;
|
||||
int chan;
|
||||
{
|
||||
struct isa_softc *sc = (struct isa_softc *)isadev;
|
||||
|
||||
if (chan < 0 || chan > 7) {
|
||||
printf("%s: bogus drq %d\n", sc->sc_dev.dv_xname, chan);
|
||||
panic("isa_dmaabort");
|
||||
printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan);
|
||||
panic("_isa_dmaabort");
|
||||
}
|
||||
|
||||
isa_dmamask(sc, chan);
|
||||
bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamaps[chan]);
|
||||
sc->sc_dmareads &= ~(1 << chan);
|
||||
_isa_dmamask(ids, chan);
|
||||
bus_dmamap_unload(ids->ids_dmat, ids->ids_dmamaps[chan]);
|
||||
ids->ids_dmareads &= ~(1 << chan);
|
||||
}
|
||||
|
||||
bus_size_t
|
||||
isa_dmacount(isadev, chan)
|
||||
struct device *isadev;
|
||||
_isa_dmacount(ids, chan)
|
||||
struct isa_dma_state *ids;
|
||||
int chan;
|
||||
{
|
||||
struct isa_softc *sc = (struct isa_softc *)isadev;
|
||||
int waport;
|
||||
bus_size_t nbytes;
|
||||
int ochan = chan & 3;
|
||||
|
||||
if (chan < 0 || chan > 7) {
|
||||
printf("%s: bogus drq %d\n", sc->sc_dev.dv_xname, chan);
|
||||
printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan);
|
||||
panic("isa_dmacount");
|
||||
}
|
||||
|
||||
isa_dmamask(sc, chan);
|
||||
_isa_dmamask(ids, chan);
|
||||
|
||||
/*
|
||||
* We have to shift the byte count by 1. If we're in auto-initialize
|
||||
|
|
@ -400,102 +435,99 @@ isa_dmacount(isadev, chan)
|
|||
*/
|
||||
if ((chan & 4) == 0) {
|
||||
waport = DMA1_CHN(ochan);
|
||||
nbytes = bus_space_read_1(sc->sc_iot, sc->sc_dma1h,
|
||||
nbytes = bus_space_read_1(ids->ids_bst, ids->ids_dma1h,
|
||||
waport + 1) + 1;
|
||||
nbytes += bus_space_read_1(sc->sc_iot, sc->sc_dma1h,
|
||||
nbytes += bus_space_read_1(ids->ids_bst, ids->ids_dma1h,
|
||||
waport + 1) << 8;
|
||||
nbytes &= 0xffff;
|
||||
} else {
|
||||
waport = DMA2_CHN(ochan);
|
||||
nbytes = bus_space_read_1(sc->sc_iot, sc->sc_dma2h,
|
||||
nbytes = bus_space_read_1(ids->ids_bst, ids->ids_dma2h,
|
||||
waport + 2) + 1;
|
||||
nbytes += bus_space_read_1(sc->sc_iot, sc->sc_dma2h,
|
||||
nbytes += bus_space_read_1(ids->ids_bst, ids->ids_dma2h,
|
||||
waport + 2) << 8;
|
||||
nbytes <<= 1;
|
||||
nbytes &= 0x1ffff;
|
||||
}
|
||||
|
||||
if (nbytes == sc->sc_dmalength[chan])
|
||||
if (nbytes == ids->ids_dmalength[chan])
|
||||
nbytes = 0;
|
||||
|
||||
isa_dmaunmask(sc, chan);
|
||||
_isa_dmaunmask(ids, chan);
|
||||
return (nbytes);
|
||||
}
|
||||
|
||||
int
|
||||
isa_dmafinished(isadev, chan)
|
||||
struct device *isadev;
|
||||
_isa_dmafinished(ids, chan)
|
||||
struct isa_dma_state *ids;
|
||||
int chan;
|
||||
{
|
||||
struct isa_softc *sc = (struct isa_softc *)isadev;
|
||||
|
||||
if (chan < 0 || chan > 7) {
|
||||
printf("%s: bogus drq %d\n", sc->sc_dev.dv_xname, chan);
|
||||
panic("isa_dmafinished");
|
||||
printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan);
|
||||
panic("_isa_dmafinished");
|
||||
}
|
||||
|
||||
/* check that the terminal count was reached */
|
||||
if ((chan & 4) == 0)
|
||||
sc->sc_dmafinished |= bus_space_read_1(sc->sc_iot,
|
||||
sc->sc_dma1h, DMA1_SR) & 0x0f;
|
||||
ids->ids_dmafinished |= bus_space_read_1(ids->ids_bst,
|
||||
ids->ids_dma1h, DMA1_SR) & 0x0f;
|
||||
else
|
||||
sc->sc_dmafinished |= (bus_space_read_1(sc->sc_iot,
|
||||
sc->sc_dma2h, DMA2_SR) & 0x0f) << 4;
|
||||
ids->ids_dmafinished |= (bus_space_read_1(ids->ids_bst,
|
||||
ids->ids_dma2h, DMA2_SR) & 0x0f) << 4;
|
||||
|
||||
return ((sc->sc_dmafinished & (1 << chan)) != 0);
|
||||
return ((ids->ids_dmafinished & (1 << chan)) != 0);
|
||||
}
|
||||
|
||||
void
|
||||
isa_dmadone(isadev, chan)
|
||||
struct device *isadev;
|
||||
_isa_dmadone(ids, chan)
|
||||
struct isa_dma_state *ids;
|
||||
int chan;
|
||||
{
|
||||
struct isa_softc *sc = (struct isa_softc *)isadev;
|
||||
bus_dmamap_t dmam;
|
||||
|
||||
if (chan < 0 || chan > 7) {
|
||||
printf("%s: bogus drq %d\n", sc->sc_dev.dv_xname, chan);
|
||||
panic("isa_dmadone");
|
||||
printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan);
|
||||
panic("_isa_dmadone");
|
||||
}
|
||||
|
||||
dmam = sc->sc_dmamaps[chan];
|
||||
dmam = ids->ids_dmamaps[chan];
|
||||
|
||||
isa_dmamask(sc, chan);
|
||||
_isa_dmamask(ids, chan);
|
||||
|
||||
if (isa_dmafinished(isadev, chan) == 0)
|
||||
printf("%s: isa_dmadone: channel %d not finished\n",
|
||||
sc->sc_dev.dv_xname, chan);
|
||||
if (_isa_dmafinished(ids, chan) == 0)
|
||||
printf("%s: _isa_dmadone: channel %d not finished\n",
|
||||
ids->ids_dev->dv_xname, chan);
|
||||
|
||||
bus_dmamap_sync(sc->sc_dmat, dmam, 0, dmam->dm_mapsize,
|
||||
(sc->sc_dmareads & (1 << chan)) ? BUS_DMASYNC_POSTREAD :
|
||||
bus_dmamap_sync(ids->ids_dmat, dmam, 0, dmam->dm_mapsize,
|
||||
(ids->ids_dmareads & (1 << chan)) ? BUS_DMASYNC_POSTREAD :
|
||||
BUS_DMASYNC_POSTWRITE);
|
||||
|
||||
bus_dmamap_unload(sc->sc_dmat, dmam);
|
||||
sc->sc_dmareads &= ~(1 << chan);
|
||||
bus_dmamap_unload(ids->ids_dmat, dmam);
|
||||
ids->ids_dmareads &= ~(1 << chan);
|
||||
}
|
||||
|
||||
int
|
||||
isa_dmamem_alloc(isadev, chan, size, addrp, flags)
|
||||
struct device *isadev;
|
||||
_isa_dmamem_alloc(ids, chan, size, addrp, flags)
|
||||
struct isa_dma_state *ids;
|
||||
int chan;
|
||||
bus_size_t size;
|
||||
bus_addr_t *addrp;
|
||||
int flags;
|
||||
{
|
||||
struct isa_softc *sc = (struct isa_softc *)isadev;
|
||||
bus_dma_segment_t seg;
|
||||
int error, boundary, rsegs;
|
||||
|
||||
if (chan < 0 || chan > 7) {
|
||||
printf("%s: bogus drq %d\n", sc->sc_dev.dv_xname, chan);
|
||||
panic("isa_dmamem_alloc");
|
||||
printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan);
|
||||
panic("_isa_dmamem_alloc");
|
||||
}
|
||||
|
||||
boundary = (chan & 4) ? (1 << 17) : (1 << 16);
|
||||
|
||||
size = round_page(size);
|
||||
|
||||
error = bus_dmamem_alloc(sc->sc_dmat, size, NBPG, boundary,
|
||||
error = bus_dmamem_alloc(ids->ids_dmat, size, NBPG, boundary,
|
||||
&seg, 1, &rsegs, flags);
|
||||
if (error)
|
||||
return (error);
|
||||
|
|
@ -505,104 +537,101 @@ isa_dmamem_alloc(isadev, chan, size, addrp, flags)
|
|||
}
|
||||
|
||||
void
|
||||
isa_dmamem_free(isadev, chan, addr, size)
|
||||
struct device *isadev;
|
||||
_isa_dmamem_free(ids, chan, addr, size)
|
||||
struct isa_dma_state *ids;
|
||||
int chan;
|
||||
bus_addr_t addr;
|
||||
bus_size_t size;
|
||||
{
|
||||
struct isa_softc *sc = (struct isa_softc *)isadev;
|
||||
bus_dma_segment_t seg;
|
||||
|
||||
if (chan < 0 || chan > 7) {
|
||||
printf("%s: bogus drq %d\n", sc->sc_dev.dv_xname, chan);
|
||||
panic("isa_dmamem_free");
|
||||
printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan);
|
||||
panic("_isa_dmamem_free");
|
||||
}
|
||||
|
||||
seg.ds_addr = addr;
|
||||
seg.ds_len = size;
|
||||
|
||||
bus_dmamem_free(sc->sc_dmat, &seg, 1);
|
||||
bus_dmamem_free(ids->ids_dmat, &seg, 1);
|
||||
}
|
||||
|
||||
int
|
||||
isa_dmamem_map(isadev, chan, addr, size, kvap, flags)
|
||||
struct device *isadev;
|
||||
_isa_dmamem_map(ids, chan, addr, size, kvap, flags)
|
||||
struct isa_dma_state *ids;
|
||||
int chan;
|
||||
bus_addr_t addr;
|
||||
bus_size_t size;
|
||||
caddr_t *kvap;
|
||||
int flags;
|
||||
{
|
||||
struct isa_softc *sc = (struct isa_softc *)isadev;
|
||||
bus_dma_segment_t seg;
|
||||
|
||||
if (chan < 0 || chan > 7) {
|
||||
printf("%s: bogus drq %d\n", sc->sc_dev.dv_xname, chan);
|
||||
panic("isa_dmamem_map");
|
||||
printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan);
|
||||
panic("_isa_dmamem_map");
|
||||
}
|
||||
|
||||
seg.ds_addr = addr;
|
||||
seg.ds_len = size;
|
||||
|
||||
return (bus_dmamem_map(sc->sc_dmat, &seg, 1, size, kvap, flags));
|
||||
return (bus_dmamem_map(ids->ids_dmat, &seg, 1, size, kvap, flags));
|
||||
}
|
||||
|
||||
void
|
||||
isa_dmamem_unmap(isadev, chan, kva, size)
|
||||
struct device *isadev;
|
||||
_isa_dmamem_unmap(ids, chan, kva, size)
|
||||
struct isa_dma_state *ids;
|
||||
int chan;
|
||||
caddr_t kva;
|
||||
size_t size;
|
||||
{
|
||||
struct isa_softc *sc = (struct isa_softc *)isadev;
|
||||
|
||||
if (chan < 0 || chan > 7) {
|
||||
printf("%s: bogus drq %d\n", sc->sc_dev.dv_xname, chan);
|
||||
panic("isa_dmamem_unmap");
|
||||
printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan);
|
||||
panic("_isa_dmamem_unmap");
|
||||
}
|
||||
|
||||
bus_dmamem_unmap(sc->sc_dmat, kva, size);
|
||||
bus_dmamem_unmap(ids->ids_dmat, kva, size);
|
||||
}
|
||||
|
||||
int
|
||||
isa_dmamem_mmap(isadev, chan, addr, size, off, prot, flags)
|
||||
struct device *isadev;
|
||||
_isa_dmamem_mmap(ids, chan, addr, size, off, prot, flags)
|
||||
struct isa_dma_state *ids;
|
||||
int chan;
|
||||
bus_addr_t addr;
|
||||
bus_size_t size;
|
||||
int off, prot, flags;
|
||||
{
|
||||
struct isa_softc *sc = (struct isa_softc *)isadev;
|
||||
bus_dma_segment_t seg;
|
||||
|
||||
if (chan < 0 || chan > 7) {
|
||||
printf("%s: bogus drq %d\n", sc->sc_dev.dv_xname, chan);
|
||||
panic("isa_dmamem_mmap");
|
||||
printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan);
|
||||
panic("_isa_dmamem_mmap");
|
||||
}
|
||||
|
||||
seg.ds_addr = addr;
|
||||
seg.ds_len = size;
|
||||
|
||||
return (bus_dmamem_mmap(sc->sc_dmat, &seg, 1, off, prot, flags));
|
||||
return (bus_dmamem_mmap(ids->ids_dmat, &seg, 1, off, prot, flags));
|
||||
}
|
||||
|
||||
int
|
||||
isa_drq_isfree(isadev, chan)
|
||||
struct device *isadev;
|
||||
_isa_drq_isfree(ids, chan)
|
||||
struct isa_dma_state *ids;
|
||||
int chan;
|
||||
{
|
||||
struct isa_softc *sc = (struct isa_softc *)isadev;
|
||||
|
||||
if (chan < 0 || chan > 7) {
|
||||
printf("%s: bogus drq %d\n", sc->sc_dev.dv_xname, chan);
|
||||
panic("isa_drq_isfree");
|
||||
printf("%s: bogus drq %d\n", ids->ids_dev->dv_xname, chan);
|
||||
panic("_isa_drq_isfree");
|
||||
}
|
||||
return ISA_DRQ_ISFREE(sc, chan);
|
||||
|
||||
return ISA_DMA_DRQ_ISFREE(ids, chan);
|
||||
}
|
||||
|
||||
void *
|
||||
isa_malloc(isadev, chan, size, pool, flags)
|
||||
struct device *isadev;
|
||||
_isa_malloc(ids, chan, size, pool, flags)
|
||||
struct isa_dma_state *ids;
|
||||
int chan;
|
||||
size_t size;
|
||||
int pool;
|
||||
|
|
@ -615,19 +644,19 @@ isa_malloc(isadev, chan, size, pool, flags)
|
|||
|
||||
bflags = flags & M_WAITOK ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT;
|
||||
|
||||
if (isa_dmamem_alloc(isadev, chan, size, &addr, bflags))
|
||||
if (_isa_dmamem_alloc(ids, chan, size, &addr, bflags))
|
||||
return 0;
|
||||
if (isa_dmamem_map(isadev, chan, addr, size, &kva, bflags)) {
|
||||
isa_dmamem_free(isadev, chan, addr, size);
|
||||
if (_isa_dmamem_map(ids, chan, addr, size, &kva, bflags)) {
|
||||
_isa_dmamem_free(ids, chan, addr, size);
|
||||
return 0;
|
||||
}
|
||||
m = malloc(sizeof(*m), pool, flags);
|
||||
if (m == 0) {
|
||||
isa_dmamem_unmap(isadev, chan, kva, size);
|
||||
isa_dmamem_free(isadev, chan, addr, size);
|
||||
_isa_dmamem_unmap(ids, chan, kva, size);
|
||||
_isa_dmamem_free(ids, chan, addr, size);
|
||||
return 0;
|
||||
}
|
||||
m->isadev = isadev;
|
||||
m->ids = ids;
|
||||
m->chan = chan;
|
||||
m->size = size;
|
||||
m->addr = addr;
|
||||
|
|
@ -638,28 +667,29 @@ isa_malloc(isadev, chan, size, pool, flags)
|
|||
}
|
||||
|
||||
void
|
||||
isa_free(addr, pool)
|
||||
_isa_free(addr, pool)
|
||||
void *addr;
|
||||
int pool;
|
||||
{
|
||||
struct isa_mem **mp, *m;
|
||||
caddr_t kva = (caddr_t)addr;
|
||||
|
||||
for(mp = &isa_mem_head; *mp && (*mp)->kva != kva; mp = &(*mp)->next)
|
||||
for(mp = &isa_mem_head; *mp && (*mp)->kva != kva;
|
||||
mp = &(*mp)->next)
|
||||
;
|
||||
m = *mp;
|
||||
if (!m) {
|
||||
printf("isa_free: freeing unallocted memory\n");
|
||||
printf("_isa_free: freeing unallocted memory\n");
|
||||
return;
|
||||
}
|
||||
*mp = m->next;
|
||||
isa_dmamem_unmap(m->isadev, m->chan, kva, m->size);
|
||||
isa_dmamem_free(m->isadev, m->chan, m->addr, m->size);
|
||||
_isa_dmamem_unmap(m->ids, m->chan, kva, m->size);
|
||||
_isa_dmamem_free(m->ids, m->chan, m->addr, m->size);
|
||||
free(m, pool);
|
||||
}
|
||||
|
||||
int
|
||||
isa_mappage(mem, off, prot)
|
||||
_isa_mappage(mem, off, prot)
|
||||
void *mem;
|
||||
int off;
|
||||
int prot;
|
||||
|
|
@ -669,9 +699,9 @@ isa_mappage(mem, off, prot)
|
|||
for(m = isa_mem_head; m && m->kva != (caddr_t)mem; m = m->next)
|
||||
;
|
||||
if (!m) {
|
||||
printf("isa_mappage: mapping unallocted memory\n");
|
||||
printf("_isa_mappage: mapping unallocted memory\n");
|
||||
return -1;
|
||||
}
|
||||
return isa_dmamem_mmap(m->isadev, m->chan, m->addr,
|
||||
m->size, off, prot, BUS_DMA_WAITOK);
|
||||
return _isa_dmamem_mmap(m->ids, m->chan, m->addr,
|
||||
m->size, off, prot, BUS_DMA_WAITOK);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/* $NetBSD: isadmavar.h,v 1.10 1997/08/04 22:13:33 augustss Exp $ */
|
||||
/* $NetBSD: isadmavar.h,v 1.11 1998/06/09 00:00:21 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997 The NetBSD Foundation, Inc.
|
||||
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
|
|
@ -37,37 +37,91 @@
|
|||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _DEV_ISA_ISADMAVAR_H_
|
||||
#define _DEV_ISA_ISADMAVAR_H_
|
||||
|
||||
#define MAX_ISADMA 65536
|
||||
|
||||
#define DMAMODE_WRITE 0
|
||||
#define DMAMODE_READ 1
|
||||
#define DMAMODE_LOOP 2
|
||||
|
||||
/*
|
||||
* ISA DMA state. This structure is provided by the ISA chipset
|
||||
* DMA entry points to the generic back-end functions that actually
|
||||
* frob the controller.
|
||||
*/
|
||||
struct isa_dma_state {
|
||||
struct device *ids_dev; /* associated device (for dv_xname) */
|
||||
bus_space_tag_t ids_bst; /* bus space tag for DMA controller */
|
||||
bus_space_handle_t ids_dma1h; /* handle for DMA controller #1 */
|
||||
bus_space_handle_t ids_dma2h; /* handle for DMA controller #2 */
|
||||
bus_space_handle_t ids_dmapgh; /* handle for DMA page registers */
|
||||
bus_dma_tag_t ids_dmat; /* DMA tag for DMA controller */
|
||||
bus_dmamap_t ids_dmamaps[8]; /* DMA maps for each channel */
|
||||
bus_size_t ids_dmalength[8]; /* size of DMA transfer per channel */
|
||||
int ids_drqmap; /* available DRQs (bitmap) */
|
||||
int ids_dmareads; /* state for isa_dmadone() (bitmap) */
|
||||
int ids_dmafinished; /* DMA completion state (bitmap) */
|
||||
int ids_initialized; /* only initialize once... */
|
||||
};
|
||||
|
||||
#define ISA_DMA_DRQ_ISFREE(state, drq) \
|
||||
(((state)->ids_drqmap & (1 << (drq))) == 0)
|
||||
|
||||
#define ISA_DMA_DRQ_ALLOC(state, drq) \
|
||||
(state)->ids_drqmap |= (1 << (drq))
|
||||
|
||||
#define ISA_DMA_DRQ_FREE(state, drq) \
|
||||
(state)->ids_drqmap &= ~(1 << (drq))
|
||||
|
||||
/*
|
||||
* Memory list used by _isa_malloc().
|
||||
*/
|
||||
struct isa_mem {
|
||||
struct isa_dma_state *ids;
|
||||
int chan;
|
||||
bus_size_t size;
|
||||
bus_addr_t addr;
|
||||
caddr_t kva;
|
||||
struct isa_mem *next;
|
||||
};
|
||||
|
||||
#ifdef _KERNEL
|
||||
struct proc;
|
||||
|
||||
void isa_dmacascade __P((struct device *, int));
|
||||
void _isa_dmainit __P((struct isa_dma_state *, bus_space_tag_t,
|
||||
bus_dma_tag_t, struct device *));
|
||||
|
||||
int isa_dmamap_create __P((struct device *, int, bus_size_t, int));
|
||||
void isa_dmamap_destroy __P((struct device *, int));
|
||||
void _isa_dmacascade __P((struct isa_dma_state *, int));
|
||||
|
||||
int isa_dmastart __P((struct device *, int, void *, bus_size_t,
|
||||
int _isa_dmamap_create __P((struct isa_dma_state *, int,
|
||||
bus_size_t, int));
|
||||
void _isa_dmamap_destroy __P((struct isa_dma_state *, int));
|
||||
|
||||
int _isa_dmastart __P((struct isa_dma_state *, int, void *, bus_size_t,
|
||||
struct proc *, int, int));
|
||||
void isa_dmaabort __P((struct device *, int));
|
||||
bus_size_t isa_dmacount __P((struct device *, int));
|
||||
int isa_dmafinished __P((struct device *, int));
|
||||
void isa_dmadone __P((struct device *, int));
|
||||
void _isa_dmaabort __P((struct isa_dma_state *, int));
|
||||
bus_size_t _isa_dmacount __P((struct isa_dma_state *, int));
|
||||
int _isa_dmafinished __P((struct isa_dma_state *, int));
|
||||
void _isa_dmadone __P((struct isa_dma_state *, int));
|
||||
|
||||
int isa_dmamem_alloc __P((struct device *, int, bus_size_t,
|
||||
int _isa_dmamem_alloc __P((struct isa_dma_state *, int, bus_size_t,
|
||||
bus_addr_t *, int));
|
||||
void isa_dmamem_free __P((struct device *, int, bus_addr_t, bus_size_t));
|
||||
int isa_dmamem_map __P((struct device *, int, bus_addr_t, bus_size_t,
|
||||
caddr_t *, int));
|
||||
void isa_dmamem_unmap __P((struct device *, int, caddr_t, size_t));
|
||||
int isa_dmamem_mmap __P((struct device *, int, bus_addr_t, bus_size_t,
|
||||
int, int, int));
|
||||
void _isa_dmamem_free __P((struct isa_dma_state *, int, bus_addr_t,
|
||||
bus_size_t));
|
||||
int _isa_dmamem_map __P((struct isa_dma_state *, int, bus_addr_t,
|
||||
bus_size_t, caddr_t *, int));
|
||||
void _isa_dmamem_unmap __P((struct isa_dma_state *, int, caddr_t,
|
||||
size_t));
|
||||
int _isa_dmamem_mmap __P((struct isa_dma_state *, int, bus_addr_t,
|
||||
bus_size_t, int, int, int));
|
||||
|
||||
int isa_drq_isfree __P((struct device *, int));
|
||||
int _isa_drq_isfree __P((struct isa_dma_state *, int));
|
||||
|
||||
void *isa_malloc __P((struct device *, int, size_t, int, int));
|
||||
void isa_free __P((void *, int));
|
||||
int isa_mappage __P((void *, int, int));
|
||||
void *_isa_malloc __P((struct isa_dma_state *, int, size_t, int, int));
|
||||
void _isa_free __P((void *, int));
|
||||
int _isa_mappage __P((void *, int, int));
|
||||
#endif /* _KERNEL */
|
||||
|
||||
#endif /* _DEV_ISA_ISADMAVAR_H_ */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: isavar.h,v 1.32 1998/04/15 01:44:23 thorpej Exp $ */
|
||||
/* $NetBSD: isavar.h,v 1.33 1998/06/09 00:00:21 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997 The NetBSD Foundation, Inc.
|
||||
|
|
@ -167,36 +167,8 @@ struct isa_softc {
|
|||
bus_dma_tag_t sc_dmat; /* isa DMA tag */
|
||||
|
||||
isa_chipset_tag_t sc_ic;
|
||||
|
||||
/*
|
||||
* Bitmap representing the DRQ channels available
|
||||
* for ISA.
|
||||
*/
|
||||
int sc_drqmap;
|
||||
|
||||
bus_space_handle_t sc_dma1h; /* i/o handle for DMA controller #1 */
|
||||
bus_space_handle_t sc_dma2h; /* i/o handle for DMA controller #2 */
|
||||
bus_space_handle_t sc_dmapgh; /* i/o handle for DMA page registers */
|
||||
|
||||
/*
|
||||
* DMA maps used for the 8 DMA channels.
|
||||
*/
|
||||
bus_dmamap_t sc_dmamaps[8];
|
||||
vm_size_t sc_dmalength[8];
|
||||
|
||||
int sc_dmareads; /* state for isa_dmadone() */
|
||||
int sc_dmafinished; /* DMA completion state */
|
||||
};
|
||||
|
||||
#define ISA_DRQ_ISFREE(isadev, drq) \
|
||||
((((struct isa_softc *)(isadev))->sc_drqmap & (1 << (drq))) == 0)
|
||||
|
||||
#define ISA_DRQ_ALLOC(isadev, drq) \
|
||||
((struct isa_softc *)(isadev))->sc_drqmap |= (1 << (drq))
|
||||
|
||||
#define ISA_DRQ_FREE(isadev, drq) \
|
||||
((struct isa_softc *)(isadev))->sc_drqmap &= ~(1 << (drq))
|
||||
|
||||
#define cf_iobase cf_loc[ISACF_PORT]
|
||||
#define cf_iosize cf_loc[ISACF_SIZE]
|
||||
#define cf_maddr cf_loc[ISACF_IOMEM]
|
||||
|
|
|
|||
Loading…
Reference in New Issue