Split the ug(4) driver in three components:
* dev/ic/ug.c (main code shared by the attachments) * dev/isa/ug_isa.c (isa attachment) * dev/acpi/ug_acpi.c (acpi attachment) That means that ug(4) can now be attached via ACPI. Thanks to Mihai Chelaru for the good work.
This commit is contained in:
xtraeme
parent
8e2e7c23e6
commit
ff1c414804
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@ -1,4 +1,4 @@
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# $NetBSD: files,v 1.842 2007/05/08 06:10:27 manu Exp $
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# $NetBSD: files,v 1.843 2007/05/08 16:48:37 xtraeme Exp $
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# @(#)files.newconf 7.5 (Berkeley) 5/10/93
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@ -785,6 +785,11 @@ file dev/ic/clmpcc.c clmpcc needs-flag
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device lm: sysmon_envsys
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file dev/ic/nslm7x.c lm needs-flag
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# Abit uGuru
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#
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device ug: sysmon_envsys
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file dev/ic/ug.c ug needs-flag
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# Essential Communications Corp. HIPPI Interface
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#
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device esh: hippi, ifnet
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@ -1,4 +1,4 @@
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# $NetBSD: files.acpi,v 1.44 2007/03/14 00:43:04 xtraeme Exp $
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# $NetBSD: files.acpi,v 1.45 2007/05/08 16:48:37 xtraeme Exp $
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include "dev/acpi/acpica/files.acpica"
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@ -104,3 +104,7 @@ file dev/acpi/hpet_acpi.c hpet_acpi
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device aiboost: sysmon_envsys
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attach aiboost at acpinodebus
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file dev/acpi/aiboost.c aiboost
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# Abit uGuru 2005
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attach ug at acpinodebus with ug_acpi
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file dev/acpi/ug_acpi.c ug_acpi
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@ -0,0 +1,121 @@
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/* $NetBSD: ug_acpi.c,v 1.1 2007/05/08 16:48:38 xtraeme Exp $ */
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/*
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* Copyright (c) 2007 Mihai Chelaru <kefren@netbsd.ro>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/syslog.h>
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#include <sys/device.h>
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#include <sys/proc.h>
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#include <sys/envsys.h>
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#include <machine/bus.h>
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#include <dev/acpi/acpica.h>
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#include <dev/acpi/acpireg.h>
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#include <dev/acpi/acpivar.h>
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#include <dev/sysmon/sysmonvar.h>
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#include <dev/ic/ugreg.h>
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#include <dev/ic/ugvar.h>
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/* autoconf(9) functions */
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static int ug_acpi_match(struct device *, struct cfdata *, void *);
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static void ug_acpi_attach(struct device *, struct device *, void *);
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CFATTACH_DECL(ug_acpi, sizeof(struct ug_softc), ug_acpi_match,
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ug_acpi_attach, NULL, NULL);
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/*
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* Supported devices
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* XXX: only uGuru 2005 for now
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*/
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static const char* const ug_acpi_ids[] = {
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"ABT2005", /* uGuru 2005 */
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NULL
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};
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static int
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ug_acpi_match(struct device *parent, struct cfdata *match,
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void *aux)
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{
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struct acpi_attach_args *aa = aux;
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if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE)
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return 0;
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return acpi_match_hid(aa->aa_node->ad_devinfo, ug_acpi_ids);
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}
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static void
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ug_acpi_attach(struct device *parent, struct device *self, void *aux)
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{
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struct ug_softc *sc = (struct ug_softc*)self;
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struct acpi_attach_args *aa = aux;
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struct acpi_resources res;
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struct acpi_io *io;
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bus_space_handle_t ioh;
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ACPI_STATUS rv;
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aprint_naive("\n");
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aprint_normal("\n");
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/* parse resources */
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rv = acpi_resource_parse(&sc->sc_dev, aa->aa_node->ad_handle, "_CRS",
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&res, &acpi_resource_parse_ops_default);
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if (ACPI_FAILURE(rv))
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return;
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/* find our i/o registers */
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io = acpi_res_io(&res, 0);
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if (io == NULL) {
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aprint_error("%s: unable to find i/o register resource\n",
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sc->sc_dev.dv_xname);
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acpi_resource_cleanup(&res);
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return;
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}
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if (bus_space_map(aa->aa_iot, io->ar_base, io->ar_length,
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0, &ioh)) {
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aprint_error("%s: can't map i/o space\n",
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sc->sc_dev.dv_xname);
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acpi_resource_cleanup(&res);
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return;
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}
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aprint_normal("%s", sc->sc_dev.dv_xname);
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sc->version = 2; /* uGuru 2005 */
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sc->sc_ioh = ioh;
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sc->sc_iot = aa->aa_iot;
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ug2_attach(sc);
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acpi_resource_cleanup(&res);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: ug.c,v 1.4 2007/05/07 07:48:28 xtraeme Exp $ */
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/* $NetBSD: ug.c,v 1.1 2007/05/08 16:48:38 xtraeme Exp $ */
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/*
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* Copyright (c) 2007 Mihai Chelaru <kefren@netbsd.ro>
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@ -25,14 +25,7 @@
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Driver for Abit uGuru (interface is inspired from it.c and nslm7x.c)
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* Inspired by olle sandberg linux driver as Abit didn't care to release docs
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* Support for uGuru 2005 from Louis Kruger and Hans de Goede linux driver
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ug.c,v 1.4 2007/05/07 07:48:28 xtraeme Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -53,137 +46,277 @@ __KERNEL_RCSID(0, "$NetBSD: ug.c,v 1.4 2007/05/07 07:48:28 xtraeme Exp $");
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#include <dev/sysmon/sysmonvar.h>
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#include <dev/isa/ugvar.h>
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#include <dev/ic/ugreg.h>
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#include <dev/ic/ugvar.h>
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/* autoconf(9) functions */
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static int ug_isa_match(struct device *, struct cfdata *, void *);
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static void ug_isa_attach(struct device *, struct device *, void *);
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uint8_t ug_ver;
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CFATTACH_DECL(ug_isa, sizeof(struct ug_softc),
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ug_isa_match, ug_isa_attach, NULL, NULL);
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/*
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* Imported from linux driver
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*/
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/* driver internal functions */
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int ug_reset(struct ug_softc *);
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uint8_t ug_read(struct ug_softc *, unsigned short);
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int ug_waitfor(struct ug_softc *, uint16_t, uint8_t);
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void ug_setup_sensors(struct ug_softc*);
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void ug2_attach(struct ug_softc*);
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int ug2_wait_ready(struct ug_softc*);
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int ug2_wait_readable(struct ug_softc*);
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int ug2_sync(struct ug_softc*);
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int ug2_read(struct ug_softc*, uint8_t, uint8_t, uint8_t, uint8_t*);
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struct ug2_motherboard_info ug2_mb[] = {
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{ 0x000C, "unknown. Please send-pr(1)", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 10, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
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{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
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{ "MCH 2.5V", 5, 0, 20, 1, 0 },
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{ "ICH 1.05V", 6, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "System", 25, 1, 1, 1, 0 },
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{ "PWM", 26, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS FAN", 34, 2, 60, 1, 0 },
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{ "AUX1 Fan", 35, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x000D, "Abit AW8", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 10, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
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{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
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{ "MCH 2.5V", 5, 0, 20, 1, 0 },
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{ "ICH 1.05V", 6, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "System", 25, 1, 1, 1, 0 },
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{ "PWM1", 26, 1, 1, 1, 0 },
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{ "PWM2", 27, 1, 1, 1, 0 },
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{ "PWM3", 28, 1, 1, 1, 0 },
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{ "PWM4", 29, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS Fan", 34, 2, 60, 1, 0 },
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{ "AUX1 Fan", 35, 2, 60, 1, 0 },
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{ "AUX2 Fan", 36, 2, 60, 1, 0 },
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{ "AUX3 Fan", 37, 2, 60, 1, 0 },
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{ "AUX4 Fan", 38, 2, 60, 1, 0 },
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{ "AUX5 Fan", 39, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x000E, "Abit AL8", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 10, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
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{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
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{ "MCH 2.5V", 5, 0, 20, 1, 0 },
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{ "ICH 1.05V", 6, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "System", 25, 1, 1, 1, 0 },
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{ "PWM", 26, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS Fan", 34, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x000F, "unknown. Please send-pr(1)", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 10, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
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{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
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{ "MCH 2.5V", 5, 0, 20, 1, 0 },
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{ "ICH 1.05V", 6, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "System", 25, 1, 1, 1, 0 },
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{ "PWM", 26, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS Fan", 34, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x0010, "Abit NI8 SLI GR", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 10, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
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{ "NB 1.4V", 4, 0, 10, 1, 0 },
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{ "SB 1.5V", 6, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "SYS", 25, 1, 1, 1, 0 },
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{ "PWM", 26, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS Fan", 34, 2, 60, 1, 0 },
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{ "AUX1 Fan", 35, 2, 60, 1, 0 },
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{ "OTES1 Fan", 36, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x0011, "Abit AT8 32X", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 20, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "CPU VDDA 2.5V", 6, 0, 20, 1, 0 },
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{ "NB 1.8V", 4, 0, 10, 1, 0 },
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{ "NB 1.8V Dual", 5, 0, 10, 1, 0 },
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{ "HTV 1.2", 3, 0, 10, 1, 0 },
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{ "PCIE 1.2V", 12, 0, 10, 1, 0 },
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{ "NB 1.2V", 13, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "NB", 25, 1, 1, 1, 0 },
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{ "System", 26, 1, 1, 1, 0 },
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{ "PWM", 27, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS Fan", 34, 2, 60, 1, 0 },
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{ "AUX1 Fan", 35, 2, 60, 1, 0 },
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{ "AUX2 Fan", 36, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x0012, "unknown. Please send-pr(1)", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 20, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "HyperTransport", 3, 0, 10, 1, 0 },
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{ "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
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{ "NB", 4, 0, 10, 1, 0 },
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{ "SB", 6, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "SYS", 25, 1, 1, 1, 0 },
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{ "PWM", 26, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS Fan", 34, 2, 60, 1, 0 },
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{ "AUX1 Fan", 36, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x0013, "unknown. Please send-pr(1)", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 10, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
|
||||
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
|
||||
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
|
||||
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
|
||||
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
|
||||
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
||||
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
||||
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
||||
{ "+3.3V", 10, 0, 20, 1, 0 },
|
||||
{ "5VSB", 11, 0, 30, 1, 0 },
|
||||
{ "CPU", 24, 1, 1, 1, 0 },
|
||||
{ "System", 25, 1, 1, 1, 0 },
|
||||
{ "PWM1", 26, 1, 1, 1, 0 },
|
||||
{ "PWM2", 27, 1, 1, 1, 0 },
|
||||
{ "PWM3", 28, 1, 1, 1, 0 },
|
||||
{ "PWM4", 29, 1, 1, 1, 0 },
|
||||
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
||||
{ "NB Fan", 33, 2, 60, 1, 0 },
|
||||
{ "SYS Fan", 34, 2, 60, 1, 0 },
|
||||
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
|
||||
{ "AUX2 Fan", 36, 2, 60, 1, 0 },
|
||||
{ "AUX3 Fan", 37, 2, 60, 1, 0 },
|
||||
{ "AUX4 Fan", 38, 2, 60, 1, 0 },
|
||||
{ NULL, 0, 0, 0, 0, 0 } }
|
||||
},
|
||||
{ 0x0014, "Abit AB9 Pro", {
|
||||
{ "CPU Core", 0, 0, 10, 1, 0 },
|
||||
{ "DDR", 1, 0, 10, 1, 0 },
|
||||
{ "DDR VTT", 2, 0, 10, 1, 0 },
|
||||
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
|
||||
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
|
||||
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
|
||||
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
|
||||
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
||||
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
||||
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
||||
{ "+3.3V", 10, 0, 20, 1, 0 },
|
||||
{ "5VSB", 11, 0, 30, 1, 0 },
|
||||
{ "CPU", 24, 1, 1, 1, 0 },
|
||||
{ "System", 25, 1, 1, 1, 0 },
|
||||
{ "PWM", 26, 1, 1, 1, 0 },
|
||||
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
||||
{ "NB Fan", 33, 2, 60, 1, 0 },
|
||||
{ "SYS Fan", 34, 2, 60, 1, 0 },
|
||||
{ NULL, 0, 0, 0, 0, 0 } }
|
||||
},
|
||||
{ 0x0015, "unknown. Please send-pr(1)", {
|
||||
{ "CPU Core", 0, 0, 10, 1, 0 },
|
||||
{ "DDR", 1, 0, 20, 1, 0 },
|
||||
{ "DDR VTT", 2, 0, 10, 1, 0 },
|
||||
{ "HyperTransport", 3, 0, 10, 1, 0 },
|
||||
{ "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
|
||||
{ "NB", 4, 0, 10, 1, 0 },
|
||||
{ "SB", 6, 0, 10, 1, 0 },
|
||||
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
||||
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
||||
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
||||
{ "+3.3V", 10, 0, 20, 1, 0 },
|
||||
{ "5VSB", 11, 0, 30, 1, 0 },
|
||||
{ "CPU", 24, 1, 1, 1, 0 },
|
||||
{ "SYS", 25, 1, 1, 1, 0 },
|
||||
{ "PWM", 26, 1, 1, 1, 0 },
|
||||
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
||||
{ "NB Fan", 33, 2, 60, 1, 0 },
|
||||
{ "SYS Fan", 34, 2, 60, 1, 0 },
|
||||
{ "AUX1 Fan", 33, 2, 60, 1, 0 },
|
||||
{ "AUX2 Fan", 35, 2, 60, 1, 0 },
|
||||
{ "AUX3 Fan", 36, 2, 60, 1, 0 },
|
||||
{ NULL, 0, 0, 0, 0, 0 } }
|
||||
},
|
||||
{ 0x0016, "generic", {
|
||||
{ "CPU Core", 0, 0, 10, 1, 0 },
|
||||
{ "DDR", 1, 0, 20, 1, 0 },
|
||||
{ "DDR VTT", 2, 0, 10, 1, 0 },
|
||||
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
|
||||
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
|
||||
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
|
||||
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
|
||||
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
||||
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
||||
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
||||
{ "+3.3V", 10, 0, 20, 1, 0 },
|
||||
{ "5VSB", 11, 0, 30, 1, 0 },
|
||||
{ "CPU", 24, 1, 1, 1, 0 },
|
||||
{ "System", 25, 1, 1, 1, 0 },
|
||||
{ "PWM", 26, 1, 1, 1, 0 },
|
||||
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
||||
{ "NB Fan", 33, 2, 60, 1, 0 },
|
||||
{ "SYS FAN", 34, 2, 60, 1, 0 },
|
||||
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
|
||||
{ NULL, 0, 0, 0, 0, 0 } }
|
||||
},
|
||||
{ 0x0000, NULL, { { NULL, 0, 0, 0, 0, 0 } } }
|
||||
};
|
||||
|
||||
/* envsys(9) glue */
|
||||
static int ug_gtredata(struct sysmon_envsys *, envsys_tre_data_t *);
|
||||
static int ug2_gtredata(struct sysmon_envsys *, envsys_tre_data_t *);
|
||||
static int ug_streinfo_ni(struct sysmon_envsys *, envsys_basic_info_t *);
|
||||
|
||||
static uint8_t ug_ver;
|
||||
|
||||
static int
|
||||
ug_isa_match(struct device *parent, struct cfdata *match, void *aux)
|
||||
{
|
||||
struct isa_attach_args *ia = aux;
|
||||
struct ug_softc wrap_sc;
|
||||
bus_space_handle_t bsh;
|
||||
uint8_t valc, vald;
|
||||
|
||||
if (ia->ia_nio < 1) /* need base addr */
|
||||
return 0;
|
||||
|
||||
if (ISA_DIRECT_CONFIG(ia))
|
||||
return 0;
|
||||
|
||||
if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT)
|
||||
return 0;
|
||||
|
||||
if (bus_space_map(ia->ia_iot, ia->ia_io[0].ir_addr, 8, 0, &bsh))
|
||||
return 0;
|
||||
|
||||
valc = bus_space_read_1(ia->ia_iot, bsh, UG_CMD);
|
||||
vald = bus_space_read_1(ia->ia_iot, bsh, UG_DATA);
|
||||
|
||||
ug_ver = 0;
|
||||
|
||||
/* Check for uGuru 2003 */
|
||||
|
||||
if (((vald == 0) || (vald == 8)) && (valc == 0xAC))
|
||||
ug_ver = 1;
|
||||
|
||||
/* Check for uGuru 2005 */
|
||||
|
||||
wrap_sc.sc_iot = ia->ia_iot;
|
||||
wrap_sc.sc_ioh = bsh;
|
||||
|
||||
if (ug2_sync(&wrap_sc) == 1)
|
||||
ug_ver = 2;
|
||||
|
||||
/* unmap, prepare ia and bye */
|
||||
bus_space_unmap(ia->ia_iot, bsh, 8);
|
||||
|
||||
if (ug_ver != 0) {
|
||||
ia->ia_nio = 1;
|
||||
ia->ia_io[0].ir_size = 8;
|
||||
ia->ia_niomem = 0;
|
||||
ia->ia_nirq = 0;
|
||||
ia->ia_ndrq = 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
static void
|
||||
ug_isa_attach(struct device *parent, struct device *self, void *aux)
|
||||
{
|
||||
struct ug_softc *sc = (void *)self;
|
||||
struct isa_attach_args *ia = aux;
|
||||
int i;
|
||||
|
||||
if (bus_space_map(sc->sc_iot, ia->ia_io[0].ir_addr,
|
||||
8, 0, &sc->sc_ioh)) {
|
||||
aprint_error(": can't map i/o space\n");
|
||||
return;
|
||||
}
|
||||
|
||||
ia->ia_iot = sc->sc_iot;
|
||||
sc->version = ug_ver;
|
||||
|
||||
if (sc->version == 2) {
|
||||
ug2_attach(sc);
|
||||
return;
|
||||
}
|
||||
|
||||
aprint_normal(": Abit uGuru system monitor\n");
|
||||
|
||||
if (!ug_reset(sc))
|
||||
aprint_error("%s: reset failed.\n", sc->sc_dev.dv_xname);
|
||||
|
||||
ug_setup_sensors(sc);
|
||||
|
||||
for (i = 0; i < UG_NUM_SENSORS; i++) {
|
||||
sc->sc_data[i].sensor = sc->sc_info[i].sensor = i;
|
||||
sc->sc_data[i].validflags = (ENVSYS_FVALID|ENVSYS_FCURVALID);
|
||||
sc->sc_info[i].validflags = ENVSYS_FVALID;
|
||||
sc->sc_data[i].warnflags = ENVSYS_WARN_OK;
|
||||
}
|
||||
|
||||
sc->sc_sysmon.sme_ranges = ug_ranges;
|
||||
sc->sc_sysmon.sme_sensor_info = sc->sc_info;
|
||||
sc->sc_sysmon.sme_sensor_data = sc->sc_data;
|
||||
sc->sc_sysmon.sme_cookie = sc;
|
||||
sc->sc_sysmon.sme_gtredata = ug_gtredata;
|
||||
sc->sc_sysmon.sme_streinfo = ug_streinfo_ni;
|
||||
sc->sc_sysmon.sme_nsensors = UG_NUM_SENSORS;
|
||||
sc->sc_sysmon.sme_envsys_version = UG_DRV_VERSION;
|
||||
sc->sc_sysmon.sme_flags = 0;
|
||||
|
||||
if (sysmon_envsys_register(&sc->sc_sysmon))
|
||||
aprint_error("%s: unable to register with sysmon\n",
|
||||
sc->sc_dev.dv_xname);
|
||||
|
||||
}
|
||||
|
||||
int
|
||||
ug_reset(struct ug_softc *sc)
|
||||
|
|
@ -297,7 +430,7 @@ ug_setup_sensors(struct ug_softc *sc)
|
|||
COPYDESCR(sc->sc_info[18].desc, "AUX Fan 2");
|
||||
}
|
||||
|
||||
static int
|
||||
int
|
||||
ug_gtredata(struct sysmon_envsys *sme, envsys_tre_data_t *tred)
|
||||
{
|
||||
struct ug_softc *sc = sme->sme_cookie;
|
||||
|
|
@ -346,7 +479,7 @@ ug_gtredata(struct sysmon_envsys *sme, envsys_tre_data_t *tred)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
int
|
||||
ug_streinfo_ni(struct sysmon_envsys *sme, envsys_basic_info_t *binfo)
|
||||
{
|
||||
/* not implemented */
|
||||
|
|
@ -448,7 +581,7 @@ ug2_attach(struct ug_softc *sc)
|
|||
sc->sc_dev.dv_xname);
|
||||
}
|
||||
|
||||
static int
|
||||
int
|
||||
ug2_gtredata(struct sysmon_envsys *sme, envsys_tre_data_t *tred)
|
||||
{
|
||||
struct ug_softc *sc = sme->sme_cookie;
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
/* $NetBSD: ugreg.h,v 1.1 2007/05/08 16:48:38 xtraeme Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007 Mihai Chelaru <kefren@netbsd.ro>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _UGREG_H_
|
||||
#define _UGREG_H_
|
||||
|
||||
#define UG_DRV_VERSION 1000
|
||||
|
||||
/*
|
||||
* Abit uGuru (first version)
|
||||
*/
|
||||
|
||||
#define UG_DELAY_CYCLES 5000
|
||||
#define UG_NUM_SENSORS 19
|
||||
#define UG_MAX_SENSORS 32
|
||||
|
||||
/* Data and Cmd offsets - Base is ussualy 0xE0 */
|
||||
#define UG_CMD 0
|
||||
#define UG_DATA 4
|
||||
|
||||
/* Temp and Voltage Sensors */
|
||||
#define UG_CPUTEMP 0x2100
|
||||
#define UG_SYSTEMP 0x2101
|
||||
#define UG_HTV 0x2102
|
||||
#define UG_VCORE 0x2103
|
||||
#define UG_DDRVDD 0x2104
|
||||
#define UG_3V3 0x2105
|
||||
#define UG_5V 0x2106
|
||||
#define UG_NBVDD 0x2108
|
||||
#define UG_AGP 0x2109
|
||||
#define UG_DDRVTT 0x210A
|
||||
#define UG_5VSB 0x210B
|
||||
#define UG_3VDUAL 0x210D
|
||||
#define UG_SBVDD 0x210E
|
||||
#define UG_PWMTEMP 0x210F
|
||||
|
||||
/* Fans */
|
||||
#define UG_CPUFAN 0x2600
|
||||
#define UG_NBFAN 0x2601
|
||||
#define UG_SYSFAN 0x2602
|
||||
#define UG_AUXFAN1 0x2603
|
||||
#define UG_AUXFAN2 0x2604
|
||||
|
||||
/* RFacts */
|
||||
#define UG_RFACT 1000
|
||||
#define UG_RFACT3 3490 * UG_RFACT / 255
|
||||
#define UG_RFACT4 4360 * UG_RFACT / 255
|
||||
#define UG_RFACT6 6250 * UG_RFACT / 255
|
||||
#define UG_RFACT_FAN 15300/255
|
||||
|
||||
/* Voltage and Fan sensors offsets */
|
||||
#define UG_VOLT_MIN 3
|
||||
#define UG_FAN_MIN 14
|
||||
|
||||
/*
|
||||
* Abit uGuru2 or uGuru 2005 settings
|
||||
*/
|
||||
|
||||
/* Sensor banks */
|
||||
#define UG2_SETTINGS_BANK 0x01
|
||||
#define UG2_SENSORS_BANK 0x08
|
||||
#define UG2_MISC_BANK 0x09
|
||||
|
||||
/* Sensor offsets */
|
||||
#define UG2_ALARMS_OFFSET 0x1E
|
||||
#define UG2_SETTINGS_OFFSET 0x24
|
||||
#define UG2_VALUES_OFFSET 0x80
|
||||
|
||||
/* Misc Sensor */
|
||||
#define UG2_BOARD_ID 0x0A
|
||||
|
||||
/* sensor types */
|
||||
#define UG2_VOLTAGE_SENSOR 0
|
||||
#define UG2_TEMP_SENSOR 1
|
||||
#define UG2_FAN_SENSOR 2
|
||||
|
||||
/* uGuru status flags */
|
||||
#define UG2_STATUS_READY_FOR_READ 0x01
|
||||
#define UG2_STATUS_BUSY 0x02
|
||||
/* No more than 32 sensors */
|
||||
#define UG2_MAX_NO_SENSORS 32
|
||||
|
||||
/* Unknown board should be the last. Now is 0x0016 */
|
||||
#define UG_MAX_MSB_BOARD 0x00
|
||||
#define UG_MAX_LSB_BOARD 0x16
|
||||
#define UG_MIN_LSB_BOARD 0x0c
|
||||
|
||||
#endif /* _UGREG_H_ */
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/* $NetBSD: ugvar.h,v 1.1 2007/05/08 16:48:38 xtraeme Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007 Mihai Chelaru <kefren@netbsd.ro>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _UGVAR_H_
|
||||
#define _UGVAR_H_
|
||||
|
||||
/*
|
||||
* sc->sensors sub-intervals for each unit type.
|
||||
*/
|
||||
static const struct envsys_range ug_ranges[] = {
|
||||
{ 0, 2, ENVSYS_STEMP },
|
||||
{ 14, 18, ENVSYS_SFANRPM },
|
||||
{ 1, 0, ENVSYS_SVOLTS_AC }, /* None */
|
||||
{ 3, 13, ENVSYS_SVOLTS_DC },
|
||||
{ 1, 0, ENVSYS_SOHMS }, /* None */
|
||||
{ 1, 0, ENVSYS_SWATTS }, /* None */
|
||||
{ 1, 0, ENVSYS_SAMPS } /* None */
|
||||
};
|
||||
|
||||
struct ug_softc {
|
||||
struct device sc_dev;
|
||||
|
||||
bus_space_tag_t sc_iot;
|
||||
bus_space_handle_t sc_ioh;
|
||||
|
||||
struct sysmon_envsys sc_sysmon;
|
||||
envsys_tre_data_t sc_data[UG_MAX_SENSORS];
|
||||
envsys_basic_info_t sc_info[UG_MAX_SENSORS];
|
||||
uint8_t version;
|
||||
void *mbsens;
|
||||
};
|
||||
|
||||
struct ug2_sensor_info {
|
||||
const char *name;
|
||||
int port;
|
||||
int type;
|
||||
int multiplier;
|
||||
int divisor;
|
||||
int offset;
|
||||
};
|
||||
|
||||
struct ug2_motherboard_info {
|
||||
uint16_t id;
|
||||
const char *name;
|
||||
struct ug2_sensor_info sensors[UG2_MAX_NO_SENSORS + 1];
|
||||
};
|
||||
|
||||
/* driver internal functions */
|
||||
int ug_reset(struct ug_softc *);
|
||||
uint8_t ug_read(struct ug_softc *, unsigned short);
|
||||
int ug_waitfor(struct ug_softc *, uint16_t, uint8_t);
|
||||
void ug_setup_sensors(struct ug_softc *);
|
||||
void ug2_attach(struct ug_softc *);
|
||||
int ug2_wait_ready(struct ug_softc *);
|
||||
int ug2_wait_readable(struct ug_softc *);
|
||||
int ug2_sync(struct ug_softc *);
|
||||
int ug2_read(struct ug_softc *, uint8_t, uint8_t, uint8_t, uint8_t*);
|
||||
|
||||
/* Envsys */
|
||||
int ug_gtredata(struct sysmon_envsys *, envsys_tre_data_t *);
|
||||
int ug_streinfo_ni(struct sysmon_envsys *, envsys_basic_info_t *);
|
||||
int ug2_gtredata(struct sysmon_envsys *, envsys_tre_data_t *);
|
||||
|
||||
#endif /* _UGVAR_H_ */
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
# $NetBSD: files.isa,v 1.148 2007/01/09 21:59:08 cube Exp $
|
||||
# $NetBSD: files.isa,v 1.149 2007/05/08 16:48:38 xtraeme Exp $
|
||||
#
|
||||
# Config file and device description for machine-independent ISA code.
|
||||
# Included by ports that need it. Requires that the SCSI files be
|
||||
|
|
@ -461,9 +461,8 @@ attach it at isa with it_isa
|
|||
file dev/isa/it.c it_isa
|
||||
|
||||
# Abit uGuru hardware monitor
|
||||
device ug: sysmon_envsys
|
||||
attach ug at isa with ug_isa
|
||||
file dev/isa/ug.c ug_isa
|
||||
attach ug at isa with ug_isa
|
||||
file dev/isa/ug_isa.c ug_isa
|
||||
|
||||
# ISDN devices
|
||||
attach isic at isa with isic_isa
|
||||
|
|
|
|||
|
|
@ -0,0 +1,171 @@
|
|||
/* $NetBSD: ug_isa.c,v 1.1 2007/05/08 16:48:38 xtraeme Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007 Mihai Chelaru <kefren@netbsd.ro>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Driver for Abit uGuru (interface is inspired from it.c and nslm7x.c)
|
||||
* Inspired by olle sandberg linux driver as Abit didn't care to release docs
|
||||
* Support for uGuru 2005 from Louis Kruger and Hans de Goede linux driver
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: ug_isa.c,v 1.1 2007/05/08 16:48:38 xtraeme Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/proc.h>
|
||||
#include <sys/device.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/errno.h>
|
||||
#include <sys/conf.h>
|
||||
#include <sys/envsys.h>
|
||||
#include <sys/time.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <machine/intr.h>
|
||||
|
||||
#include <dev/isa/isareg.h>
|
||||
#include <dev/isa/isavar.h>
|
||||
|
||||
#include <dev/sysmon/sysmonvar.h>
|
||||
|
||||
#include <dev/ic/ugreg.h>
|
||||
#include <dev/ic/ugvar.h>
|
||||
|
||||
/* autoconf(9) functions */
|
||||
static int ug_isa_match(struct device *, struct cfdata *, void *);
|
||||
static void ug_isa_attach(struct device *, struct device *, void *);
|
||||
|
||||
CFATTACH_DECL(ug_isa, sizeof(struct ug_softc),
|
||||
ug_isa_match, ug_isa_attach, NULL, NULL);
|
||||
|
||||
extern uint8_t ug_ver;
|
||||
|
||||
static int
|
||||
ug_isa_match(struct device *parent, struct cfdata *match, void *aux)
|
||||
{
|
||||
struct isa_attach_args *ia = aux;
|
||||
struct ug_softc wrap_sc;
|
||||
bus_space_handle_t bsh;
|
||||
uint8_t valc, vald;
|
||||
|
||||
if (ia->ia_nio < 1) /* need base addr */
|
||||
return 0;
|
||||
|
||||
if (ISA_DIRECT_CONFIG(ia))
|
||||
return 0;
|
||||
|
||||
if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT)
|
||||
return 0;
|
||||
|
||||
if (bus_space_map(ia->ia_iot, ia->ia_io[0].ir_addr, 8, 0, &bsh))
|
||||
return 0;
|
||||
|
||||
valc = bus_space_read_1(ia->ia_iot, bsh, UG_CMD);
|
||||
vald = bus_space_read_1(ia->ia_iot, bsh, UG_DATA);
|
||||
|
||||
ug_ver = 0;
|
||||
|
||||
/* Check for uGuru 2003 */
|
||||
|
||||
if (((vald == 0) || (vald == 8)) && (valc == 0xAC))
|
||||
ug_ver = 1;
|
||||
|
||||
/* Check for uGuru 2005 */
|
||||
|
||||
wrap_sc.sc_iot = ia->ia_iot;
|
||||
wrap_sc.sc_ioh = bsh;
|
||||
|
||||
if (ug2_sync(&wrap_sc) == 1)
|
||||
ug_ver = 2;
|
||||
|
||||
/* unmap, prepare ia and bye */
|
||||
bus_space_unmap(ia->ia_iot, bsh, 8);
|
||||
|
||||
if (ug_ver != 0) {
|
||||
ia->ia_nio = 1;
|
||||
ia->ia_io[0].ir_size = 8;
|
||||
ia->ia_niomem = 0;
|
||||
ia->ia_nirq = 0;
|
||||
ia->ia_ndrq = 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
static void
|
||||
ug_isa_attach(struct device *parent, struct device *self, void *aux)
|
||||
{
|
||||
struct ug_softc *sc = (void *)self;
|
||||
struct isa_attach_args *ia = aux;
|
||||
int i;
|
||||
|
||||
if (bus_space_map(sc->sc_iot, ia->ia_io[0].ir_addr,
|
||||
8, 0, &sc->sc_ioh)) {
|
||||
aprint_error(": can't map i/o space\n");
|
||||
return;
|
||||
}
|
||||
|
||||
ia->ia_iot = sc->sc_iot;
|
||||
sc->version = ug_ver;
|
||||
|
||||
if (sc->version == 2) {
|
||||
ug2_attach(sc);
|
||||
return;
|
||||
}
|
||||
|
||||
aprint_normal(": Abit uGuru system monitor\n");
|
||||
|
||||
if (!ug_reset(sc))
|
||||
aprint_error("%s: reset failed.\n", sc->sc_dev.dv_xname);
|
||||
|
||||
ug_setup_sensors(sc);
|
||||
|
||||
for (i = 0; i < UG_NUM_SENSORS; i++) {
|
||||
sc->sc_data[i].sensor = sc->sc_info[i].sensor = i;
|
||||
sc->sc_data[i].validflags = (ENVSYS_FVALID|ENVSYS_FCURVALID);
|
||||
sc->sc_info[i].validflags = ENVSYS_FVALID;
|
||||
sc->sc_data[i].warnflags = ENVSYS_WARN_OK;
|
||||
}
|
||||
|
||||
sc->sc_sysmon.sme_ranges = ug_ranges;
|
||||
sc->sc_sysmon.sme_sensor_info = sc->sc_info;
|
||||
sc->sc_sysmon.sme_sensor_data = sc->sc_data;
|
||||
sc->sc_sysmon.sme_cookie = sc;
|
||||
sc->sc_sysmon.sme_gtredata = ug_gtredata;
|
||||
sc->sc_sysmon.sme_streinfo = ug_streinfo_ni;
|
||||
sc->sc_sysmon.sme_nsensors = UG_NUM_SENSORS;
|
||||
sc->sc_sysmon.sme_envsys_version = UG_DRV_VERSION;
|
||||
sc->sc_sysmon.sme_flags = 0;
|
||||
|
||||
if (sysmon_envsys_register(&sc->sc_sysmon))
|
||||
aprint_error("%s: unable to register with sysmon\n",
|
||||
sc->sc_dev.dv_xname);
|
||||
|
||||
}
|
||||
|
|
@ -1,420 +0,0 @@
|
|||
/* $NetBSD: ugvar.h,v 1.4 2007/05/07 07:48:28 xtraeme Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007 Mihai Chelaru <kefren@netbsd.ro>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _DEV_ISA_UGVAR_H
|
||||
#define _DEV_ISA_UGVAR_H
|
||||
|
||||
#define UG_DRV_VERSION 1000
|
||||
|
||||
/*
|
||||
* Abit uGuru (first version)
|
||||
*/
|
||||
|
||||
#define UG_DELAY_CYCLES 5000
|
||||
#define UG_NUM_SENSORS 19
|
||||
#define UG_MAX_SENSORS 32
|
||||
|
||||
/* Data and Cmd offsets - Base is ussualy 0xE0 */
|
||||
#define UG_CMD 0
|
||||
#define UG_DATA 4
|
||||
|
||||
/* Temp and Voltage Sensors */
|
||||
#define UG_CPUTEMP 0x2100
|
||||
#define UG_SYSTEMP 0x2101
|
||||
#define UG_HTV 0x2102
|
||||
#define UG_VCORE 0x2103
|
||||
#define UG_DDRVDD 0x2104
|
||||
#define UG_3V3 0x2105
|
||||
#define UG_5V 0x2106
|
||||
#define UG_NBVDD 0x2108
|
||||
#define UG_AGP 0x2109
|
||||
#define UG_DDRVTT 0x210A
|
||||
#define UG_5VSB 0x210B
|
||||
#define UG_3VDUAL 0x210D
|
||||
#define UG_SBVDD 0x210E
|
||||
#define UG_PWMTEMP 0x210F
|
||||
|
||||
/* Fans */
|
||||
#define UG_CPUFAN 0x2600
|
||||
#define UG_NBFAN 0x2601
|
||||
#define UG_SYSFAN 0x2602
|
||||
#define UG_AUXFAN1 0x2603
|
||||
#define UG_AUXFAN2 0x2604
|
||||
|
||||
/* RFacts */
|
||||
#define UG_RFACT 1000
|
||||
#define UG_RFACT3 3490 * UG_RFACT / 255
|
||||
#define UG_RFACT4 4360 * UG_RFACT / 255
|
||||
#define UG_RFACT6 6250 * UG_RFACT / 255
|
||||
#define UG_RFACT_FAN 15300/255
|
||||
|
||||
/* Voltage and Fan sensors offsets */
|
||||
#define UG_VOLT_MIN 3
|
||||
#define UG_FAN_MIN 14
|
||||
|
||||
/*
|
||||
* sc->sensors sub-intervals for each unit type.
|
||||
*/
|
||||
static const struct envsys_range ug_ranges[] = {
|
||||
{ 0, 2, ENVSYS_STEMP },
|
||||
{ 14, 18, ENVSYS_SFANRPM },
|
||||
{ 1, 0, ENVSYS_SVOLTS_AC }, /* None */
|
||||
{ 3, 13, ENVSYS_SVOLTS_DC },
|
||||
{ 1, 0, ENVSYS_SOHMS }, /* None */
|
||||
{ 1, 0, ENVSYS_SWATTS }, /* None */
|
||||
{ 1, 0, ENVSYS_SAMPS } /* None */
|
||||
};
|
||||
|
||||
struct ug_softc {
|
||||
struct device sc_dev;
|
||||
|
||||
bus_space_tag_t sc_iot;
|
||||
bus_space_handle_t sc_ioh;
|
||||
|
||||
struct sysmon_envsys sc_sysmon;
|
||||
envsys_tre_data_t sc_data[UG_MAX_SENSORS];
|
||||
envsys_basic_info_t sc_info[UG_MAX_SENSORS];
|
||||
uint8_t version;
|
||||
void *mbsens;
|
||||
};
|
||||
|
||||
/*
|
||||
* Abit uGuru2 or uGuru 2005 settings
|
||||
*/
|
||||
|
||||
/* Sensor banks */
|
||||
#define UG2_SETTINGS_BANK 0x01
|
||||
#define UG2_SENSORS_BANK 0x08
|
||||
#define UG2_MISC_BANK 0x09
|
||||
|
||||
/* Sensor offsets */
|
||||
#define UG2_ALARMS_OFFSET 0x1E
|
||||
#define UG2_SETTINGS_OFFSET 0x24
|
||||
#define UG2_VALUES_OFFSET 0x80
|
||||
|
||||
/* Misc Sensor */
|
||||
#define UG2_BOARD_ID 0x0A
|
||||
|
||||
/* sensor types */
|
||||
#define UG2_VOLTAGE_SENSOR 0
|
||||
#define UG2_TEMP_SENSOR 1
|
||||
#define UG2_FAN_SENSOR 2
|
||||
|
||||
/* uGuru status flags */
|
||||
#define UG2_STATUS_READY_FOR_READ 0x01
|
||||
#define UG2_STATUS_BUSY 0x02
|
||||
/* No more than 32 sensors */
|
||||
#define UG2_MAX_NO_SENSORS 32
|
||||
|
||||
struct ug2_sensor_info {
|
||||
const char *name;
|
||||
int port;
|
||||
int type;
|
||||
int multiplier;
|
||||
int divisor;
|
||||
int offset;
|
||||
};
|
||||
|
||||
struct ug2_motherboard_info {
|
||||
uint16_t id;
|
||||
const char *name;
|
||||
struct ug2_sensor_info sensors[UG2_MAX_NO_SENSORS + 1];
|
||||
};
|
||||
|
||||
|
||||
/* Unknown board should be the last. Now is 0x0016 */
|
||||
#define UG_MAX_MSB_BOARD 0x00
|
||||
#define UG_MAX_LSB_BOARD 0x16
|
||||
#define UG_MIN_LSB_BOARD 0x0c
|
||||
|
||||
/*
|
||||
* Imported from linux driver
|
||||
*/
|
||||
|
||||
struct ug2_motherboard_info ug2_mb[] = {
|
||||
{ 0x000C, "unknown. Please send-pr(1)", {
|
||||
{ "CPU Core", 0, 0, 10, 1, 0 },
|
||||
{ "DDR", 1, 0, 10, 1, 0 },
|
||||
{ "DDR VTT", 2, 0, 10, 1, 0 },
|
||||
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
|
||||
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
|
||||
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
|
||||
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
|
||||
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
||||
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
||||
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
||||
{ "+3.3V", 10, 0, 20, 1, 0 },
|
||||
{ "5VSB", 11, 0, 30, 1, 0 },
|
||||
{ "CPU", 24, 1, 1, 1, 0 },
|
||||
{ "System", 25, 1, 1, 1, 0 },
|
||||
{ "PWM", 26, 1, 1, 1, 0 },
|
||||
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
||||
{ "NB Fan", 33, 2, 60, 1, 0 },
|
||||
{ "SYS FAN", 34, 2, 60, 1, 0 },
|
||||
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
|
||||
{ NULL, 0, 0, 0, 0, 0 } }
|
||||
},
|
||||
{ 0x000D, "Abit AW8", {
|
||||
{ "CPU Core", 0, 0, 10, 1, 0 },
|
||||
{ "DDR", 1, 0, 10, 1, 0 },
|
||||
{ "DDR VTT", 2, 0, 10, 1, 0 },
|
||||
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
|
||||
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
|
||||
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
|
||||
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
|
||||
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
||||
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
||||
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
||||
{ "+3.3V", 10, 0, 20, 1, 0 },
|
||||
{ "5VSB", 11, 0, 30, 1, 0 },
|
||||
{ "CPU", 24, 1, 1, 1, 0 },
|
||||
{ "System", 25, 1, 1, 1, 0 },
|
||||
{ "PWM1", 26, 1, 1, 1, 0 },
|
||||
{ "PWM2", 27, 1, 1, 1, 0 },
|
||||
{ "PWM3", 28, 1, 1, 1, 0 },
|
||||
{ "PWM4", 29, 1, 1, 1, 0 },
|
||||
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
||||
{ "NB Fan", 33, 2, 60, 1, 0 },
|
||||
{ "SYS Fan", 34, 2, 60, 1, 0 },
|
||||
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
|
||||
{ "AUX2 Fan", 36, 2, 60, 1, 0 },
|
||||
{ "AUX3 Fan", 37, 2, 60, 1, 0 },
|
||||
{ "AUX4 Fan", 38, 2, 60, 1, 0 },
|
||||
{ "AUX5 Fan", 39, 2, 60, 1, 0 },
|
||||
{ NULL, 0, 0, 0, 0, 0 } }
|
||||
},
|
||||
{ 0x000E, "Abit AL8", {
|
||||
{ "CPU Core", 0, 0, 10, 1, 0 },
|
||||
{ "DDR", 1, 0, 10, 1, 0 },
|
||||
{ "DDR VTT", 2, 0, 10, 1, 0 },
|
||||
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
|
||||
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
|
||||
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
|
||||
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
|
||||
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
||||
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
||||
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
||||
{ "+3.3V", 10, 0, 20, 1, 0 },
|
||||
{ "5VSB", 11, 0, 30, 1, 0 },
|
||||
{ "CPU", 24, 1, 1, 1, 0 },
|
||||
{ "System", 25, 1, 1, 1, 0 },
|
||||
{ "PWM", 26, 1, 1, 1, 0 },
|
||||
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
||||
{ "NB Fan", 33, 2, 60, 1, 0 },
|
||||
{ "SYS Fan", 34, 2, 60, 1, 0 },
|
||||
{ NULL, 0, 0, 0, 0, 0 } }
|
||||
},
|
||||
{ 0x000F, "unknown. Please send-pr(1)", {
|
||||
{ "CPU Core", 0, 0, 10, 1, 0 },
|
||||
{ "DDR", 1, 0, 10, 1, 0 },
|
||||
{ "DDR VTT", 2, 0, 10, 1, 0 },
|
||||
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
|
||||
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
|
||||
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
|
||||
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
|
||||
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
||||
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
||||
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
||||
{ "+3.3V", 10, 0, 20, 1, 0 },
|
||||
{ "5VSB", 11, 0, 30, 1, 0 },
|
||||
{ "CPU", 24, 1, 1, 1, 0 },
|
||||
{ "System", 25, 1, 1, 1, 0 },
|
||||
{ "PWM", 26, 1, 1, 1, 0 },
|
||||
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
||||
{ "NB Fan", 33, 2, 60, 1, 0 },
|
||||
{ "SYS Fan", 34, 2, 60, 1, 0 },
|
||||
{ NULL, 0, 0, 0, 0, 0 } }
|
||||
},
|
||||
{ 0x0010, "Abit NI8 SLI GR", {
|
||||
{ "CPU Core", 0, 0, 10, 1, 0 },
|
||||
{ "DDR", 1, 0, 10, 1, 0 },
|
||||
{ "DDR VTT", 2, 0, 10, 1, 0 },
|
||||
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
|
||||
{ "NB 1.4V", 4, 0, 10, 1, 0 },
|
||||
{ "SB 1.5V", 6, 0, 10, 1, 0 },
|
||||
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
||||
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
||||
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
||||
{ "+3.3V", 10, 0, 20, 1, 0 },
|
||||
{ "5VSB", 11, 0, 30, 1, 0 },
|
||||
{ "CPU", 24, 1, 1, 1, 0 },
|
||||
{ "SYS", 25, 1, 1, 1, 0 },
|
||||
{ "PWM", 26, 1, 1, 1, 0 },
|
||||
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
||||
{ "NB Fan", 33, 2, 60, 1, 0 },
|
||||
{ "SYS Fan", 34, 2, 60, 1, 0 },
|
||||
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
|
||||
{ "OTES1 Fan", 36, 2, 60, 1, 0 },
|
||||
{ NULL, 0, 0, 0, 0, 0 } }
|
||||
},
|
||||
{ 0x0011, "Abit AT8 32X", {
|
||||
{ "CPU Core", 0, 0, 10, 1, 0 },
|
||||
{ "DDR", 1, 0, 20, 1, 0 },
|
||||
{ "DDR VTT", 2, 0, 10, 1, 0 },
|
||||
{ "CPU VDDA 2.5V", 6, 0, 20, 1, 0 },
|
||||
{ "NB 1.8V", 4, 0, 10, 1, 0 },
|
||||
{ "NB 1.8V Dual", 5, 0, 10, 1, 0 },
|
||||
{ "HTV 1.2", 3, 0, 10, 1, 0 },
|
||||
{ "PCIE 1.2V", 12, 0, 10, 1, 0 },
|
||||
{ "NB 1.2V", 13, 0, 10, 1, 0 },
|
||||
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
||||
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
||||
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
||||
{ "+3.3V", 10, 0, 20, 1, 0 },
|
||||
{ "5VSB", 11, 0, 30, 1, 0 },
|
||||
{ "CPU", 24, 1, 1, 1, 0 },
|
||||
{ "NB", 25, 1, 1, 1, 0 },
|
||||
{ "System", 26, 1, 1, 1, 0 },
|
||||
{ "PWM", 27, 1, 1, 1, 0 },
|
||||
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
||||
{ "NB Fan", 33, 2, 60, 1, 0 },
|
||||
{ "SYS Fan", 34, 2, 60, 1, 0 },
|
||||
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
|
||||
{ "AUX2 Fan", 36, 2, 60, 1, 0 },
|
||||
{ NULL, 0, 0, 0, 0, 0 } }
|
||||
},
|
||||
{ 0x0012, "unknown. Please send-pr(1)", {
|
||||
{ "CPU Core", 0, 0, 10, 1, 0 },
|
||||
{ "DDR", 1, 0, 20, 1, 0 },
|
||||
{ "DDR VTT", 2, 0, 10, 1, 0 },
|
||||
{ "HyperTransport", 3, 0, 10, 1, 0 },
|
||||
{ "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
|
||||
{ "NB", 4, 0, 10, 1, 0 },
|
||||
{ "SB", 6, 0, 10, 1, 0 },
|
||||
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
||||
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
||||
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
||||
{ "+3.3V", 10, 0, 20, 1, 0 },
|
||||
{ "5VSB", 11, 0, 30, 1, 0 },
|
||||
{ "CPU", 24, 1, 1, 1, 0 },
|
||||
{ "SYS", 25, 1, 1, 1, 0 },
|
||||
{ "PWM", 26, 1, 1, 1, 0 },
|
||||
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
||||
{ "NB Fan", 33, 2, 60, 1, 0 },
|
||||
{ "SYS Fan", 34, 2, 60, 1, 0 },
|
||||
{ "AUX1 Fan", 36, 2, 60, 1, 0 },
|
||||
{ NULL, 0, 0, 0, 0, 0 } }
|
||||
},
|
||||
{ 0x0013, "unknown. Please send-pr(1)", {
|
||||
{ "CPU Core", 0, 0, 10, 1, 0 },
|
||||
{ "DDR", 1, 0, 10, 1, 0 },
|
||||
{ "DDR VTT", 2, 0, 10, 1, 0 },
|
||||
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
|
||||
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
|
||||
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
|
||||
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
|
||||
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
||||
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
||||
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
||||
{ "+3.3V", 10, 0, 20, 1, 0 },
|
||||
{ "5VSB", 11, 0, 30, 1, 0 },
|
||||
{ "CPU", 24, 1, 1, 1, 0 },
|
||||
{ "System", 25, 1, 1, 1, 0 },
|
||||
{ "PWM1", 26, 1, 1, 1, 0 },
|
||||
{ "PWM2", 27, 1, 1, 1, 0 },
|
||||
{ "PWM3", 28, 1, 1, 1, 0 },
|
||||
{ "PWM4", 29, 1, 1, 1, 0 },
|
||||
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
||||
{ "NB Fan", 33, 2, 60, 1, 0 },
|
||||
{ "SYS Fan", 34, 2, 60, 1, 0 },
|
||||
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
|
||||
{ "AUX2 Fan", 36, 2, 60, 1, 0 },
|
||||
{ "AUX3 Fan", 37, 2, 60, 1, 0 },
|
||||
{ "AUX4 Fan", 38, 2, 60, 1, 0 },
|
||||
{ NULL, 0, 0, 0, 0, 0 } }
|
||||
},
|
||||
{ 0x0014, "Abit AB9 Pro", {
|
||||
{ "CPU Core", 0, 0, 10, 1, 0 },
|
||||
{ "DDR", 1, 0, 10, 1, 0 },
|
||||
{ "DDR VTT", 2, 0, 10, 1, 0 },
|
||||
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
|
||||
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
|
||||
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
|
||||
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
|
||||
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
||||
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
||||
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
||||
{ "+3.3V", 10, 0, 20, 1, 0 },
|
||||
{ "5VSB", 11, 0, 30, 1, 0 },
|
||||
{ "CPU", 24, 1, 1, 1, 0 },
|
||||
{ "System", 25, 1, 1, 1, 0 },
|
||||
{ "PWM", 26, 1, 1, 1, 0 },
|
||||
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
||||
{ "NB Fan", 33, 2, 60, 1, 0 },
|
||||
{ "SYS Fan", 34, 2, 60, 1, 0 },
|
||||
{ NULL, 0, 0, 0, 0, 0 } }
|
||||
},
|
||||
{ 0x0015, "unknown. Please send-pr(1)", {
|
||||
{ "CPU Core", 0, 0, 10, 1, 0 },
|
||||
{ "DDR", 1, 0, 20, 1, 0 },
|
||||
{ "DDR VTT", 2, 0, 10, 1, 0 },
|
||||
{ "HyperTransport", 3, 0, 10, 1, 0 },
|
||||
{ "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
|
||||
{ "NB", 4, 0, 10, 1, 0 },
|
||||
{ "SB", 6, 0, 10, 1, 0 },
|
||||
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
||||
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
||||
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
||||
{ "+3.3V", 10, 0, 20, 1, 0 },
|
||||
{ "5VSB", 11, 0, 30, 1, 0 },
|
||||
{ "CPU", 24, 1, 1, 1, 0 },
|
||||
{ "SYS", 25, 1, 1, 1, 0 },
|
||||
{ "PWM", 26, 1, 1, 1, 0 },
|
||||
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
||||
{ "NB Fan", 33, 2, 60, 1, 0 },
|
||||
{ "SYS Fan", 34, 2, 60, 1, 0 },
|
||||
{ "AUX1 Fan", 33, 2, 60, 1, 0 },
|
||||
{ "AUX2 Fan", 35, 2, 60, 1, 0 },
|
||||
{ "AUX3 Fan", 36, 2, 60, 1, 0 },
|
||||
{ NULL, 0, 0, 0, 0, 0 } }
|
||||
},
|
||||
{ 0x0016, "generic", {
|
||||
{ "CPU Core", 0, 0, 10, 1, 0 },
|
||||
{ "DDR", 1, 0, 20, 1, 0 },
|
||||
{ "DDR VTT", 2, 0, 10, 1, 0 },
|
||||
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
|
||||
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
|
||||
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
|
||||
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
|
||||
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
||||
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
||||
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
||||
{ "+3.3V", 10, 0, 20, 1, 0 },
|
||||
{ "5VSB", 11, 0, 30, 1, 0 },
|
||||
{ "CPU", 24, 1, 1, 1, 0 },
|
||||
{ "System", 25, 1, 1, 1, 0 },
|
||||
{ "PWM", 26, 1, 1, 1, 0 },
|
||||
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
||||
{ "NB Fan", 33, 2, 60, 1, 0 },
|
||||
{ "SYS FAN", 34, 2, 60, 1, 0 },
|
||||
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
|
||||
{ NULL, 0, 0, 0, 0, 0 } }
|
||||
},
|
||||
{ 0x0000, NULL, { { NULL, 0, 0, 0, 0, 0 } } }
|
||||
};
|
||||
|
||||
#endif /* _DEV_ISA_UGVAR_H_ */
|
||||
Loading…
Reference in New Issue