merge in ultrasparc changes
This commit is contained in:
mrg
parent
58d0ed9dd2
commit
feddb7ad96
@ -1,4 +1,4 @@
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/* $NetBSD: fpu.c,v 1.6 1997/07/29 10:09:51 fair Exp $ */
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/* $NetBSD: fpu.c,v 1.7 2000/06/18 06:54:17 mrg Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -98,7 +98,11 @@ static u_char fpu_codes[] = {
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void
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fpu_cleanup(p, fs)
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register struct proc *p;
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#ifndef SUN4U
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register struct fpstate *fs;
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#else /* SUN4U */
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register struct fpstate64 *fs;
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#endif /* SUN4U */
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{
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register int i, fsr = fs->fs_fsr, error;
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union instr instr;
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@ -107,7 +111,7 @@ fpu_cleanup(p, fs)
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switch ((fsr >> FSR_FTT_SHIFT) & FSR_FTT_MASK) {
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case FSR_TT_NONE:
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panic("fpu_cleanup 1"); /* ??? */
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panic("fpu_cleanup: No fault"); /* ??? */
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break;
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case FSR_TT_IEEE:
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@ -118,9 +122,18 @@ fpu_cleanup(p, fs)
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break; /* XXX should return, but queue remains */
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case FSR_TT_UNFIN:
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#ifdef SUN4U
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if (fs->fs_qsize == 0) {
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printf("fpu_cleanup: unfinished fpop");
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/* The book sez reexecute or emulate. */
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return;
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}
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break;
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#endif /* SUN4U */
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case FSR_TT_UNIMP:
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if (fs->fs_qsize == 0)
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panic("fpu_cleanup 2");
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panic("fpu_cleanup: unimplemented fpop");
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break;
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case FSR_TT_SEQ:
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@ -159,6 +172,12 @@ fpu_cleanup(p, fs)
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break;
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case NOTFPU:
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#ifdef SUN4U
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#ifdef DEBUG
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printf("fpu_cleanup: not an FPU error -- sending SIGILL\n", p);
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Debugger();
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#endif
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#endif /* SUN4U */
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trapsignal(p, SIGILL, 0); /* ??? code? */
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break;
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@ -183,7 +202,11 @@ out:
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fpu_emulate(p, tf, fs)
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struct proc *p;
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register struct trapframe *tf;
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#ifndef SUN4U
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register struct fpstate *fs;
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#else /* SUN4U */
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register struct fpstate64 *fs;
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#endif /* SUN4U */
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{
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do {
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@ -234,8 +257,13 @@ fpu_execute(fe, instr)
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union instr instr;
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{
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register struct fpn *fp;
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#ifndef SUN4U
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register int opf, rs1, rs2, rd, type, mask, fsr, cx;
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register struct fpstate *fs;
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#else /* SUN4U */
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register int opf, rs1, rs2, rd, type, mask, fsr, cx, i, cond;
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register struct fpstate64 *fs;
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#endif /* SUN4U */
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u_int space[4];
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/*
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@ -256,6 +284,119 @@ fpu_execute(fe, instr)
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fs = fe->fe_fpstate;
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fe->fe_fsr = fs->fs_fsr & ~FSR_CX;
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fe->fe_cx = 0;
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#ifdef SUN4U
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/*
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* Check to see if we're dealing with a fancy cmove and handle
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* it first.
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*/
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if (instr.i_op3.i_op3 == IOP3_FPop2 && (opf&0xff0) != (FCMP&0xff0)) {
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switch (opf >>= 2) {
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case FMVFC0 >> 2:
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cond = (fs->fs_fsr>>FSR_FCC_SHIFT)&FSR_FCC_MASK;
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if (instr.i_fmovcc.i_cond != cond) return(0); /* success */
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rs1 = fs->fs_regs[rs2];
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goto mov;
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case FMVFC1 >> 2:
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cond = (fs->fs_fsr>>FSR_FCC1_SHIFT)&FSR_FCC_MASK;
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if (instr.i_fmovcc.i_cond != cond) return(0); /* success */
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rs1 = fs->fs_regs[rs2];
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goto mov;
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case FMVFC2 >> 2:
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cond = (fs->fs_fsr>>FSR_FCC2_SHIFT)&FSR_FCC_MASK;
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if (instr.i_fmovcc.i_cond != cond) return(0); /* success */
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rs1 = fs->fs_regs[rs2];
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goto mov;
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case FMVFC3 >> 2:
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cond = (fs->fs_fsr>>FSR_FCC3_SHIFT)&FSR_FCC_MASK;
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if (instr.i_fmovcc.i_cond != cond) return(0); /* success */
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rs1 = fs->fs_regs[rs2];
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goto mov;
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case FMVIC >> 2:
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/* Presume we're curproc */
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cond = (curproc->p_md.md_tf->tf_tstate>>TSTATE_CCR_SHIFT)&PSR_ICC;
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if (instr.i_fmovcc.i_cond != cond) return(0); /* success */
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rs1 = fs->fs_regs[rs2];
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goto mov;
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case FMVXC >> 2:
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/* Presume we're curproc */
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cond = (curproc->p_md.md_tf->tf_tstate>>(TSTATE_CCR_SHIFT+XCC_SHIFT))&PSR_ICC;
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if (instr.i_fmovcc.i_cond != cond) return(0); /* success */
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rs1 = fs->fs_regs[rs2];
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goto mov;
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case FMVRZ >> 2:
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/* Presume we're curproc */
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rs1 = instr.i_fmovr.i_rs1;
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if (rs1 != 0 && (int64_t)curproc->p_md.md_tf->tf_global[rs1] != 0)
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return (0); /* success */
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rs1 = fs->fs_regs[rs2];
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goto mov;
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case FMVRLEZ >> 2:
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/* Presume we're curproc */
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rs1 = instr.i_fmovr.i_rs1;
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if (rs1 != 0 && (int64_t)curproc->p_md.md_tf->tf_global[rs1] > 0)
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return (0); /* success */
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rs1 = fs->fs_regs[rs2];
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goto mov;
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case FMVRLZ >> 2:
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/* Presume we're curproc */
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rs1 = instr.i_fmovr.i_rs1;
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if (rs1 == 0 || (int64_t)curproc->p_md.md_tf->tf_global[rs1] >= 0)
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return (0); /* success */
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rs1 = fs->fs_regs[rs2];
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goto mov;
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case FMVRNZ >> 2:
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/* Presume we're curproc */
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rs1 = instr.i_fmovr.i_rs1;
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if (rs1 == 0 || (int64_t)curproc->p_md.md_tf->tf_global[rs1] == 0)
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return (0); /* success */
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rs1 = fs->fs_regs[rs2];
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goto mov;
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case FMVRGZ >> 2:
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/* Presume we're curproc */
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rs1 = instr.i_fmovr.i_rs1;
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if (rs1 == 0 || (int64_t)curproc->p_md.md_tf->tf_global[rs1] <= 0)
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return (0); /* success */
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rs1 = fs->fs_regs[rs2];
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goto mov;
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case FMVRGEZ >> 2:
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/* Presume we're curproc */
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rs1 = instr.i_fmovr.i_rs1;
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if (rs1 != 0 && (int64_t)curproc->p_md.md_tf->tf_global[rs1] < 0)
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return (0); /* success */
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rs1 = fs->fs_regs[rs2];
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goto mov;
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case FCMP >> 2:
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fpu_explode(fe, &fe->fe_f1, type, rs1);
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fpu_explode(fe, &fe->fe_f2, type, rs2);
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fpu_compare(fe, 0);
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goto cmpdone;
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case FCMPE >> 2:
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fpu_explode(fe, &fe->fe_f1, type, rs1);
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fpu_explode(fe, &fe->fe_f2, type, rs2);
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fpu_compare(fe, 1);
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cmpdone:
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/*
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* The only possible exception here is NV; catch it
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* early and get out, as there is no result register.
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*/
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cx = fe->fe_cx;
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fsr = fe->fe_fsr | (cx << FSR_CX_SHIFT);
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if (cx != 0) {
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if (fsr & (FSR_NV << FSR_TEM_SHIFT)) {
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fs->fs_fsr = (fsr & ~FSR_FTT) |
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(FSR_TT_IEEE << FSR_FTT_SHIFT);
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return (FPE);
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}
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fsr |= FSR_NV << FSR_AX_SHIFT;
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}
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fs->fs_fsr = fsr;
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return (0);
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default:
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return (NOTFPU);
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}
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}
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#endif /* SUN4U */
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switch (opf >>= 2) {
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default:
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@ -272,7 +413,14 @@ fpu_execute(fe, instr)
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case FABS >> 2:
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rs1 = fs->fs_regs[rs2] & ~(1 << 31);
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mov:
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#ifndef SUN4U
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fs->fs_regs[rd] = rs1;
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#else /* SUN4U */
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i = 1<<type;
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fs->fs_regs[rd++] = rs1;
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while (--i)
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fs->fs_regs[rd++] = fs->fs_regs[++rs2];
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#endif /* SUN4U */
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fs->fs_fsr = fe->fe_fsr;
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return (0); /* success */
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@ -305,6 +453,7 @@ fpu_execute(fe, instr)
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fp = fpu_div(fe);
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break;
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#ifndef SUN4U
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case FCMP >> 2:
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fpu_explode(fe, &fe->fe_f1, type, rs1);
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fpu_explode(fe, &fe->fe_f2, type, rs2);
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@ -333,6 +482,7 @@ fpu_execute(fe, instr)
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fs->fs_fsr = fsr;
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return (0);
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#endif /* not SUN4U */
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case FSMULD >> 2:
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case FDMULX >> 2:
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if (type == FTYPE_EXT)
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@ -343,9 +493,27 @@ fpu_execute(fe, instr)
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fp = fpu_mul(fe);
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break;
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#ifdef SUN4U
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case FXTOS >> 2:
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case FXTOD >> 2:
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case FXTOQ >> 2:
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type = FTYPE_LNG;
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fpu_explode(fe, fp = &fe->fe_f1, type, rs2);
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type = opf & 3; /* sneaky; depends on instruction encoding */
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break;
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case FTOX >> 2:
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fpu_explode(fe, fp = &fe->fe_f1, type, rs2);
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type = FTYPE_LNG;
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#endif /* SUN4U */
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case FTOS >> 2:
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case FTOD >> 2:
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#ifndef SUN4U
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case FTOX >> 2:
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#else /* SUN4U */
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case FTOQ >> 2:
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#endif /* SUN4U */
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case FTOI >> 2:
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fpu_explode(fe, fp = &fe->fe_f1, type, rs2);
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type = opf & 3; /* sneaky; depends on instruction encoding */
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@ -374,7 +542,11 @@ fpu_execute(fe, instr)
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}
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fs->fs_fsr = fsr;
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fs->fs_regs[rd] = space[0];
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#ifndef SUN4U
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if (type >= FTYPE_DBL) {
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#else /* SUN4U */
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if (type >= FTYPE_DBL || type == FTYPE_LNG) {
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#endif /* SUN4U */
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fs->fs_regs[rd + 1] = space[1];
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if (type > FTYPE_DBL) {
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fs->fs_regs[rd + 2] = space[2];
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@ -1,4 +1,4 @@
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/* $NetBSD: fpu_emu.h,v 1.2 1994/11/20 20:52:39 deraadt Exp $ */
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/* $NetBSD: fpu_emu.h,v 1.3 2000/06/18 06:54:17 mrg Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -90,6 +90,7 @@ struct fpn {
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#define FP_NMANT 115 /* total bits in mantissa (incl g,r) */
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#define FP_NG 2 /* number of low-order guard bits */
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#define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */
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#define FP_LG2 ((FP_NMANT - 1) & 63) /* log2(1.0) for fp_mant[0] and fp_mant[1] */
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#define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */
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#define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */
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#define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */
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@ -138,7 +139,11 @@ struct fpn {
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* Emulator state.
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*/
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struct fpemu {
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#ifndef SUN4U
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struct fpstate *fe_fpstate; /* registers, etc */
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#else /* SUN4U */
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struct fpstate64 *fe_fpstate; /* registers, etc */
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#endif /* SUN4U */
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int fe_fsr; /* fsr copy (modified during op) */
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int fe_cx; /* exceptions */
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struct fpn fe_f1; /* operand 1 */
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@ -1,4 +1,4 @@
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/* $NetBSD: fpu_explode.c,v 1.3 1996/03/14 19:41:54 christos Exp $ */
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/* $NetBSD: fpu_explode.c,v 1.4 2000/06/18 06:54:17 mrg Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -105,6 +105,33 @@ fpu_itof(fp, i)
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return (FPC_NUM);
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}
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#ifdef SUN4U
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/*
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* 64-bit int -> fpn.
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*/
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int
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fpu_xitof(fp, i)
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register struct fpn *fp;
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register u_int64_t i;
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{
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if (i == 0)
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return (FPC_ZERO);
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/*
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* The value FP_1 represents 2^FP_LG, so set the exponent
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* there and let normalization fix it up. Convert negative
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* numbers to sign-and-magnitude. Note that this relies on
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* fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
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*/
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fp->fp_exp = FP_LG2;
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*((int64_t*)fp->fp_mant) = (int64_t)i < 0 ? -i : i;
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fp->fp_mant[2] = 0;
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fp->fp_mant[3] = 0;
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fpu_norm(fp);
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return (FPC_NUM);
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}
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#endif /* SUN4U */
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#define mask(nbits) ((1 << (nbits)) - 1)
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/*
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@ -220,12 +247,22 @@ fpu_explode(fe, fp, type, reg)
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int type, reg;
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{
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register u_int s, *space;
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#ifdef SUN4U
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u_int64_t l, *xspace;
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xspace = (u_int64_t *)&fe->fe_fpstate->fs_regs[reg & ~1];
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l = xspace[0];
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#endif /* SUN4U */
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space = &fe->fe_fpstate->fs_regs[reg];
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s = space[0];
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fp->fp_sign = s >> 31;
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fp->fp_sticky = 0;
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switch (type) {
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#ifdef SUN4U
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case FTYPE_LNG:
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s = fpu_xitof(fp, l);
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break;
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#endif /* SUN4U */
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case FTYPE_INT:
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s = fpu_itof(fp, s);
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@ -1,4 +1,4 @@
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/* $NetBSD: fpu_extern.h,v 1.2 1998/09/05 15:28:08 christos Exp $ */
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/* $NetBSD: fpu_extern.h,v 1.3 2000/06/18 06:54:17 mrg Exp $ */
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/*-
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* Copyright (c) 1995 The NetBSD Foundation, Inc.
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@ -37,15 +37,25 @@
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*/
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struct proc;
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#ifndef SUN4U
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struct fpstate;
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struct trapframe;
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#else /* SUN4U */
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struct fpstate64;
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struct trapframe64;
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#endif /* SUN4U */
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union instr;
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struct fpemu;
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struct fpn;
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/* fpu.c */
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#ifndef SUN4U
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void fpu_cleanup __P((struct proc *, struct fpstate *));
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int fpu_emulate __P((struct proc *, struct trapframe *, struct fpstate *));
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#else /* SUN4U */
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void fpu_cleanup __P((struct proc *, struct fpstate64 *));
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int fpu_emulate __P((struct proc *, struct trapframe64 *, struct fpstate64 *));
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#endif /* SUN4U */
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int fpu_execute __P((struct fpemu *, union instr));
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/* fpu_add.c */
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@ -59,6 +69,9 @@ struct fpn *fpu_div __P((struct fpemu *));
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/* fpu_explode.c */
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int fpu_itof __P((struct fpn *, u_int));
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#ifdef SUN4U
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int fpu_xitof __P((struct fpn *, u_int64_t));
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#endif /* SUN4U */
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int fpu_stof __P((struct fpn *, u_int));
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int fpu_dtof __P((struct fpn *, u_int, u_int ));
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int fpu_xtof __P((struct fpn *, u_int, u_int , u_int , u_int ));
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@ -66,6 +79,9 @@ void fpu_explode __P((struct fpemu *, struct fpn *, int, int ));
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|
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/* fpu_implode.c */
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u_int fpu_ftoi __P((struct fpemu *, struct fpn *));
|
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#ifdef SUN4U
|
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u_int fpu_ftoxi __P((struct fpemu *, struct fpn *, u_int *));
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#endif /* SUN4U */
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u_int fpu_ftos __P((struct fpemu *, struct fpn *));
|
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u_int fpu_ftod __P((struct fpemu *, struct fpn *, u_int *));
|
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u_int fpu_ftox __P((struct fpemu *, struct fpn *, u_int *));
|
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|
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@ -1,4 +1,4 @@
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/* $NetBSD: fpu_implode.c,v 1.4 2000/04/12 04:06:41 chs Exp $ */
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/* $NetBSD: fpu_implode.c,v 1.5 2000/06/18 06:54:17 mrg Exp $ */
|
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|
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/*
|
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* Copyright (c) 1992, 1993
|
||||
@ -233,6 +233,59 @@ fpu_ftoi(fe, fp)
|
||||
return (0x7fffffff + sign);
|
||||
}
|
||||
|
||||
#ifdef SUN4U
|
||||
/*
|
||||
* fpn -> extended int (high bits of int value returned as return value).
|
||||
*
|
||||
* N.B.: this conversion always rounds towards zero (this is a peculiarity
|
||||
* of the SPARC instruction set).
|
||||
*/
|
||||
u_int
|
||||
fpu_ftoxi(fe, fp, res)
|
||||
struct fpemu *fe;
|
||||
register struct fpn *fp;
|
||||
u_int *res;
|
||||
{
|
||||
register u_int64_t i;
|
||||
register int sign, exp;
|
||||
|
||||
sign = fp->fp_sign;
|
||||
switch (fp->fp_class) {
|
||||
|
||||
case FPC_ZERO:
|
||||
res[1] = 0;
|
||||
return (0);
|
||||
|
||||
case FPC_NUM:
|
||||
/*
|
||||
* If exp >= 2^64, overflow. Otherwise shift value right
|
||||
* into last mantissa word (this will not exceed 0xffffffffffffffff),
|
||||
* shifting any guard and round bits out into the sticky
|
||||
* bit. Then ``round'' towards zero, i.e., just set an
|
||||
* inexact exception if sticky is set (see round()).
|
||||
* If the result is > 0x8000000000000000, or is positive and equals
|
||||
* 0x8000000000000000, overflow; otherwise the last fraction word
|
||||
* is the result.
|
||||
*/
|
||||
if ((exp = fp->fp_exp) >= 64)
|
||||
break;
|
||||
/* NB: the following includes exp < 0 cases */
|
||||
if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
|
||||
fe->fe_cx |= FSR_NX;
|
||||
i = (fp->fp_mant[2]<<32)|fp->fp_mant[3];
|
||||
if (i >= ((u_int64_t)0x8000000000000000LL + sign))
|
||||
break;
|
||||
return (sign ? -i : i);
|
||||
|
||||
default: /* Inf, qNaN, sNaN */
|
||||
break;
|
||||
}
|
||||
/* overflow: replace any inexact exception with invalid */
|
||||
fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV;
|
||||
return (0x7fffffffffffffffLL + sign);
|
||||
}
|
||||
#endif /* SUN4U */
|
||||
|
||||
/*
|
||||
* fpn -> single (32 bit single returned as return value).
|
||||
* We assume <= 29 bits in a single-precision fraction (1.f part).
|
||||
@ -452,6 +505,12 @@ fpu_implode(fe, fp, type, space)
|
||||
|
||||
switch (type) {
|
||||
|
||||
#ifdef SUN4U
|
||||
case FTYPE_LNG:
|
||||
space[0] = fpu_ftoxi(fe, fp, space);
|
||||
break;
|
||||
#endif /* SUN4U */
|
||||
|
||||
case FTYPE_INT:
|
||||
space[0] = fpu_ftoi(fe, fp);
|
||||
break;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user