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s/endianess/endianness/

This commit is contained in:
msaitoh 2021-11-10 17:19:29 +00:00
parent 79252e85b6
commit fead0fdcaf
19 changed files with 48 additions and 48 deletions
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4
sbin/dkscan_bsdlabel/dkscan_bsdlabel.8
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@ -1,4 +1,4 @@
.\" $NetBSD: dkscan_bsdlabel.8,v 1.2 2008/04/30 13:10:52 martin Exp $
.\" $NetBSD: dkscan_bsdlabel.8,v 1.3 2021/11/10 17:19:29 msaitoh Exp $
.\"
.\" Copyright (c) 2007 The NetBSD Foundation, Inc.
.\" All rights reserved.
@ -41,7 +41,7 @@
.Nm
scans a disk for a BSD disklabel, which does not need to be the
label variant used on the architecture currently running, or even
the same endianess.
the same endianness.
.Pp
The following options are supported:
.Bl -tag -width device -compact

6
sys/arch/mips/atheros/dev/ohci_arbus.c
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@ -1,4 +1,4 @@
/* $NetBSD: ohci_arbus.c,v 1.5 2021/08/07 16:18:59 thorpej Exp $ */
/* $NetBSD: ohci_arbus.c,v 1.6 2021/11/10 17:19:29 msaitoh Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000, 2002, 2003 The NetBSD Foundation, Inc.
@ -32,7 +32,7 @@
#include "locators.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ohci_arbus.c,v 1.5 2021/08/07 16:18:59 thorpej Exp $");
__KERNEL_RCSID(0, "$NetBSD: ohci_arbus.c,v 1.6 2021/11/10 17:19:29 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -107,7 +107,7 @@ ohci_arbus_attach(device_t parent, device_t self, void *aux)
if (ih == NULL)
panic("%s: couldn't establish interrupt", device_xname(self));
/* we don't handle endianess in bus space */
/* we don't handle endianness in bus space */
sc->sc_endian = OHCI_LITTLE_ENDIAN;
int err = ohci_init(sc);

4
sys/arch/mips/cavium/dev/octeon_xhci.c
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@ -1,4 +1,4 @@
/* $NetBSD: octeon_xhci.c,v 1.6 2021/08/07 16:18:59 thorpej Exp $ */
/* $NetBSD: octeon_xhci.c,v 1.7 2021/11/10 17:19:29 msaitoh Exp $ */
/* $OpenBSD: octxhci.c,v 1.4 2019/09/29 04:32:23 visa Exp $ */
/*
@ -327,7 +327,7 @@ octxhci_uctl_init(struct octxhci_softc *sc, uint64_t clock_freq,
XCTL_WR_8(sc, XCTL_CTL, val);
(void)XCTL_RD_8(sc, XCTL_CTL);
/* Fix endianess. */
/* Fix endianness. */
val = XCTL_RD_8(sc, XCTL_SHIM_CFG);
val &= ~XCTL_SHIM_CFG_CSR_BYTE_SWAP;
val &= ~XCTL_SHIM_CFG_DMA_BYTE_SWAP;

6
sys/arch/mips/rmi/rmixl_ohci.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: rmixl_ohci.c,v 1.7 2021/08/07 16:18:59 thorpej Exp $ */
/* $NetBSD: rmixl_ohci.c,v 1.8 2021/11/10 17:19:29 msaitoh Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000, 2002, 2003 The NetBSD Foundation, Inc.
@ -32,7 +32,7 @@
#include "locators.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: rmixl_ohci.c,v 1.7 2021/08/07 16:18:59 thorpej Exp $");
__KERNEL_RCSID(0, "$NetBSD: rmixl_ohci.c,v 1.8 2021/11/10 17:19:29 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -115,7 +115,7 @@ rmixl_ohci_attach(device_t parent, device_t self, void *aux)
device_xname(self));
}
/* we handle endianess in bus space */
/* we handle endianness in bus space */
sc->sc_endian = OHCI_HOST_ENDIAN;
int err = ohci_init(sc);

4
sys/arch/newsmips/apbus/if_snvar.h
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@ -1,4 +1,4 @@
/* $NetBSD: if_snvar.h,v 1.14 2018/10/14 00:10:11 tsutsui Exp $ */
/* $NetBSD: if_snvar.h,v 1.15 2021/11/10 17:19:29 msaitoh Exp $ */
/*
* Copyright (c) 1991 Algorithmics Ltd (http://www.algor.co.uk)
@ -130,7 +130,7 @@ struct sn_softc {
/*
* Accessing SONIC data structures and registers as 32 bit values
* makes code endianess independent. The SONIC is however always in
* makes code endianness independent. The SONIC is however always in
* bigendian mode so it is necessary to ensure that data structures shared
* between the CPU and the SONIC are always in bigendian order.
*/

4
sys/arch/sgimips/dev/crimereg.h
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@ -1,4 +1,4 @@
/* $NetBSD: crimereg.h,v 1.10 2005/12/11 12:18:52 christos Exp $ */
/* $NetBSD: crimereg.h,v 1.11 2021/11/10 17:19:29 msaitoh Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang
@ -55,7 +55,7 @@
#define CRIME_CONTROL_HARD_RESET 0x0800
#define CRIME_CONTROL_SOFT_RESET 0x0400
#define CRIME_CONTROL_DOG_ENABLE 0x0200
#define CRIME_CONTROL_ENDIANESS 0x0100 /* assert for BE */
#define CRIME_CONTROL_ENDIANNESS 0x0100 /* assert for BE */
#define CRIME_CONTROL_CQUEUE_HWM 0x000f
#define CRIME_CONTROL_CQUEUE_SHFT 0
#define CRIME_CONTROL_WBUF_HWM 0x00f0

6
sys/dev/ic/ahcisata_core.c
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@ -1,4 +1,4 @@
/* $NetBSD: ahcisata_core.c,v 1.103 2021/10/11 12:48:10 jmcneill Exp $ */
/* $NetBSD: ahcisata_core.c,v 1.104 2021/11/10 17:19:30 msaitoh Exp $ */
/*
* Copyright (c) 2006 Manuel Bouyer.
@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.103 2021/10/11 12:48:10 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.104 2021/11/10 17:19:30 msaitoh Exp $");
#include <sys/types.h>
#include <sys/malloc.h>
@ -1363,7 +1363,7 @@ ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer)
AHCI_CMDH_SYNC(sc, achp, xfer->c_slot,
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
/* ata(4) expects IDENTIFY data to be in host endianess */
/* ata(4) expects IDENTIFY data to be in host endianness */
if (ata_c->r_command == WDCC_IDENTIFY ||
ata_c->r_command == ATAPI_IDENTIFY_DEVICE) {
idwordbuf = xfer->c_databuf;

6
sys/dev/ic/dm9000.c
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@ -1,4 +1,4 @@
/* $NetBSD: dm9000.c,v 1.30 2021/09/11 20:28:06 andvar Exp $ */
/* $NetBSD: dm9000.c,v 1.31 2021/11/10 17:19:30 msaitoh Exp $ */
/*
* Copyright (c) 2009 Paul Fleischer
@ -918,7 +918,7 @@ pkt_write_2(struct dme_softc *sc, struct mbuf *bufChain)
length++;
}
/* Does shift direction depend on endianess? */
/* Does shift direction depend on endianness? */
left_over_buf = left_over_buf | (b << 8);
bus_space_write_2(sc->sc_iot, sc->sc_ioh,
@ -956,7 +956,7 @@ pkt_write_2(struct dme_softc *sc, struct mbuf *bufChain)
to_write % 2));
left_over_count = 1;
/* XXX: Does this depend on
* the endianess?
* the endianness?
*/
left_over_buf = *write_ptr;

6
sys/dev/ic/i82596.c
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@ -1,4 +1,4 @@
/* $NetBSD: i82596.c,v 1.44 2020/02/04 05:25:39 thorpej Exp $ */
/* $NetBSD: i82596.c,v 1.45 2021/11/10 17:19:30 msaitoh Exp $ */
/*
* Copyright (c) 2003 Jochen Kunz.
@ -43,7 +43,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: i82596.c,v 1.44 2020/02/04 05:25:39 thorpej Exp $");
__KERNEL_RCSID(0, "$NetBSD: i82596.c,v 1.45 2021/11/10 17:19:30 msaitoh Exp $");
/* autoconfig and device stuff */
#include <sys/param.h>
@ -120,7 +120,7 @@ static void iee_cb_setup(struct iee_softc *, uint32_t);
* the chip.
*
* IEE_NEED_SWAP in sc->sc_flags has to be cleared on little endian hardware
* and set on big endian hardware, when endianess conversion is not done
* and set on big endian hardware, when endianness conversion is not done
* by the bus attachment but done by i82596 chip itself.
* Usually you need to set IEE_NEED_SWAP on big endian machines
* where the hardware (the LE/~BE pin) is configured as BE mode.

4
sys/dev/ic/mpt.h
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@ -1,4 +1,4 @@
/* $NetBSD: mpt.h,v 1.8 2014/09/27 16:14:16 jmcneill Exp $ */
/* $NetBSD: mpt.h,v 1.9 2021/11/10 17:19:30 msaitoh Exp $ */
/*
* Copyright (c) 2000, 2001 by Greg Ansley
@ -187,7 +187,7 @@ void mpt_print_scsi_io_request(MSG_SCSI_IO_REQUEST *);
void mpt_print_config_request(void *);
void mpt_print_request(void *);
/********************************** Endianess *********************************/
/******************************** Endianness *********************************/
#define MPT_2_HOST64(ptr, tag) ptr->tag = le64toh(ptr->tag)
#define MPT_2_HOST32(ptr, tag) ptr->tag = le32toh(ptr->tag)
#define MPT_2_HOST16(ptr, tag) ptr->tag = le16toh(ptr->tag)

4
sys/dev/ic/nvmeio.h
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@ -1,4 +1,4 @@
/* $NetBSD: nvmeio.h,v 1.3 2018/04/19 21:50:08 christos Exp $ */
/* $NetBSD: nvmeio.h,v 1.4 2021/11/10 17:19:30 msaitoh Exp $ */
/*-
* Copyright (C) 2012-2013 Intel Corporation
@ -95,7 +95,7 @@ struct nvme_pt_command {
uint32_t timeout;
};
/* Endianess conversion functions for NVMe structs */
/* Endianness conversion functions for NVMe structs */
static __inline void
nvme_le128toh(uint64_t v[2])
{

6
sys/dev/ic/siisata.c
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@ -1,4 +1,4 @@
/* $NetBSD: siisata.c,v 1.49 2021/10/05 08:01:05 rin Exp $ */
/* $NetBSD: siisata.c,v 1.50 2021/11/10 17:19:30 msaitoh Exp $ */
/* from ahcisata_core.c */
@ -79,7 +79,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.49 2021/10/05 08:01:05 rin Exp $");
__KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.50 2021/11/10 17:19:30 msaitoh Exp $");
#include <sys/types.h>
#include <sys/param.h>
@ -1142,7 +1142,7 @@ siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int tfd)
satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis);
}
/* correct the endianess of IDENTIFY data */
/* correct the endianness of IDENTIFY data */
if (ata_c->r_command == WDCC_IDENTIFY ||
ata_c->r_command == ATAPI_IDENTIFY_DEVICE) {
idwordbuf = xfer->c_databuf;

4
sys/dev/marvell/gtethreg.h
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@ -1,4 +1,4 @@
/* $NetBSD: gtethreg.h,v 1.5 2010/04/28 13:51:56 kiyohara Exp $ */
/* $NetBSD: gtethreg.h,v 1.6 2021/11/10 17:19:30 msaitoh Exp $ */
/*
* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
@ -54,7 +54,7 @@
* Descriptors used for both receive & transmit data. Note that the descriptor
* must start on a 4LW boundary. Since the GT accesses the descriptor as
* two 64-bit quantities, we must present them 32bit quantities in the right
* order based on endianess.
* order based on endianness.
*/
struct gt_eth_desc {

4
sys/dev/marvell/gtidmacreg.h
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@ -1,4 +1,4 @@
/* $NetBSD: gtidmacreg.h,v 1.4 2017/01/07 14:32:32 kiyohara Exp $ */
/* $NetBSD: gtidmacreg.h,v 1.5 2021/11/10 17:19:30 msaitoh Exp $ */
/*
* Copyright (c) 2008, 2009 KIYOHARA Takashi
* All rights reserved.
@ -149,7 +149,7 @@
#define MVXORE_XEXCR_DBL_32B (2 << 8)
#define MVXORE_XEXCR_DBL_64B (3 << 8)
#define MVXORE_XEXCR_DBL_128B (4 << 8)
#define MVXORE_XEXCR_DRDRESSWP (1 << 12) /* Endianess Swap */
#define MVXORE_XEXCR_DRDRESSWP (1 << 12) /* Endianness Swap */
#define MVXORE_XEXCR_DWRREQSWP (1 << 13) /* ReadReq/WriteRes */
#define MVXORE_XEXCR_DESSWP (1 << 14) /* Desc read/write */
#define MVXORE_XEXCR_REGACCPROTECT (1 << 15) /* Reg Access protect */

6
sys/dev/marvell/gtreg.h
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@ -1,4 +1,4 @@
/* $NetBSD: gtreg.h,v 1.6 2021/10/30 21:08:58 andvar Exp $ */
/* $NetBSD: gtreg.h,v 1.7 2021/11/10 17:19:30 msaitoh Exp $ */
/*
* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
@ -332,7 +332,7 @@
* 11:11 AACKDelay Address Acknowledge Delay
* 0: AACK* is asserted one cycle after TS*.
* 1: AACK* is asserted two cycles after TS*.
* 12:12 Endianess Must be 0
* 12:12 Endianness Must be 0
* NOTE: The GT64260 does not support the PowerPC
* Little Endian convention
* 13:13 Pipeline Pipeline Enable
@ -390,7 +390,7 @@
#define GT_CPUCfg_NoMatchCntEn GT__BIT( 9)
#define GT_CPUCfg_NoMatchCntExt GT__BIT(10)
#define GT_CPUCfg_AACKDelay GT__BIT(11)
#define GT_CPUCfg_Endianess GT__BIT(12)
#define GT_CPUCfg_Endianness GT__BIT(12)
#define GT_CPUCfg_Pipeline GT__BIT(13)
#define GT_CPUCfg_TADelay GT__BIT(15)
#define GT_CPUCfg_RdOOO GT__BIT(16)

6
sys/dev/mvme/if_ie_mvme.c
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@ -1,4 +1,4 @@
/* $NetBSD: if_ie_mvme.c,v 1.20 2014/03/25 15:52:33 christos Exp $ */
/* $NetBSD: if_ie_mvme.c,v 1.21 2021/11/10 17:19:30 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2002 The NetBSD Foundation, Inc.
@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: if_ie_mvme.c,v 1.20 2014/03/25 15:52:33 christos Exp $");
__KERNEL_RCSID(0, "$NetBSD: if_ie_mvme.c,v 1.21 2021/11/10 17:19:30 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -109,7 +109,7 @@ ie_reset(struct ie_softc *sc, int why)
/*
* Set the BUSY and BUS_USE bytes here, since the MI code
* incorrectly assumes it can use byte addressing to set it.
* (due to wrong-endianess of the chip)
* (due to wrong-endianness of the chip)
*/
ie_write_16(sc, IE_ISCP_BUSY(sc->iscp), 1);
ie_write_16(sc, IE_SCP_BUS_USE(sc->scp), IE_BUS_USE);

4
sys/dev/pci/cxgb/cxgb_t3_hw.c
View File

@ -28,7 +28,7 @@ POSSIBILITY OF SUCH DAMAGE.
***************************************************************************/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cxgb_t3_hw.c,v 1.5 2021/08/02 12:56:24 andvar Exp $");
__KERNEL_RCSID(0, "$NetBSD: cxgb_t3_hw.c,v 1.6 2021/11/10 17:19:30 msaitoh Exp $");
#ifdef CONFIG_DEFINED
@ -785,7 +785,7 @@ static int flash_wait_op(adapter_t *adapter, int attempts, int delay)
* Read the specified number of 32-bit words from the serial flash.
* If @byte_oriented is set the read data is stored as a byte array
* (i.e., big-endian), otherwise as 32-bit words in the platform's
* natural endianess.
* natural endianness.
*/
int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
u32 *data, int byte_oriented)

8
sys/dev/pcmcia/if_malo_pcmcia.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_malo_pcmcia.c,v 1.26 2021/06/16 00:21:19 riastradh Exp $ */
/* $NetBSD: if_malo_pcmcia.c,v 1.27 2021/11/10 17:19:30 msaitoh Exp $ */
/* $OpenBSD: if_malo.c,v 1.65 2009/03/29 21:53:53 sthen Exp $ */
/*
@ -18,7 +18,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: if_malo_pcmcia.c,v 1.26 2021/06/16 00:21:19 riastradh Exp $");
__KERNEL_RCSID(0, "$NetBSD: if_malo_pcmcia.c,v 1.27 2021/11/10 17:19:30 msaitoh Exp $");
#ifdef _MODULE
#include <sys/module.h>
@ -2001,10 +2001,10 @@ cmalo_cmd_response(struct malo_softc *sc)
cmalo_hexdump(sc->sc_cmd, psize);
/*
* We convert the header values into the machines correct endianess,
* We convert the header values into the machines correct endianness,
* so we don't have to le16toh() all over the code. The body is
* kept in the cards order, little endian. We need to take care
* about the body endianess in the corresponding response routines.
* about the body endianness in the corresponding response routines.
*/
hdr->cmd = le16toh(hdr->cmd);
hdr->size = le16toh(hdr->size);

4
tests/ipf/h_common.sh
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@ -1,4 +1,4 @@
# $NetBSD: h_common.sh,v 1.8 2013/05/16 07:20:29 martin Exp $
# $NetBSD: h_common.sh,v 1.9 2021/11/10 17:19:30 msaitoh Exp $
#
# Copyright (c) 2008, 2010 The NetBSD Foundation, Inc.
# All rights reserved.
@ -79,7 +79,7 @@ failing_test_case()
failing_test_case_be()
{
# this test fails on some architectures - not fully analyzed, assume
# an endianess bug
# an endianness bug
local name="${1}"; shift
local check_function="${1}"; shift
local reason="${1}"; shift