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Add write-through cache work-around for ARM11 as well as ARM9/ARM10. Analyzed

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& tested on i.MX35 with help from Tsubai Masanari.
This commit is contained in:
uebayasi 2009-12-27 05:14:56 +00:00
parent 2a8f722d1a
commit fe705f1018
5 changed files with 38 additions and 8 deletions
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8
sys/arch/arm/arm/cpufunc.c
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@ -1,4 +1,4 @@
/* $NetBSD: cpufunc.c,v 1.93 2009/03/15 22:23:16 cegger Exp $ */
/* $NetBSD: cpufunc.c,v 1.94 2009/12/27 05:14:56 uebayasi Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@ -48,7 +48,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.93 2009/03/15 22:23:16 cegger Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.94 2009/12/27 05:14:56 uebayasi Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@ -1426,7 +1426,11 @@ set_cpufuncs(void)
cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
cpu_do_powersave = 1; /* Enable powersave */
get_cachetype_cp15();
#ifdef ARM11_CACHE_WRITE_THROUGH
pmap_pte_init_arm11();
#else
pmap_pte_init_generic();
#endif
if (arm_cache_prefer_mask)
uvmexp.ncolors = (arm_cache_prefer_mask >> PGSHIFT) + 1;

27
sys/arch/arm/arm32/pmap.c
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@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.203 2009/11/28 11:44:45 scw Exp $ */
/* $NetBSD: pmap.c,v 1.204 2009/12/27 05:14:56 uebayasi Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@ -211,7 +211,7 @@
#include <machine/param.h>
#include <arm/arm32/katelib.h>
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.203 2009/11/28 11:44:45 scw Exp $");
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.204 2009/12/27 05:14:56 uebayasi Exp $");
#ifdef PMAP_DEBUG
@ -5971,7 +5971,7 @@ pmap_pte_init_arm9(void)
pte_l2_l_cache_mode_pt = L2_C;
pte_l2_s_cache_mode_pt = L2_C;
}
#endif /* CPU_ARM9 */
#endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */
#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */
#if defined(CPU_ARM10)
@ -5996,6 +5996,27 @@ pmap_pte_init_arm10(void)
}
#endif /* CPU_ARM10 */
#if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH)
void
pmap_pte_init_arm11(void)
{
/*
* ARM11 is compatible with generic, but we want to use
* write-through caching for now.
*/
pmap_pte_init_generic();
pte_l1_s_cache_mode = L1_S_C;
pte_l2_l_cache_mode = L2_C;
pte_l2_s_cache_mode = L2_C;
pte_l1_s_cache_mode_pt = L1_S_C;
pte_l2_l_cache_mode_pt = L2_C;
pte_l2_s_cache_mode_pt = L2_C;
}
#endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */
#if ARM_MMU_SA1 == 1
void
pmap_pte_init_sa1(void)

3
sys/arch/arm/conf/files.arm
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@ -1,4 +1,4 @@
# $NetBSD: files.arm,v 1.96 2009/01/18 16:42:09 bjh21 Exp $
# $NetBSD: files.arm,v 1.97 2009/12/27 05:14:56 uebayasi Exp $
# temporary define to allow easy moving to ../arch/arm/arm32
defflag ARM32
@ -27,6 +27,7 @@ defflag opt_cpuoptions.h ARM9_CACHE_WRITE_THROUGH
defflag opt_cpuoptions.h PROCESS_ID_IS_CURLWP
defflag opt_cpuoptions.h PROCESS_ID_IS_CURCPU
defflag opt_cpuoptions.h ARM11_PMC
defflag opt_cpuoptions.h ARM11_CACHE_WRITE_THROUGH
# Interrupt implementation header definition.
defparam opt_arm_intr_impl.h ARM_INTR_IMPL

5
sys/arch/arm/include/arm32/pmap.h
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@ -1,4 +1,4 @@
/* $NetBSD: pmap.h,v 1.93 2009/10/22 19:50:55 rmind Exp $ */
/* $NetBSD: pmap.h,v 1.94 2009/12/27 05:14:56 uebayasi Exp $ */
/*
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@ -462,6 +462,9 @@ void pmap_pte_init_arm9(void);
#if defined(CPU_ARM10)
void pmap_pte_init_arm10(void);
#endif /* CPU_ARM10 */
#if defined(CPU_ARM11)
void pmap_pte_init_arm11(void);
#endif /* CPU_ARM11 */
#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
#if ARM_MMU_SA1 == 1

3
sys/arch/evbarm/conf/std.imx31
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@ -1,4 +1,4 @@
# $NetBSD: std.imx31,v 1.2 2008/04/27 18:58:46 matt Exp $
# $NetBSD: std.imx31,v 1.3 2009/12/27 05:14:56 uebayasi Exp $
#
# standard NetBSD/evbarm options for FreeScale I.MX31
@ -17,6 +17,7 @@ makeoptions CPUFLAGS="-mcpu=arm1136j-s"
# To support easy transit to ../arch/arm/arm32
options ARM32
options ARM11_PMC
options ARM11_CACHE_WRITE_THROUGH
makeoptions LOADADDRESS="0x80100000"
makeoptions BOARDTYPE="imx31"