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nvmm: Filter CR4 bits on x86 SVM (AMD). 

In particular, prohibit PKE, Protection Key Enable, which requires
some additional management of CPU state by nvmm.
This commit is contained in:
riastradh 2023-02-23 02:54:02 +00:00
parent 69fcdd9c6b
commit fe02344ba9
1 changed files with 30 additions and 2 deletions
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32
sys/dev/nvmm/x86/nvmm_x86_svm.c
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@ -1,4 +1,4 @@
/* $NetBSD: nvmm_x86_svm.c,v 1.84 2022/08/20 23:48:51 riastradh Exp $ */
/* $NetBSD: nvmm_x86_svm.c,v 1.85 2023/02/23 02:54:02 riastradh Exp $ */
/*
* Copyright (c) 2018-2020 Maxime Villard, m00nbsd.net
@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.84 2022/08/20 23:48:51 riastradh Exp $");
__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.85 2023/02/23 02:54:02 riastradh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -523,6 +523,33 @@ static uint64_t svm_xcr0_mask __read_mostly;
#define CR4_TLB_FLUSH \
(CR4_PSE|CR4_PAE|CR4_PGE|CR4_PCIDE|CR4_SMEP)
#define CR4_VALID \
(CR4_VME | \
CR4_PVI | \
CR4_TSD | \
CR4_DE | \
CR4_PSE | \
CR4_PAE | \
CR4_MCE | \
CR4_PGE | \
CR4_PCE | \
CR4_OSFXSR | \
CR4_OSXMMEXCPT | \
CR4_UMIP | \
/* CR4_LA57 excluded */ \
/* bit 13 reserved on AMD */ \
/* bit 14 reserved on AMD */ \
/* bit 15 reserved on AMD */ \
CR4_FSGSBASE | \
CR4_PCIDE | \
CR4_OSXSAVE | \
/* bit 19 reserved on AMD */ \
CR4_SMEP | \
CR4_SMAP \
/* CR4_PKE excluded */ \
/* CR4_CET excluded */ \
/* bits 24:63 reserved on AMD */)
/* -------------------------------------------------------------------------- */
struct svm_machdata {
@ -1853,6 +1880,7 @@ svm_vcpu_setstate(struct nvmm_cpu *vcpu)
vmcb->state.cr2 = state->crs[NVMM_X64_CR_CR2];
vmcb->state.cr3 = state->crs[NVMM_X64_CR_CR3];
vmcb->state.cr4 = state->crs[NVMM_X64_CR_CR4];
vmcb->state.cr4 &= CR4_VALID;
vmcb->ctrl.v &= ~VMCB_CTRL_V_TPR;
vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8],