sun4/sun4c MMU: keep `wired' status per page, implemented by defining a bit
in the PTE word that is not used by the hardware. Use it to unlock a `pmeg' if the wired count in a segment drops to zero.
This commit is contained in:
pk
parent
b1fbf8b8ca
commit
fda797e0a4
@ -1,4 +1,4 @@
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/* $NetBSD: pmap.h,v 1.69 2003/08/12 15:13:13 pk Exp $ */
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/* $NetBSD: pmap.h,v 1.70 2003/08/16 19:21:23 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -174,6 +174,7 @@ struct segmap {
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int *sg_pte; /* points to NPTESG PTEs */
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pmeg_t sg_pmeg; /* the MMU segment number (4c) */
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u_char sg_npte; /* number of valid PTEs per seg */
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int8_t sg_nwired; /* number of wired pages */
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};
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typedef struct pmap *pmap_t;
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.266 2003/08/14 11:00:02 hannken Exp $ */
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/* $NetBSD: pmap.c,v 1.267 2003/08/16 19:21:21 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -56,7 +56,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.266 2003/08/14 11:00:02 hannken Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.267 2003/08/16 19:21:21 pk Exp $");
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#include "opt_ddb.h"
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#include "opt_kgdb.h"
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@ -864,8 +864,8 @@ setpte4m(va, pte)
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int pte;
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{
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struct pmap *pm;
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struct regmap *rm;
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struct segmap *sm;
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struct regmap *rp;
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struct segmap *sp;
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if (getcontext4m() != 0)
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panic("setpte4m: user context");
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@ -877,20 +877,18 @@ setpte4m(va, pte)
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if (pm->pm_regmap == NULL)
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panic("setpte4m: no regmap entry");
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#endif
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rm = &pm->pm_regmap[VA_VREG(va)];
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sm = &rm->rg_segmap[VA_VSEG(va)];
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rp = &pm->pm_regmap[VA_VREG(va)];
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sp = &rp->rg_segmap[VA_VSEG(va)];
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#ifdef DEBUG
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if (rm->rg_segmap == NULL)
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panic("setpte4m: no segmap for va %p (rp=%p)",
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(caddr_t)va, (caddr_t)rm);
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if (rp->rg_segmap == NULL)
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panic("setpte4m: no segmap for va %lx (rp=%p)", va, rp);
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if (sm->sg_pte == NULL)
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panic("setpte4m: no pte for va %p (rp=%p, sp=%p)",
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(caddr_t)va, rm, sm);
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if (sp->sg_pte == NULL)
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panic("setpte4m: no pte for va %lx (rp=%p,sp=%p)", va, rp, sp);
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#endif
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tlb_flush_page(va, 0, CPUSET_ALL);
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setpgt4m(sm->sg_pte + VA_SUN4M_VPG(va), pte);
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setpgt4m(sp->sg_pte + VA_SUN4M_VPG(va), pte);
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}
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/*
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@ -1551,10 +1549,12 @@ mmu_setup4m_L3(pagtblptd, sp)
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/*
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* MMU management.
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*/
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int me_alloc(struct mmuq *, struct pmap *, int, int);
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static int me_alloc(struct mmuq *, struct pmap *, int, int);
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static void me_free(struct pmap *, u_int);
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int region_alloc(struct mmuq *, struct pmap *, int);
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void region_free(struct pmap *, u_int);
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#if defined(SUN4_MMU3L)
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static int region_alloc(struct mmuq *, struct pmap *, int);
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static void region_free(struct pmap *, u_int);
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#endif
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/*
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@ -1571,7 +1571,7 @@ void region_free(struct pmap *, u_int);
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* since it implements the dynamic allocation of MMU entries.
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*/
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int
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static __inline__ int
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me_alloc(mh, newpm, newvreg, newvseg)
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struct mmuq *mh;
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struct pmap *newpm;
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@ -1579,7 +1579,7 @@ me_alloc(mh, newpm, newvreg, newvseg)
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{
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struct mmuentry *me;
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struct pmap *pm;
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int i, va, *pte, tpte;
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int i, va, *ptep, pte;
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int ctx;
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struct regmap *rp;
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struct segmap *sp;
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@ -1647,7 +1647,7 @@ me_alloc(mh, newpm, newvreg, newvseg)
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rp = &pm->pm_regmap[me->me_vreg];
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sp = &rp->rg_segmap[me->me_vseg];
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pte = sp->sg_pte;
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ptep = sp->sg_pte;
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#ifdef DEBUG
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if (sp->sg_pmeg != me->me_cookie)
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@ -1712,13 +1712,14 @@ me_alloc(mh, newpm, newvreg, newvseg)
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*/
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i = NPTESG;
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do {
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tpte = getpte4(va);
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if ((tpte & (PG_V | PG_TYPE)) == (PG_V | PG_OBMEM)) {
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int swbits = *ptep & PG_MBZ;
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pte = getpte4(va);
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if ((pte & (PG_V | PG_TYPE)) == (PG_V | PG_OBMEM)) {
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struct vm_page *pg;
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if ((pg = pvhead4_4c(tpte)) != NULL)
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VM_MDPAGE_PVHEAD(pg)->pv_flags |= MR4_4C(tpte);
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if ((pg = pvhead4_4c(pte)) != NULL)
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VM_MDPAGE_PVHEAD(pg)->pv_flags |= MR4_4C(pte);
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}
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*pte++ = tpte & ~(PG_U|PG_M);
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*ptep++ = swbits | (pte & ~(PG_U|PG_M));
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va += NBPG;
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} while (--i > 0);
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@ -1977,7 +1978,7 @@ mmu_pagein_reg(struct pmap *pm, struct regmap *rp, vaddr_t va,
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}
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#endif /* SUN4_MMU3L */
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static __inline__ void
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static void
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mmu_pmeg_lock(int pmeg)
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{
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struct mmuentry *me = &mmusegments[pmeg];
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@ -1985,7 +1986,15 @@ mmu_pmeg_lock(int pmeg)
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MMUQ_INSERT_TAIL(&segm_locked, me, me_list);
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}
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static __inline__ void
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static void
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mmu_pmeg_unlock(int pmeg)
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{
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struct mmuentry *me = &mmusegments[pmeg];
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MMUQ_REMOVE(me, me_list);
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MMUQ_INSERT_TAIL(&segm_lru, me, me_list);
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}
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static void
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mmu_pagein_seg(struct pmap *pm, struct segmap *sp, vaddr_t va,
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int vr, int vs, struct mmuq *mh)
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{
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@ -2011,7 +2020,7 @@ mmu_pagein_seg(struct pmap *pm, struct segmap *sp, vaddr_t va,
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pte = sp->sg_pte;
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i = NPTESG;
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do {
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setpte4(va, *pte++);
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setpte4(va, *pte++ & ~PG_MBZ);
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va += NBPG;
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} while (--i > 0);
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splx(s);
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@ -2320,7 +2329,7 @@ pv_changepte4_4c(pg, bis, bic)
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struct vm_page *pg;
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int bis, bic;
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{
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int *pte;
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int pte, *ptep;
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struct pvlist *pv;
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struct pmap *pm;
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int va, vr, vs;
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@ -2344,20 +2353,17 @@ pv_changepte4_4c(pg, bis, bic)
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vs = VA_VSEG(va);
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rp = &pm->pm_regmap[vr];
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sp = &rp->rg_segmap[vs];
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pte = sp->sg_pte;
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ptep = &sp->sg_pte[VA_VPG(va)];
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if (sp->sg_pmeg == seginval) {
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/* not in hardware: just fix software copy */
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pte += VA_VPG(va);
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*pte = (*pte | bis) & ~bic;
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*ptep = (*ptep | bis) & ~bic;
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} else {
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int tpte;
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/* in hardware: fix hardware copy */
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if (CTX_USABLE(pm,rp)) {
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setcontext4(pm->pm_ctxnum);
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/* XXX should flush only when necessary */
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tpte = getpte4(va);
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pte = getpte4(va);
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/*
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* XXX: always flush cache; conservative, but
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* needed to invalidate cache tag protection
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@ -2371,14 +2377,13 @@ pv_changepte4_4c(pg, bis, bic)
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setregmap(0, tregion);
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setsegmap(0, sp->sg_pmeg);
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va = VA_VPG(va) << PGSHIFT;
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tpte = getpte4(va);
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pte = getpte4(va);
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}
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if (tpte & PG_V)
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VM_MDPAGE_PVHEAD(pg)->pv_flags |= MR4_4C(tpte);
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tpte = (tpte | bis) & ~bic;
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setpte4(va, tpte);
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if (pte != NULL) /* update software copy */
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pte[VA_VPG(va)] = tpte;
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if (pte & PG_V)
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VM_MDPAGE_PVHEAD(pg)->pv_flags |= MR4_4C(pte);
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pte = (pte | bis) & ~bic;
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setpte4(va, pte);
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*ptep = (*ptep & PG_MBZ) | pte;
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}
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}
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setcontext4(ctx);
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@ -2398,7 +2403,7 @@ pv_syncflags4_4c(pg)
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{
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struct pvlist *pv;
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struct pmap *pm;
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int tpte, va, vr, vs, pmeg, flags;
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int pte, va, vr, vs, pmeg, flags;
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int ctx, s;
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struct regmap *rp;
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struct segmap *sp;
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@ -2424,8 +2429,8 @@ pv_syncflags4_4c(pg)
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if (CTX_USABLE(pm,rp)) {
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setcontext4(pm->pm_ctxnum);
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/* XXX should flush only when necessary */
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tpte = getpte4(va);
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if (tpte & PG_M)
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pte = getpte4(va);
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if (pte & PG_M)
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cache_flush_page(va, pm->pm_ctxnum);
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} else {
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/* Make temp map in ctx 0 to access the PTE */
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@ -2434,12 +2439,12 @@ pv_syncflags4_4c(pg)
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setregmap(0, tregion);
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setsegmap(0, pmeg);
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va = VA_VPG(va) << PGSHIFT;
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tpte = getpte4(va);
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pte = getpte4(va);
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}
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if (tpte & (PG_M|PG_U) && tpte & PG_V) {
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flags |= MR4_4C(tpte);
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tpte &= ~(PG_M|PG_U);
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setpte4(va, tpte);
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if (pte & (PG_M|PG_U) && pte & PG_V) {
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flags |= MR4_4C(pte);
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pte &= ~(PG_M|PG_U);
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setpte4(va, pte);
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}
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}
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@ -3101,7 +3106,8 @@ pmap_bootstrap4_4c(top, nctx, nregion, nsegment)
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#if defined(SUN4_MMU3L)
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struct mmuentry *mmureg;
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#endif
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struct regmap *rp;
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struct regmap *rp;
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struct segmap *sp;
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int i, j;
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int npte, zseg, vr, vs;
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int startscookie, scookie;
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@ -3238,9 +3244,9 @@ pmap_bootstrap4_4c(top, nctx, nregion, nsegment)
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kernel_regmap_store[i].rg_segmap =
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&kernel_segmap_store[i * NSEGRG];
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for (j = NSEGRG; --j >= 0;) {
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kernel_segmap_store[i * NSEGRG + j].sg_pmeg = seginval;
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kernel_segmap_store[i * NSEGRG + j].sg_pte =
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&kptes[(i * NSEGRG + j) * NPTESG];
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sp = &kernel_segmap_store[i * NSEGRG + j];
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sp->sg_pmeg = seginval;
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sp->sg_pte = &kptes[(i * NSEGRG + j) * NPTESG];
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}
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}
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@ -3391,13 +3397,14 @@ pmap_bootstrap4_4c(top, nctx, nregion, nsegment)
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mmuseg->me_pmap = pmap_kernel();
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mmuseg->me_vreg = vr;
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mmuseg->me_vseg = vs % NSEGRG;
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rp->rg_segmap[vs % NSEGRG].sg_pmeg = scookie;
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sp = &rp->rg_segmap[vs % NSEGRG];
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sp->sg_pmeg = scookie;
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npte = ++scookie < zseg ? NPTESG : lastpage;
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rp->rg_segmap[vs % NSEGRG].sg_npte = npte;
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sp->sg_npte = npte;
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sp->sg_nwired = npte;
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rp->rg_nsegmap += 1;
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for (i = 0; i < npte; i++)
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rp->rg_segmap[vs % NSEGRG].sg_pte[i] =
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getpte4(p + i * NBPG);
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sp->sg_pte[i] = getpte4(p + i * NBPG) | PG_WIRED;
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mmuseg++;
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vs++;
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if (scookie < zseg) {
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@ -3517,7 +3524,10 @@ pmap_bootstrap4_4c(top, nctx, nregion, nsegment)
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*/
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for (p = etext_gap_start; p < etext_gap_end; p += NBPG) {
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rp = &pmap_kernel()->pm_regmap[VA_VREG(p)];
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rp->rg_segmap[VA_VSEG(p)].sg_pte[VA_VPG(p)] = 0;
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sp = &rp->rg_segmap[VA_VSEG(p)];
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sp->sg_nwired--;
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sp->sg_npte--;
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sp->sg_pte[VA_VPG(p)] = 0;
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setpte4(p, 0);
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}
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@ -4434,6 +4444,7 @@ static void pgt_lvl23_remove4_4c(struct pmap *pm, struct regmap *rp,
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panic("pgt_rm: pm %p: nsegmap = %d\n", pm, rp->rg_nsegmap);
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if (--rp->rg_nsegmap == 0) {
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#if defined(SUN4_MMU3L)
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if (HASSUN4_MMU3L) {
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if (rp->rg_smeg != reginval) {
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if (pm == pmap_kernel()) {
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@ -4452,6 +4463,7 @@ static void pgt_lvl23_remove4_4c(struct pmap *pm, struct regmap *rp,
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rp->rg_smeg = reginval;
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}
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}
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#endif /* SUN4_MMU3L */
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/* Free software tables for non-kernel maps */
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if (pm != pmap_kernel()) {
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GAP_WIDEN(pm,vr);
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@ -4612,6 +4624,7 @@ pmap_rmk4_4c(pm, va, endva, vr, vs)
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return;
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pmeg = sp->sg_pmeg;
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inmmu = pmeg != seginval;
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ptep = &sp->sg_pte[VA_VPG(va)];
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/* decide how to flush cache */
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npg = (endva - va) >> PGSHIFT;
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@ -4626,7 +4639,6 @@ pmap_rmk4_4c(pm, va, endva, vr, vs)
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perpage = (CACHEINFO.c_vactype != VAC_NONE);
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}
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ptep = sp->sg_pte + VA_VPG(va);
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for (; va < endva; va += NBPG, ptep++) {
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pte = *ptep;
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if (inmmu)
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@ -4654,13 +4666,25 @@ pmap_rmk4_4c(pm, va, endva, vr, vs)
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panic("pmap_rmk: too many PTEs in segment; "
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"va 0x%lx; endva 0x%lx", va, endva);
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#endif
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if (pte & PG_WIRED)
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sp->sg_nwired--;
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if (inmmu)
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setpte4(va, 0);
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*ptep = 0;
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}
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#ifdef DIAGNOSTIC
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if (sp->sg_nwired > nleft || sp->sg_nwired < 0)
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panic("pmap_rmk: pm %p, va %lx: nleft=%d, nwired=%d",
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pm, va, nleft, sp->sg_nwired);
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#endif
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if ((sp->sg_npte = nleft) == 0)
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pgt_lvl23_remove4_4c(pm, rp, sp, vr, vs);
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else if (sp->sg_nwired == 0) {
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if (sp->sg_pmeg != seginval)
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mmu_pmeg_unlock(sp->sg_pmeg);
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}
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}
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#endif /* SUN4 || SUN4C */
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@ -4742,7 +4766,7 @@ pmap_rmu4_4c(pm, va, endva, vr, vs)
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vaddr_t va, endva;
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int vr, vs;
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{
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int *ptep, pteva, tpte, perpage, npg;
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int *ptep, pteva, pte, perpage, npg;
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struct vm_page *pg;
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int nleft, pmeg, inmmu;
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struct regmap *rp;
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@ -4789,23 +4813,23 @@ pmap_rmu4_4c(pm, va, endva, vr, vs)
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ptep = sp->sg_pte + VA_VPG(va);
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for (; va < endva; ptep++, pteva += NBPG, va += NBPG) {
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int mmupte;
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tpte = *ptep;
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pte = *ptep;
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if (inmmu)
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mmupte = getpte4(pteva);
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if ((tpte & PG_V) == 0) {
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if ((pte & PG_V) == 0) {
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#ifdef DIAGNOSTIC
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if (inmmu && (mmupte & PG_V) != 0)
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printf("pmap_rmu: tpte=%x, mmupte=%x\n",
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tpte, getpte4(pteva));
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printf("pmap_rmu: pte=%x, mmupte=%x\n",
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pte, getpte4(pteva));
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#endif
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continue;
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}
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if ((tpte & PG_TYPE) == PG_OBMEM) {
|
||||
if ((pte & PG_TYPE) == PG_OBMEM) {
|
||||
/* if cacheable, flush page as needed */
|
||||
if (perpage && (mmupte & PG_NC) == 0)
|
||||
cache_flush_page(va, pm->pm_ctxnum);
|
||||
if ((pg = pvhead4_4c(tpte)) != NULL) {
|
||||
if ((pg = pvhead4_4c(pte)) != NULL) {
|
||||
if (inmmu)
|
||||
VM_MDPAGE_PVHEAD(pg)->pv_flags |= MR4_4C(mmupte);
|
||||
pv_unlink4_4c(pg, pm, va);
|
||||
@ -4819,11 +4843,23 @@ pmap_rmu4_4c(pm, va, endva, vr, vs)
|
||||
#endif
|
||||
if (inmmu)
|
||||
setpte4(pteva, 0);
|
||||
|
||||
if (pte & PG_WIRED)
|
||||
sp->sg_nwired--;
|
||||
*ptep = 0;
|
||||
}
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
if (sp->sg_nwired > nleft || sp->sg_nwired < 0)
|
||||
panic("pmap_rmu: pm %p, va %lx: nleft=%d, nwired=%d",
|
||||
pm, va, nleft, sp->sg_nwired);
|
||||
#endif
|
||||
if ((sp->sg_npte = nleft) == 0)
|
||||
pgt_lvl23_remove4_4c(pm, rp, sp, vr, vs);
|
||||
else if (sp->sg_nwired == 0) {
|
||||
if (sp->sg_pmeg != seginval)
|
||||
mmu_pmeg_unlock(sp->sg_pmeg);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* SUN4 || SUN4C */
|
||||
@ -4930,7 +4966,8 @@ pmap_page_protect4_4c(pg, prot)
|
||||
{
|
||||
struct pvlist *pv, *npv;
|
||||
struct pmap *pm;
|
||||
int va, vr, vs, pteva, tpte;
|
||||
vaddr_t va;
|
||||
int vr, vs, pteva, pte, *ptep;
|
||||
int flags, nleft, s, ctx;
|
||||
struct regmap *rp;
|
||||
struct segmap *sp;
|
||||
@ -4981,41 +5018,48 @@ pmap_page_protect4_4c(pg, prot)
|
||||
if ((nleft = sp->sg_npte) <= 0)
|
||||
panic("pmap_page_protect: empty vseg");
|
||||
sp->sg_npte = --nleft;
|
||||
ptep = &sp->sg_pte[VA_VPG(va)];
|
||||
|
||||
if (sp->sg_pmeg == seginval) {
|
||||
sp->sg_pte[VA_VPG(va)] = 0;
|
||||
if (nleft == 0)
|
||||
pgt_lvl23_remove4_4c(pm, rp, sp, vr, vs);
|
||||
goto nextpv;
|
||||
}
|
||||
if (*ptep & PG_WIRED)
|
||||
sp->sg_nwired--;
|
||||
|
||||
if (CTX_USABLE(pm,rp)) {
|
||||
setcontext4(pm->pm_ctxnum);
|
||||
pteva = va;
|
||||
cache_flush_page(va, pm->pm_ctxnum);
|
||||
} else {
|
||||
setcontext4(0);
|
||||
/* XXX use per-cpu pteva? */
|
||||
if (HASSUN4_MMU3L)
|
||||
setregmap(0, tregion);
|
||||
setsegmap(0, sp->sg_pmeg);
|
||||
pteva = VA_VPG(va) << PGSHIFT;
|
||||
}
|
||||
if (sp->sg_pmeg != seginval) {
|
||||
/* Update PV flags */
|
||||
if (CTX_USABLE(pm,rp)) {
|
||||
setcontext4(pm->pm_ctxnum);
|
||||
pteva = va;
|
||||
cache_flush_page(va, pm->pm_ctxnum);
|
||||
} else {
|
||||
setcontext4(0);
|
||||
/* XXX use per-cpu pteva? */
|
||||
if (HASSUN4_MMU3L)
|
||||
setregmap(0, tregion);
|
||||
setsegmap(0, sp->sg_pmeg);
|
||||
pteva = VA_VPG(va) << PGSHIFT;
|
||||
}
|
||||
|
||||
tpte = getpte4(pteva);
|
||||
#ifdef DIAGNOSTIC
|
||||
if ((tpte & PG_V) == 0)
|
||||
panic("pmap_page_protect !PG_V: "
|
||||
"ctx %d, va 0x%x, pte 0x%x",
|
||||
pm->pm_ctxnum, va, tpte);
|
||||
pte = getpte4(pteva);
|
||||
#ifdef DIAGNOSTIC
|
||||
if ((pte & PG_V) == 0)
|
||||
panic("pmap_page_protect !PG_V: "
|
||||
"ctx %d, va 0x%lx, pte 0x%x",
|
||||
pm->pm_ctxnum, va, pte);
|
||||
#endif
|
||||
flags |= MR4_4C(tpte);
|
||||
flags |= MR4_4C(pte);
|
||||
|
||||
setpte4(pteva, 0);
|
||||
sp->sg_pte[VA_VPG(pteva)] = 0;
|
||||
setpte4(pteva, 0);
|
||||
#ifdef DIAGNOSTIC
|
||||
if (sp->sg_nwired > nleft || sp->sg_nwired < 0)
|
||||
panic("pmap_page_protect: pm %p, va %lx: nleft=%d, nwired=%d",
|
||||
pm, va, nleft, sp->sg_nwired);
|
||||
#endif
|
||||
if (sp->sg_nwired == 0)
|
||||
mmu_pmeg_unlock(sp->sg_pmeg);
|
||||
}
|
||||
|
||||
*ptep = 0;
|
||||
if (nleft == 0)
|
||||
pgt_lvl23_remove4_4c(pm, rp, sp, vr, vs);
|
||||
nextpv:
|
||||
npv = pv->pv_next;
|
||||
if (pv != VM_MDPAGE_PVHEAD(pg))
|
||||
pool_put(&pv_pool, pv);
|
||||
@ -5084,15 +5128,15 @@ pmap_protect4_4c(pm, sva, eva, prot)
|
||||
panic("pmap_protect: no pages");
|
||||
#endif
|
||||
if (sp->sg_pmeg == seginval) {
|
||||
int *pte = &sp->sg_pte[VA_VPG(va)];
|
||||
int *ptep = &sp->sg_pte[VA_VPG(va)];
|
||||
|
||||
/* not in MMU; just clear PG_W from core copies */
|
||||
for (; va < nva; va += NBPG)
|
||||
*pte++ &= ~PG_W;
|
||||
*ptep++ &= ~PG_W;
|
||||
} else {
|
||||
/* in MMU: take away write bits from MMU PTEs */
|
||||
if (CTX_USABLE(pm,rp)) {
|
||||
int tpte;
|
||||
int pte;
|
||||
|
||||
/*
|
||||
* Flush cache so that any existing cache
|
||||
@ -5103,12 +5147,12 @@ pmap_protect4_4c(pm, sva, eva, prot)
|
||||
(nva - va) >> PGSHIFT;
|
||||
setcontext4(pm->pm_ctxnum);
|
||||
for (; va < nva; va += NBPG) {
|
||||
tpte = getpte4(va);
|
||||
if ((tpte & (PG_W|PG_TYPE)) ==
|
||||
pte = getpte4(va);
|
||||
if ((pte & (PG_W|PG_TYPE)) ==
|
||||
(PG_W|PG_OBMEM)) {
|
||||
pmap_stats.ps_npg_prot_actual++;
|
||||
cache_flush_page(va, pm->pm_ctxnum);
|
||||
setpte4(va, tpte & ~PG_W);
|
||||
setpte4(va, pte & ~PG_W);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
@ -5146,7 +5190,8 @@ pmap_changeprot4_4c(pm, va, prot, flags)
|
||||
vm_prot_t prot;
|
||||
int flags;
|
||||
{
|
||||
int vr, vs, tpte, newprot, ctx;
|
||||
int vr, vs, newprot, ctx, pte, *ptep;
|
||||
int pmeg;
|
||||
struct regmap *rp;
|
||||
struct segmap *sp;
|
||||
|
||||
@ -5164,15 +5209,24 @@ pmap_changeprot4_4c(pm, va, prot, flags)
|
||||
vs = VA_VSEG(va);
|
||||
rp = &pm->pm_regmap[vr];
|
||||
sp = &rp->rg_segmap[vs];
|
||||
ptep = &sp->sg_pte[VA_VPG(va)];
|
||||
|
||||
pmap_stats.ps_changeprots++;
|
||||
|
||||
/* update PTEs in software or hardware */
|
||||
if (sp->sg_pmeg == seginval) {
|
||||
int *pte = &sp->sg_pte[VA_VPG(va)];
|
||||
pte = *ptep;
|
||||
if (pte & PG_WIRED && (flags & PMAP_WIRED) == 0) {
|
||||
pte &= ~PG_WIRED;
|
||||
sp->sg_nwired--;
|
||||
} else if ((pte & PG_WIRED) == 0 && flags & PMAP_WIRED) {
|
||||
pte |= PG_WIRED;
|
||||
sp->sg_nwired++;
|
||||
}
|
||||
pte = (pte & ~PG_PROT) | newprot;
|
||||
/* Update S/W pte entry */
|
||||
*ptep = pte;
|
||||
|
||||
/* update in software */
|
||||
*pte = (*pte & ~PG_PROT) | newprot;
|
||||
} else {
|
||||
/* update PTEs in software or hardware */
|
||||
if ((pmeg = sp->sg_pmeg) != seginval) {
|
||||
/* update in hardware */
|
||||
ctx = getcontext4();
|
||||
if (CTX_USABLE(pm,rp)) {
|
||||
@ -5182,21 +5236,30 @@ pmap_changeprot4_4c(pm, va, prot, flags)
|
||||
* avoid stale protection bits in the cache tags.
|
||||
*/
|
||||
setcontext4(pm->pm_ctxnum);
|
||||
tpte = getpte4(va);
|
||||
if ((tpte & (PG_U|PG_NC|PG_TYPE)) == (PG_U|PG_OBMEM))
|
||||
pte = getpte4(va);
|
||||
if ((pte & (PG_U|PG_NC|PG_TYPE)) == (PG_U|PG_OBMEM))
|
||||
cache_flush_page(va, pm->pm_ctxnum);
|
||||
} else {
|
||||
setcontext4(0);
|
||||
/* XXX use per-cpu va? */
|
||||
if (HASSUN4_MMU3L)
|
||||
setregmap(0, tregion);
|
||||
setsegmap(0, sp->sg_pmeg);
|
||||
setsegmap(0, pmeg);
|
||||
va = VA_VPG(va) << PGSHIFT;
|
||||
tpte = getpte4(va);
|
||||
pte = getpte4(va);
|
||||
}
|
||||
tpte = (tpte & ~PG_PROT) | newprot;
|
||||
setpte4(va, tpte);
|
||||
pte = (pte & ~PG_PROT) | newprot;
|
||||
setpte4(va, pte);
|
||||
setcontext4(ctx);
|
||||
#ifdef DIAGNOSTIC
|
||||
if (sp->sg_nwired > sp->sg_npte || sp->sg_nwired < 0)
|
||||
panic("pmap_protect: pm %p, va %lx: nleft=%d, nwired=%d",
|
||||
pm, va, sp->sg_npte, sp->sg_nwired);
|
||||
#endif
|
||||
if (sp->sg_nwired == 0)
|
||||
mmu_pmeg_unlock(pmeg);
|
||||
else
|
||||
mmu_pmeg_lock(pmeg);
|
||||
}
|
||||
}
|
||||
|
||||
@ -5523,6 +5586,9 @@ pmap_enter4_4c(pm, va, pa, prot, flags)
|
||||
if (prot & VM_PROT_WRITE)
|
||||
pteproto |= PG_W;
|
||||
|
||||
if ((flags & PMAP_WIRED) != 0)
|
||||
pteproto |= PG_WIRED;
|
||||
|
||||
write_user_windows();
|
||||
ctx = getcontext4();
|
||||
if (pm == pmap_kernel())
|
||||
@ -5543,7 +5609,7 @@ pmap_enk4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
struct vm_page *pg;
|
||||
int pteproto;
|
||||
{
|
||||
int vr, vs, tpte, s, inmmu;
|
||||
int vr, vs, pte, s, inmmu;
|
||||
int *ptep;
|
||||
struct regmap *rp;
|
||||
struct segmap *sp;
|
||||
@ -5561,10 +5627,10 @@ pmap_enk4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
#endif
|
||||
|
||||
inmmu = sp->sg_pmeg != seginval;
|
||||
if ((tpte = *ptep) & PG_V) {
|
||||
if ((pte = *ptep) & PG_V) {
|
||||
|
||||
/* old mapping exists, and is of the same pa type */
|
||||
if ((tpte & (PG_PFNUM|PG_TYPE)) ==
|
||||
if ((pte & (PG_PFNUM|PG_TYPE)) ==
|
||||
(pteproto & (PG_PFNUM|PG_TYPE))) {
|
||||
/* just changing protection and/or wiring */
|
||||
pmap_changeprot4_4c(pm, va, prot, flags);
|
||||
@ -5572,7 +5638,7 @@ pmap_enk4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
return (0);
|
||||
}
|
||||
|
||||
if ((tpte & PG_TYPE) == PG_OBMEM) {
|
||||
if ((pte & PG_TYPE) == PG_OBMEM) {
|
||||
struct vm_page *opg;
|
||||
|
||||
/*
|
||||
@ -5580,13 +5646,15 @@ pmap_enk4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
* If old pa was managed, remove from pvlist.
|
||||
* If old page was cached, flush cache.
|
||||
*/
|
||||
if ((opg = pvhead4_4c(tpte)) != NULL)
|
||||
if ((opg = pvhead4_4c(pte)) != NULL)
|
||||
pv_unlink4_4c(opg, pm, va);
|
||||
if (inmmu && (tpte & PG_NC) == 0) {
|
||||
if (inmmu && (pte & PG_NC) == 0) {
|
||||
setcontext4(0); /* ??? */
|
||||
cache_flush_page(va, 0);
|
||||
}
|
||||
}
|
||||
if (pte & PG_WIRED)
|
||||
sp->sg_nwired--;
|
||||
} else {
|
||||
/* adding new entry */
|
||||
if (sp->sg_npte++ == 0) {
|
||||
@ -5610,15 +5678,22 @@ pmap_enk4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
|
||||
/* Update S/W page table */
|
||||
*ptep = pteproto;
|
||||
if (pteproto & PG_WIRED)
|
||||
sp->sg_nwired++;
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
if (sp->sg_nwired > sp->sg_npte || sp->sg_nwired < 0)
|
||||
panic("pmap_enk: pm %p, va %lx: nleft=%d, nwired=%d",
|
||||
pm, va, sp->sg_npte, sp->sg_nwired);
|
||||
#endif
|
||||
if (sp->sg_pmeg == seginval)
|
||||
mmu_pagein_seg(pm, sp, va, vr, vs,
|
||||
(flags & PMAP_WIRED) != 0 ? &segm_locked : &segm_lru);
|
||||
else if ((flags & PMAP_WIRED) != 0)
|
||||
(pteproto & PG_WIRED) != 0 ? &segm_locked : &segm_lru);
|
||||
else if ((pteproto & PG_WIRED) != 0)
|
||||
mmu_pmeg_lock(sp->sg_pmeg);
|
||||
|
||||
/* Update H/W page table */
|
||||
setpte4(va, pteproto);
|
||||
setpte4(va, pteproto & ~PG_MBZ);
|
||||
splx(s);
|
||||
return (0);
|
||||
}
|
||||
@ -5633,7 +5708,7 @@ pmap_enu4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
struct vm_page *pg;
|
||||
int pteproto;
|
||||
{
|
||||
int vr, vs, *pte, tpte, pmeg, s;
|
||||
int vr, vs, *ptep, pte, pmeg, s;
|
||||
int error = 0;
|
||||
struct regmap *rp;
|
||||
struct segmap *sp;
|
||||
@ -5692,14 +5767,14 @@ pmap_enu4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
|
||||
sp = &rp->rg_segmap[vs];
|
||||
|
||||
if ((pte = sp->sg_pte) == NULL) {
|
||||
if ((ptep = sp->sg_pte) == NULL) {
|
||||
/* definitely a new mapping */
|
||||
int size = NPTESG * sizeof *pte;
|
||||
int size = NPTESG * sizeof *ptep;
|
||||
int mflag = PR_NOWAIT;
|
||||
|
||||
sretry:
|
||||
pte = (int *)pool_get(&pte_pool, mflag);
|
||||
if (pte == NULL) {
|
||||
ptep = (int *)pool_get(&pte_pool, mflag);
|
||||
if (ptep == NULL) {
|
||||
if ((flags & PMAP_CANFAIL) != 0) {
|
||||
error = ENOMEM;
|
||||
goto out;
|
||||
@ -5713,16 +5788,16 @@ pmap_enu4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
if (sp->sg_pmeg != seginval)
|
||||
panic("pmap_enter: new ptes, but not seginval");
|
||||
#endif
|
||||
qzero((caddr_t)pte, size);
|
||||
sp->sg_pte = pte;
|
||||
qzero((caddr_t)ptep, size);
|
||||
sp->sg_pte = ptep;
|
||||
sp->sg_npte = 1;
|
||||
rp->rg_nsegmap++;
|
||||
} else {
|
||||
/* might be a change: fetch old pte */
|
||||
tpte = pte[VA_VPG(va)];
|
||||
if (tpte & PG_V) {
|
||||
pte = ptep[VA_VPG(va)];
|
||||
if (pte & PG_V) {
|
||||
/* old mapping exists, and is of the same pa type */
|
||||
if ((tpte & (PG_PFNUM|PG_TYPE)) ==
|
||||
if ((pte & (PG_PFNUM|PG_TYPE)) ==
|
||||
(pteproto & (PG_PFNUM|PG_TYPE))) {
|
||||
/* just changing prot and/or wiring */
|
||||
/* caller should call this directly: */
|
||||
@ -5744,9 +5819,9 @@ pmap_enu4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
"va(0x%lx)=>pa entry\n",
|
||||
curproc->p_comm, curproc->p_pid, va);
|
||||
#endif
|
||||
if ((tpte & PG_TYPE) == PG_OBMEM) {
|
||||
if ((pte & PG_TYPE) == PG_OBMEM) {
|
||||
struct vm_page *opg;
|
||||
if ((opg = pvhead4_4c(tpte)) != NULL)
|
||||
if ((opg = pvhead4_4c(pte)) != NULL)
|
||||
pv_unlink4_4c(opg, pm, va);
|
||||
if (CACHEINFO.c_vactype != VAC_NONE &&
|
||||
(pmeg = sp->sg_pmeg) != seginval) {
|
||||
@ -5763,6 +5838,8 @@ pmap_enu4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
cache_flush_page(va, pm->pm_ctxnum);
|
||||
}
|
||||
}
|
||||
if (pte & PG_WIRED)
|
||||
sp->sg_nwired--;
|
||||
} else {
|
||||
/* adding new entry */
|
||||
sp->sg_npte++;
|
||||
@ -5778,11 +5855,20 @@ pmap_enu4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
if (pg != NULL)
|
||||
pteproto |= pv_link4_4c(pg, pm, va, pteproto & PG_NC);
|
||||
|
||||
/*
|
||||
* Update hardware & software PTEs.
|
||||
*/
|
||||
/* Update S/W page table */
|
||||
ptep += VA_VPG(va);
|
||||
*ptep = pteproto;
|
||||
if (pteproto & PG_WIRED)
|
||||
sp->sg_nwired++;
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
if (sp->sg_nwired > sp->sg_npte || sp->sg_nwired < 0)
|
||||
panic("pmap_enu: pm %p, va %lx: nleft=%d, nwired=%d",
|
||||
pm, va, sp->sg_npte, sp->sg_nwired);
|
||||
#endif
|
||||
|
||||
if ((pmeg = sp->sg_pmeg) != seginval) {
|
||||
/* ptes are in hardware */
|
||||
/* Update H/W page table */
|
||||
if (CTX_USABLE(pm,rp))
|
||||
setcontext4(pm->pm_ctxnum);
|
||||
else {
|
||||
@ -5792,11 +5878,8 @@ pmap_enu4_4c(pm, va, prot, flags, pg, pteproto)
|
||||
setsegmap(0, pmeg);
|
||||
va = VA_VPG(va) << PGSHIFT;
|
||||
}
|
||||
setpte4(va, pteproto);
|
||||
setpte4(va, pteproto & ~PG_MBZ);
|
||||
}
|
||||
/* update software copy */
|
||||
pte += VA_VPG(va);
|
||||
*pte = pteproto;
|
||||
|
||||
out:
|
||||
splx(s);
|
||||
@ -5828,6 +5911,11 @@ pmap_kenter_pa4_4c(va, pa, prot)
|
||||
sp = &rp->rg_segmap[vs];
|
||||
ptep = &sp->sg_pte[VA_VPG(va)];
|
||||
|
||||
if (lockit) {
|
||||
pteproto |= PG_WIRED;
|
||||
sp->sg_nwired++;
|
||||
}
|
||||
|
||||
KASSERT((*ptep & PG_V) == 0);
|
||||
|
||||
s = splvm();
|
||||
@ -5851,6 +5939,12 @@ pmap_kenter_pa4_4c(va, pa, prot)
|
||||
/* Update S/W page table */
|
||||
*ptep = pteproto;
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
if (sp->sg_nwired > sp->sg_npte || sp->sg_nwired < 0)
|
||||
panic("pmap_kenter: pm %p, va %lx: nleft=%d, nwired=%d",
|
||||
pm, va, sp->sg_npte, sp->sg_nwired);
|
||||
#endif
|
||||
|
||||
if (sp->sg_pmeg == seginval) {
|
||||
mmu_pagein_seg(pm, sp, va, vr, vs,
|
||||
lockit ? &segm_locked : &segm_lru);
|
||||
@ -5858,7 +5952,7 @@ pmap_kenter_pa4_4c(va, pa, prot)
|
||||
mmu_pmeg_lock(sp->sg_pmeg);
|
||||
|
||||
/* Update H/W page table */
|
||||
setpte4(va, pteproto);
|
||||
setpte4(va, pteproto & ~PG_MBZ);
|
||||
splx(s);
|
||||
}
|
||||
|
||||
@ -5938,6 +6032,7 @@ pmap_kremove4_4c(va, len)
|
||||
continue;
|
||||
pmeg = sp->sg_pmeg;
|
||||
inmmu = (pmeg != seginval);
|
||||
ptep = &sp->sg_pte[VA_VPG(va)];
|
||||
|
||||
/* decide how to flush cache */
|
||||
npg = (nva - va) >> PGSHIFT;
|
||||
@ -5955,7 +6050,6 @@ pmap_kremove4_4c(va, len)
|
||||
perpage = (CACHEINFO.c_vactype != VAC_NONE);
|
||||
}
|
||||
|
||||
ptep = sp->sg_pte + VA_VPG(va);
|
||||
for (; va < nva; va += NBPG, ptep++) {
|
||||
pte = *ptep;
|
||||
if (inmmu)
|
||||
@ -5978,13 +6072,26 @@ pmap_kremove4_4c(va, len)
|
||||
panic("pmap_kremove: too many PTEs in segment; "
|
||||
"va 0x%lx; endva 0x%lx", va, endva);
|
||||
#endif
|
||||
if (pte & PG_WIRED)
|
||||
sp->sg_nwired--;
|
||||
|
||||
if (inmmu)
|
||||
setpte4(va, 0);
|
||||
*ptep = 0;
|
||||
}
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
if (sp->sg_nwired > nleft || sp->sg_nwired < 0)
|
||||
panic("pmap_kremove: pm %p, va %lx: nleft=%d, nwired=%d",
|
||||
pm, va, nleft, sp->sg_nwired);
|
||||
#endif
|
||||
|
||||
if ((sp->sg_npte = nleft) == 0)
|
||||
pgt_lvl23_remove4_4c(pm, rp, sp, vr, vs);
|
||||
else if (sp->sg_nwired == 0) {
|
||||
if (sp->sg_pmeg != seginval)
|
||||
mmu_pmeg_unlock(sp->sg_pmeg);
|
||||
}
|
||||
}
|
||||
simple_unlock(&pm->pm_lock);
|
||||
setcontext4(ctx);
|
||||
@ -6551,14 +6658,40 @@ pmap_kprotect4m(vaddr_t va, vsize_t size, vm_prot_t prot)
|
||||
/*
|
||||
* Clear the wiring attribute for a map/virtual-address pair.
|
||||
*/
|
||||
int printunwire=0;
|
||||
/* ARGSUSED */
|
||||
void
|
||||
pmap_unwire(pm, va)
|
||||
struct pmap *pm;
|
||||
vaddr_t va;
|
||||
{
|
||||
int vr, vs, pte, *ptep;
|
||||
struct regmap *rp;
|
||||
struct segmap *sp;
|
||||
|
||||
pmap_stats.ps_useless_changewire++;
|
||||
vr = VA_VREG(va);
|
||||
vs = VA_VSEG(va);
|
||||
rp = &pm->pm_regmap[vr];
|
||||
sp = &rp->rg_segmap[vs];
|
||||
ptep = &sp->sg_pte[VA_VPG(va)];
|
||||
pte = *ptep;
|
||||
if ((pte & PG_WIRED) == 0) {
|
||||
pmap_stats.ps_useless_changewire++;
|
||||
return;
|
||||
}
|
||||
if (printunwire) printf("pmap_unwire: pm %p, va %lx\n", pm, va);
|
||||
|
||||
pte &= ~PG_WIRED;
|
||||
*ptep = pte;
|
||||
if (--sp->sg_nwired <= 0) {
|
||||
#ifdef DIAGNOSTIC
|
||||
if (sp->sg_nwired > sp->sg_npte || sp->sg_nwired < 0)
|
||||
panic("pmap_unwire: pm %p, va %lx: nleft=%d, nwired=%d",
|
||||
pm, va, sp->sg_npte, sp->sg_nwired);
|
||||
#endif
|
||||
if (sp->sg_pmeg != seginval)
|
||||
mmu_pmeg_unlock(sp->sg_pmeg);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
@ -6698,8 +6831,8 @@ pmap_copy(dst_pmap, src_pmap, dst_addr, len, src_addr)
|
||||
vaddr_t src_addr;
|
||||
{
|
||||
#if notyet
|
||||
struct regmap *rm;
|
||||
struct segmap *sm;
|
||||
struct regmap *rp;
|
||||
struct segmap *sp;
|
||||
|
||||
if (pmap_copy_disabled)
|
||||
return;
|
||||
@ -6720,17 +6853,17 @@ pmap_copy(dst_pmap, src_pmap, dst_addr, len, src_addr)
|
||||
npg = len >> PGSHIFT;
|
||||
for (i = 0; i < npg; i++) {
|
||||
tlb_flush_page(src_addr, getcontext4m(), PMAP_CPUSET(src_map));
|
||||
if ((rm = src_pmap->pm_regmap) == NULL)
|
||||
if ((rp = src_pmap->pm_regmap) == NULL)
|
||||
continue;
|
||||
rm += VA_VREG(src_addr);
|
||||
rp += VA_VREG(src_addr);
|
||||
|
||||
if ((sm = rm->rg_segmap) == NULL)
|
||||
if ((sp = rp->rg_segmap) == NULL)
|
||||
continue;
|
||||
sm += VA_VSEG(src_addr);
|
||||
if (sm->sg_npte == 0)
|
||||
sp += VA_VSEG(src_addr);
|
||||
if (sp->sg_npte == 0)
|
||||
continue;
|
||||
|
||||
pte = sm->sg_pte[VA_SUN4M_VPG(src_addr)];
|
||||
pte = sp->sg_pte[VA_SUN4M_VPG(src_addr)];
|
||||
if ((pte & SRMMU_TETYPE) != SRMMU_TEPTE)
|
||||
continue;
|
||||
|
||||
@ -7949,3 +8082,57 @@ void print_fe_map(void)
|
||||
printf("done\n");
|
||||
}
|
||||
#endif /* EXTREME_DEBUG */
|
||||
|
||||
#ifdef DDB
|
||||
int pmap_dump(struct pmap *pm);
|
||||
int pmap_dump(struct pmap *pm)
|
||||
{
|
||||
int startvr, endvr, vr, vs, i, n;
|
||||
struct regmap *rp;
|
||||
struct segmap *sp;
|
||||
|
||||
if (pm == NULL)
|
||||
pm = pmap_kernel();
|
||||
|
||||
if (pm == pmap_kernel()) {
|
||||
startvr = NUREG;
|
||||
endvr = 256;
|
||||
} else {
|
||||
startvr = 0;
|
||||
endvr = NUREG;
|
||||
}
|
||||
|
||||
for (vr = startvr; vr < endvr; vr++) {
|
||||
rp = &pm->pm_regmap[vr];
|
||||
if (rp->rg_nsegmap == 0)
|
||||
continue;
|
||||
printf("vr %d: %d segments", vr, rp->rg_nsegmap);
|
||||
if (rp->rg_segmap == NULL) {
|
||||
printf("[no segments]\n");
|
||||
continue;
|
||||
}
|
||||
for (vs = 0; vs < NSEGRG; vs++) {
|
||||
sp = &rp->rg_segmap[vs];
|
||||
if (sp->sg_npte == 0)
|
||||
continue;
|
||||
if ((vs & 3) == 0)
|
||||
printf("\n ");
|
||||
printf(" %d: n %d w %d p %d,", vs,
|
||||
sp->sg_npte, sp->sg_nwired, sp->sg_pmeg);
|
||||
if (sp->sg_pte == NULL) {
|
||||
printf("[no ptes]");
|
||||
continue;
|
||||
}
|
||||
for (n = 0, i = 0; i < NPTESG; i++) {
|
||||
if (sp->sg_pte[i] & PG_WIRED)
|
||||
n++;
|
||||
}
|
||||
if (n != sp->sg_nwired)
|
||||
printf("[wired count %d]", n);
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
#endif /* DDB */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user