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Implement workaround for IBM405 Errata 77 (aka CPU_210), where

Browse Source 
interrupted stwcx. may errantly write data to memory:

    https://elinux.org/images/1/1d/Ppc405gp-errata.pdf

This is because stwcx. is split into two pieces in the pipeline.

We need to
(1) insert dcbt before every stwcx. instruction, as well as
(2) insert sync before every rfi/rfci instruction.

It is unclear which processors are affected, but according to Linux,
all 405-based cores up until 405GPR and 405EP are affected:

    https://github.com/torvalds/linux/blob/master/arch/powerpc/platforms/40x/Kconfig#L140

For kernel, this workaround can be restricted to affected processors.
However, for kernel modules and userland, we have to enable it for all
32bit powerpc archs in order to share common binaries as before.

Proposed on port-powerpc:

    http://mail-index.netbsd.org/port-powerpc/2020/02/21/msg003583.html
This commit is contained in:
rin 2020-03-01 23:23:36 +00:00
parent 0d1a142685
commit fd255ae543
14 changed files with 82 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
common/lib/libc/arch/powerpc/atomic/atomic_cas.S
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@ -1,4 +1,4 @@
/* $NetBSD: atomic_cas.S,v 1.8 2014/03/07 07:17:54 matt Exp $ */
/* $NetBSD: atomic_cas.S,v 1.9 2020/03/01 23:23:36 rin Exp $ */
/*-
* Copyright (c) 2007, 2008 The NetBSD Foundation, Inc.
@ -31,7 +31,7 @@
#include "atomic_op_asm.h"
__RCSID("$NetBSD: atomic_cas.S,v 1.8 2014/03/07 07:17:54 matt Exp $")
__RCSID("$NetBSD: atomic_cas.S,v 1.9 2020/03/01 23:23:36 rin Exp $")
.text
ENTRY(_atomic_cas_32)
@ -39,6 +39,7 @@ ENTRY(_atomic_cas_32)
1: lwarx %r3,0,%r10
cmpw %r3,%r4
bnelr-
IBM405_ERRATA77_DCBT(0,%r10)
stwcx. %r5,0,%r10
beqlr+
b 1b

4
common/lib/libc/arch/powerpc/atomic/atomic_op_asm.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: atomic_op_asm.h,v 1.6 2014/03/07 07:17:54 matt Exp $ */
/* $NetBSD: atomic_op_asm.h,v 1.7 2020/03/01 23:23:36 rin Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@ -49,6 +49,7 @@ ENTRY(_atomic_##op##_32) ; \
mr %r10,%r3 ; \
1: lwarx %r3,0,%r10 ; \
insn %r5,%r3,arg ; \
IBM405_ERRATA77_DCBT(0,%r10) ; \
stwcx. %r5,0,%r10 ; \
beqlr+ ; \
b 1b ; \
@ -71,6 +72,7 @@ ENTRY(_atomic_##op##_32_nv) ; \
mr %r10,%r3 ; \
1: lwarx %r3,0,%r10 ; \
insn %r3,%r3,arg ; \
IBM405_ERRATA77_DCBT(0,%r10) ; \
stwcx. %r3,0,%r10 ; \
beqlr+ ; \
b 1b ; \

5
common/lib/libc/arch/powerpc/atomic/atomic_swap.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: atomic_swap.S,v 1.7 2014/03/07 07:17:54 matt Exp $ */
/* $NetBSD: atomic_swap.S,v 1.8 2020/03/01 23:23:36 rin Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@ -31,12 +31,13 @@
#include "atomic_op_asm.h"
__RCSID("$NetBSD: atomic_swap.S,v 1.7 2014/03/07 07:17:54 matt Exp $")
__RCSID("$NetBSD: atomic_swap.S,v 1.8 2020/03/01 23:23:36 rin Exp $")
.text
ENTRY(_atomic_swap_32)
mr %r10,%r3
1: lwarx %r3,0,%r10
IBM405_ERRATA77_DCBT(0,%r10)
stwcx. %r4,0,%r10
beqlr+
b 1b

4
sys/arch/evbppc/conf/std.obs200
View File

@ -1,9 +1,11 @@
# $NetBSD: std.obs200,v 1.4 2010/03/18 14:15:38 kiyohara Exp $
# $NetBSD: std.obs200,v 1.5 2020/03/01 23:23:36 rin Exp $
#
# Standard/required options for obs200
include "arch/evbppc/conf/std.obs405"
options IBM405_ERRATA77
makeoptions PRDCTTYPE="obs200"
makeoptions TEXTADDR=0x450000
options KERNBASE=0x450000

4
sys/arch/evbppc/conf/std.obs266
View File

@ -1,9 +1,11 @@
# $NetBSD: std.obs266,v 1.2 2011/04/04 19:55:16 dyoung Exp $
# $NetBSD: std.obs266,v 1.3 2020/03/01 23:23:36 rin Exp $
#
# Standard/required options for obs266.
include "arch/evbppc/conf/std.obs405"
options IBM405_ERRATA77
makeoptions PRDCTTYPE="obs266"
makeoptions TEXTADDR=0x25000
options KERNBASE=0x25000

6
sys/arch/evbppc/conf/std.virtex
View File

@ -1,4 +1,4 @@
# $NetBSD: std.virtex,v 1.3 2011/06/20 17:44:33 matt Exp $
# $NetBSD: std.virtex,v 1.4 2020/03/01 23:23:36 rin Exp $
#
# Standard/required options for NetBSD/virtex.
@ -8,6 +8,10 @@ include "conf/std" # MI standard options
# standard ("mandatory") kernel options.
options PPC_IBM4XX # IBM 40x family
# XXX According to Linux, 405D5 (Virtex-II Pro) is affected, whereas
# XXX 405F6 (Virtex-4) is not.
options IBM405_ERRATA77
# Executable support:
options EXEC_ELF32 # (native) ELF32 binary support
options EXEC_AOUT # (native) a.out binary support (deprecated)

4
sys/arch/evbppc/conf/std.walnut
View File

@ -1,4 +1,4 @@
# $NetBSD: std.walnut,v 1.8 2011/06/22 18:06:32 matt Exp $
# $NetBSD: std.walnut,v 1.9 2020/03/01 23:23:36 rin Exp $
#
# Standard/required options for NetBSD/walnut.
@ -8,6 +8,8 @@ include "conf/std" # MI standard options
# standard ("mandatory") kernel options.
options PPC_IBM4XX # IBM 40x family
options IBM405_ERRATA77
# Executable support:
options EXEC_ELF32 # (native) ELF32 binary support
options EXEC_AOUT # (native) a.out binary support (deprecated)

4
sys/arch/powerpc/ibm4xx/4xx_trap_subr.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: 4xx_trap_subr.S,v 1.7 2011/05/19 07:51:50 kiyohara Exp $ */
/* $NetBSD: 4xx_trap_subr.S,v 1.8 2020/03/01 23:23:36 rin Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -55,10 +55,12 @@ _C_LABEL(pitfitwdog):
_C_LABEL(pitfitwdogsize) = .-_C_LABEL(pitfitwdog)
pithandler:
IBM405_ERRATA77_SYNC
rfi
ba . /* Protect against prefetch */
wdoghandler:
IBM405_ERRATA77_SYNC
rfi
ba . /* Protect against prefetch */

4
sys/arch/powerpc/ibm4xx/trap_subr.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: trap_subr.S,v 1.27 2018/07/15 05:16:43 maxv Exp $ */
/* $NetBSD: trap_subr.S,v 1.28 2020/03/01 23:23:36 rin Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -334,6 +334,7 @@ intrleave_to_kernel:
mtpid %r31
mfsprg3 %r31
mfsprg2 %r30
IBM405_ERRATA77_SYNC
rfi
ba . /* Protect against prefetch */
@ -375,6 +376,7 @@ intrleave_to_user:
mtpid %r31
mfsprg3 %r31
mfsprg2 %r30
IBM405_ERRATA77_SYNC
rfi
ba . /* Protect against prefetch */

18
sys/arch/powerpc/include/asm.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: asm.h,v 1.48 2015/01/12 02:32:33 dennis Exp $ */
/* $NetBSD: asm.h,v 1.49 2020/03/01 23:23:36 rin Exp $ */
/*
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
@ -432,4 +432,20 @@ y: .quad .##y,.TOC.@tocbase,0; \
.endm
#endif /* _LOCORE */
#if defined(IBM405_ERRATA77) || \
((defined(_MODULE) || !defined(_KERNEL)) && !defined(__LP64__))
/*
* Workaround for IBM405 Errata 77 (CPU_210): interrupted stwcx. may
* errantly write data to memory
*
* (1) Insert dcbt before every stwcx. instruction
* (2) Insert sync before every rfi/rfci instruction
*/
#define IBM405_ERRATA77_DCBT(ra, rb) dcbt ra,rb
#define IBM405_ERRATA77_SYNC sync
#else
#define IBM405_ERRATA77_DCBT(ra, rb) /* nothing */
#define IBM405_ERRATA77_SYNC /* nothing */
#endif
#endif /* !_PPC_ASM_H_ */

21
sys/arch/powerpc/include/lock.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: lock.h,v 1.14 2019/11/29 20:05:59 riastradh Exp $ */
/* $NetBSD: lock.h,v 1.15 2020/03/01 23:23:36 rin Exp $ */
/*-
* Copyright (c) 2000, 2007 The NetBSD Foundation, Inc.
@ -80,7 +80,11 @@ __cpu_simple_lock(__cpu_simple_lock_t *alp)
2: lwzx %0,0,%1 \n\
cmpwi %0,%2 \n\
beq+ 1b \n\
b 2b \n\
b 2b \n"
#ifdef IBM405_ERRATA77
"dcbt 0,%1 \n"
#endif
" \
3: stwcx. %3,0,%1 \n\
bne- 1b \n\
isync \n\
@ -99,9 +103,16 @@ __cpu_simple_lock_try(__cpu_simple_lock_t *alp)
\n\
1: lwarx %0,0,%1 \n\
cmpwi %0,%2 \n\
bne 2f \n\
stwcx. %3,0,%1 \n\
bne- 1b \n\
bne 2f \n"
#ifdef IBM405_ERRATA77
"dcbt 0,%1 \n"
#endif
"stwcx. %3,0,%1 \n\
bne- 1b \n"
#ifdef IBM405_ERRATA77
"dcbt 0,%4 \n"
#endif
" \
2: stwcx. %3,0,%4 \n\
isync \n\
\n"

8
sys/arch/powerpc/powerpc/lock_stubs.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: lock_stubs.S,v 1.11 2020/01/21 04:30:14 thorpej Exp $ */
/* $NetBSD: lock_stubs.S,v 1.12 2020/03/01 23:23:36 rin Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@ -55,6 +55,7 @@ ENTRY(_lock_cas)
lptrarx %r10,0,%r3
cmpptr %r10,%r4
bne- 2f
IBM405_ERRATA77_DCBT(0,%r3)
stptrcx. %r5,0,%r3
bne- 1b
SYNC
@ -73,6 +74,7 @@ ENTRY(mutex_enter)
lptrarx %r10,0,%r3
cmpptri %r10,0
bne- 2f
IBM405_ERRATA77_DCBT(0,%r3)
stptrcx. %r13,0,%r3
bne- 1b
ISYNC
@ -90,6 +92,7 @@ ENTRY(mutex_exit)
lptrarx %r10,0,%r3
cmpptr %r10,%r13
bne- 2f
IBM405_ERRATA77_DCBT(0,%r3)
stptrcx. %r7,0,%r3
bne- 1b
blr
@ -125,6 +128,7 @@ ENTRY(rw_enter)
2: lptrarx %r10,0,%r3
cmpptr %r10,%r9
bne- 3f
IBM405_ERRATA77_DCBT(0,%r3)
stptrcx. %r7,0,%r3
bne- 2b
ISYNC
@ -150,6 +154,7 @@ ENTRY(rw_tryenter)
2: lptrarx %r10,0,%r3
cmpptr %r10,%r9
bne- 3f
IBM405_ERRATA77_DCBT(0,%r3)
stptrcx. %r7,0,%r3
bne- 2b
@ -181,6 +186,7 @@ ENTRY(rw_exit)
2: lptrarx %r10,0,%r3
cmpptr %r10,%r9
bne- 3f
IBM405_ERRATA77_DCBT(0,%r3)
stptrcx. %r7,0,%r3
bne- 2b

6
sys/arch/powerpc/powerpc/locore_subr.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore_subr.S,v 1.60 2020/02/25 00:42:12 rin Exp $ */
/* $NetBSD: locore_subr.S,v 1.61 2020/03/01 23:23:36 rin Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@ -281,6 +281,7 @@ ENTRY(cpu_switchto)
*/
ldreg %r31,CFRAME_R31(%r1) /* restore saved registers */
ldreg %r30,CFRAME_R30(%r1)
IBM405_ERRATA77_DCBT(0,%r1)
stwcx. %r1,0,%r1 /* clear reservation */
#if 1
addi %r1,%r1,CALLFRAMELEN
@ -320,6 +321,7 @@ _ENTRY(softint_cleanup)
mtmsr %r0
isync
#endif
IBM405_ERRATA77_DCBT(0,%r1)
stwcx. %r1,0,%r1 /* clear reservation */
addi %r1, %r1, CALLFRAMELEN
ldreg %r0, CFRAME_LR(%r1)
@ -471,6 +473,7 @@ _ENTRY(softint_fast_dispatch)
ldreg %r29,SFRAME_R29(%r1) /* R29 */
ldreg %r31,SFRAMELEN+CFRAME_R31(%r1) /* restore saved registers */
ldreg %r30,SFRAMELEN+CFRAME_R30(%r1)
IBM405_ERRATA77_DCBT(0,%r1)
stwcx. %r1,0,%r1 /* clear reservation */
addi %r1,%r1,SFRAMELEN+2*CALLFRAMELEN /* remove switch & callframes */
#endif
@ -579,6 +582,7 @@ ENTRY(do_ucas_32)
lwarx %r10,0,%r3
cmpw %r10, %r4
bne 2f
IBM405_ERRATA77_DCBT(0,%r3)
stwcx. %r5,0,%r3
bne 1b
mr %r5,%r10

9
sys/arch/powerpc/powerpc/trap_subr.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: trap_subr.S,v 1.80 2018/07/15 05:16:44 maxv Exp $ */
/* $NetBSD: trap_subr.S,v 1.81 2020/03/01 23:23:36 rin Exp $ */
/*
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
@ -315,6 +315,7 @@ dsitrap_fix_dbat7:
ldreg %r30,(CI_DISISAVE+CPUSAVE_R30)(%r1) /* restore r30 */
ldreg %r31,(CI_DISISAVE+CPUSAVE_R31)(%r1) /* restore r31 */
mfsprg1 %r1
IBM405_ERRATA77_SYNC
RFI /* return to trapped code */
1:
#endif /* !PPC_MPC8XX */
@ -387,6 +388,7 @@ _C_LABEL(dsi601trap):
ldreg %r30,(CI_DISISAVE+CPUSAVE_R30)(%r1) /* restore r30 */
ldreg %r31,(CI_DISISAVE+CPUSAVE_R31)(%r1) /* restore r31 */
mfsprg1 %r1
IBM405_ERRATA77_SYNC
RFI /* return to trapped code */
1:
mflr %r28 /* save LR */
@ -503,6 +505,7 @@ _C_LABEL(tlbimiss):
srwi %r1,%r1,8 /* get byte 7 of pte */
tlbli %r0 /* load the itlb */
stb %r1,6(%r2) /* update page table */
IBM405_ERRATA77_SYNC
RFI
3: /* not found in pteg */
@ -562,6 +565,7 @@ _C_LABEL(tlbdlmiss):
srwi %r1,%r1,8 /* get byte 7 of pte */
tlbld %r0 /* load the dtlb */
stb %r1,6(%r2) /* update page table */
IBM405_ERRATA77_SYNC
RFI
3: /* not found in pteg */
@ -618,6 +622,7 @@ _C_LABEL(tlbdsmiss):
mtcrf 0x80,%r3 /* and restore */
mtspr SPR_RPA,%r1 /* set the pte */
tlbld %r0 /* load the dtlb */
IBM405_ERRATA77_SYNC
RFI
3: /* not found in pteg */
@ -991,6 +996,7 @@ trapleave:
FRAME_RESTORE_CALLEE
intrleave:
FRAME_LEAVE(CI_TEMPSAVE)
IBM405_ERRATA77_SYNC
RFI
/*
@ -1214,6 +1220,7 @@ ddbtrap:
beq trapagain
FRAME_RESTORE_CALLEE
FRAME_LEAVE(CI_DDBSAVE)
IBM405_ERRATA77_SYNC
RFI
#endif /* DDB || KGDB */