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Add ECC support for the packet buffer. Only 82571 and I21[78] support ECC.

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This commit is contained in:
msaitoh 2013-06-19 10:38:51 +00:00
parent f96c92e089
commit fce172c5e6
2 changed files with 69 additions and 3 deletions
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24
sys/dev/pci/if_wm.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_wm.c,v 1.256 2013/06/19 10:27:08 msaitoh Exp $ */
/* $NetBSD: if_wm.c,v 1.257 2013/06/19 10:38:51 msaitoh Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@ -76,7 +76,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.256 2013/06/19 10:27:08 msaitoh Exp $");
__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.257 2013/06/19 10:38:51 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -4799,6 +4799,26 @@ wm_init(struct ifnet *ifp)
/* Set the receive filter. */
wm_set_filter(sc);
/* Enable ECC */
switch (sc->sc_type) {
case WM_T_82571:
reg = CSR_READ(sc, WMREG_PBA_ECC);
reg |= PBA_ECC_CORR_EN;
CSR_WRITE(sc, WMREG_PBA_ECC, reg);
break;
case WM_T_PCH_LPT:
reg = CSR_READ(sc, WMREG_PBECCSTS);
reg |= PBECCSTS_UNCORR_ECC_ENABLE;
CSR_WRITE(sc, WMREG_PBECCSTS, reg);
reg = CSR_READ(sc, WMREG_CTRL);
reg |= CTRL_MEHE;
CSR_WRITE(sc, WMREG_CTRL, reg);
break;
default:
break;
}
/* On 575 and later set RDT only if RX enabled */
if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
for (i = 0; i < WM_NRXDESC; i++)

48
sys/dev/pci/if_wmreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_wmreg.h,v 1.52 2013/04/21 19:59:41 msaitoh Exp $ */
/* $NetBSD: if_wmreg.h,v 1.53 2013/06/19 10:38:51 msaitoh Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@ -35,6 +35,39 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
Copyright (c) 2001-2012, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/*
* Register description for the Intel i82542 (``Wiseman''),
* i82543 (``Livengood''), and i82544 (``Cordova'') Gigabit
@ -200,6 +233,7 @@ struct livengood_tcpip_ctxdesc {
#define CTRL_SWDPIO_SHIFT 22
#define CTRL_SWDPIO_MASK 0x0f
#define CTRL_SWDPIO(x) (1U << (CTRL_SWDPIO_SHIFT + (x)))
#define CTRL_MEHE (1U << 17) /* Memory Error Handling Enable(I217)*/
#define CTRL_RST (1U << 26) /* device reset */
#define CTRL_RFCE (1U << 27) /* Rx flow control enable */
#define CTRL_TFCE (1U << 28) /* Tx flow control enable */
@ -692,6 +726,11 @@ struct livengood_tcpip_ctxdesc {
#define WMREG_PBS 0x1008 /* Packet Buffer Size (ICH) */
#define WMREG_PBECCSTS 0x100c /* Packet Buffer ECC Status (PCH_LPT) */
#define PBECCSTS_CORR_ERR_CNT_MASK 0x000000ff
#define PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000ff00
#define PBECCSTS_UNCORR_ECC_ENABLE 0x00010000
#define WMREG_EEMNGCTL 0x1010 /* MNG EEprom Control */
#define EEMNGCTL_CFGDONE_0 0x040000 /* MNG config cycle done */
#define EEMNGCTL_CFGDONE_1 0x080000 /* 2nd port */
@ -710,6 +749,13 @@ struct livengood_tcpip_ctxdesc {
#define MAX_SGMII_PHY_REG_ADDR 255
#define I2CCMD_PHY_TIMEOUT 200
#define WMREG_PBA_ECC 0x01100 /* PBA ECC */
#define PBA_ECC_COUNTER_MASK 0xfff00000 /* ECC counter mask */
#define PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */
#define PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */
#define PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
#define PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */
#define WMREG_EICS 0x01520 /* Ext. Interrupt Cause Set - WO */
#define WMREG_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
#define WMREG_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */