Implement sparse bus space support.
This commit is contained in:
tsubai
parent
5ff97947fe
commit
fbeabd992c
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@ -1,5 +1,4 @@
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/* $NetBSD: bus.h,v 1.5 1998/10/03 21:24:00 thorpej Exp $ */
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/* $OpenBSD: bus.h,v 1.1 1997/10/13 10:53:42 pefo Exp $ */
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/* $NetBSD: bus.h,v 1.6 1998/12/06 15:39:12 tsubai Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
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@ -69,61 +68,36 @@
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1997 Per Fogelstrom. All rights reserved.
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* Copyright (c) 1996 Niklas Hallqvist. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Christopher G. Demetriou
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MACPPC_BUS_H_
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#define _MACPPC_BUS_H_
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#include <machine/pio.h>
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/*
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* Values for the PowerMac bus space tag, not to be used directly by MI code.
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*/
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/* #define MACPPC_BUS_REVERSE 1 */
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/*
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* Bus access types.
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*/
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typedef u_int32_t bus_addr_t;
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typedef u_int32_t bus_size_t;
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typedef u_int32_t bus_space_handle_t;
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typedef u_int32_t bus_space_tag_t;
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/*
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* Access methods for bus resources
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* Values for the macppc bus space tag, not to be used directly by MI code.
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*/
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#define __BUS_SPACE_HAS_STREAM_METHODS
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#define MACPPC_BUS_ADDR_MASK 0xfffff000
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#define MACPPC_BUS_STRIDE_MASK 0x0000000f
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#define macppc_make_bus_space_tag(addr, stride) \
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(((addr) & MACPPC_BUS_ADDR_MASK) | (stride))
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#define __BA(t, h, o) ((void *)((h) + ((o) << ((t) & MACPPC_BUS_STRIDE_MASK))))
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/*
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* Bus address and size types
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*/
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typedef u_int32_t bus_addr_t;
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typedef u_int32_t bus_size_t;
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/*
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* Access methods for bus resources and address space.
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*/
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typedef u_int32_t bus_space_tag_t;
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typedef u_int32_t bus_space_handle_t;
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/*
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* int bus_space_map __P((bus_space_tag_t t, bus_addr_t addr,
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* bus_size_t size, int flags, bus_space_handle_t *bshp));
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@ -134,10 +108,24 @@ typedef u_int32_t bus_space_tag_t;
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#define BUS_SPACE_MAP_CACHEABLE 0x01
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#define BUS_SPACE_MAP_LINEAR 0x02
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#define bus_space_map(t, addr, size, cacheable, bshp) \
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((*(bshp) = (bus_space_handle_t)mapiodev(((u_int)(t)) + (addr), size)), 0)
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extern void * mapiodev __P((paddr_t, psize_t));
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static __inline int
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bus_space_map(t, addr, size, flags, bshp)
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bus_space_tag_t t;
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bus_addr_t addr;
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bus_size_t size;
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int flags;
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bus_space_handle_t *bshp;
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{
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paddr_t base = t & MACPPC_BUS_ADDR_MASK;
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int stride = t & MACPPC_BUS_STRIDE_MASK;
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*bshp = (bus_space_handle_t)
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mapiodev(base + (addr << stride), size << stride);
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return 0;
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}
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/*
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* int bus_space_unmap __P((bus_space_tag_t t,
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* bus_space_handle_t bsh, bus_size_t size));
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@ -156,7 +144,7 @@ extern void * mapiodev __P((paddr_t, psize_t));
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*/
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#define bus_space_subregion(t, bsh, offset, size, bshp) \
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((*(bshp) = (bsh) + (offset)), 0)
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((*(bshp) = (bus_space_handle_t)__BA(t, bsh, offset)), 0)
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/*
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* int bus_space_alloc __P((bus_space_tag_t t, bus_addr_t rstart,
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@ -189,16 +177,16 @@ extern void * mapiodev __P((paddr_t, psize_t));
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* described by tag/handle/offset.
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*/
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#define bus_space_read_1(t, h, o) (in8((h) + (o)))
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#define bus_space_read_2(t, h, o) (in16rb((h) + (o)))
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#define bus_space_read_4(t, h, o) (in32rb((h) + (o)))
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#define bus_space_read_1(t, h, o) (in8(__BA(t, h, o)))
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#define bus_space_read_2(t, h, o) (in16rb(__BA(t, h, o)))
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#define bus_space_read_4(t, h, o) (in32rb(__BA(t, h, o)))
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#if 0 /* Cause a link error for bus_space_read_8 */
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#define bus_space_read_8(t, h, o) !!! unimplemented !!!
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#endif
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#define bus_space_read_stream_1(t, h, o) (in8((h) + (o)))
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#define bus_space_read_stream_2(t, h, o) (in16((h) + (o)))
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#define bus_space_read_stream_4(t, h, o) (in32((h) + (o)))
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#define bus_space_read_stream_1(t, h, o) (in8(__BA(t, h, o)))
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#define bus_space_read_stream_2(t, h, o) (in16(__BA(t, h, o)))
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#define bus_space_read_stream_4(t, h, o) (in32(__BA(t, h, o)))
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#if 0 /* Cause a link error for bus_space_read_stream_8 */
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#define bus_space_read_8(t, h, o) !!! unimplemented !!!
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#endif
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@ -213,15 +201,15 @@ extern void * mapiodev __P((paddr_t, psize_t));
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*/
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#define bus_space_read_multi_1(t, h, o, a, c) do { \
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ins8((u_int8_t *)((h) + (o)), (a), (c)); \
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ins8(__BA(t, h, o), (a), (c)); \
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} while (0)
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#define bus_space_read_multi_2(t, h, o, a, c) do { \
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ins16rb((u_int16_t *)((h) + (o)), (a), (c)); \
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ins16rb(__BA(t, h, o), (a), (c)); \
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} while (0)
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#define bus_space_read_multi_4(t, h, o, a, c) do { \
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ins32rb((u_int32_t *)((h) + (o)), (a), (c)); \
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ins32rb(__BA(t, h, o), (a), (c)); \
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} while (0)
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#if 0 /* Cause a link error for bus_space_read_multi_8 */
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@ -229,15 +217,15 @@ extern void * mapiodev __P((paddr_t, psize_t));
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#endif
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#define bus_space_read_multi_stream_1(t, h, o, a, c) do { \
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ins8((u_int8_t *)((h) + (o)), (a), (c)); \
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ins8(__BA(t, h, o), (a), (c)); \
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} while (0)
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#define bus_space_read_multi_stream_2(t, h, o, a, c) do { \
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ins16((u_int16_t *)((h) + (o)), (a), (c)); \
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ins16(__BA(t, h, o), (a), (c)); \
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} while (0)
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#define bus_space_read_multi_stream_4(t, h, o, a, c) do { \
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ins32((u_int32_t *)((h) + (o)), (a), (c)); \
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ins32(__BA(t, h, o), (a), (c)); \
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} while (0)
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#if 0 /* Cause a link error for bus_space_read_multi_stream_8 */
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@ -262,9 +250,8 @@ bus_space_read_region_1(tag, bsh, offset, addr, count)
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u_int8_t *addr;
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size_t count;
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{
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volatile u_int8_t *s;
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volatile u_int8_t *s = __BA(tag, bsh, offset);
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s = (volatile u_int8_t *)(bsh + offset);
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while (count--)
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*addr++ = *s++;
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__asm __volatile("eieio; sync");
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@ -278,9 +265,8 @@ bus_space_read_region_2(tag, bsh, offset, addr, count)
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u_int16_t *addr;
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size_t count;
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{
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volatile u_int16_t *s;
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volatile u_int16_t *s = __BA(tag, bsh, offset);
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s = (volatile u_int16_t *)(bsh + offset);
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while (count--)
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__asm __volatile("lhbrx %0, 0, %1" :
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"=r"(*addr++) : "r"(s++));
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@ -295,9 +281,8 @@ bus_space_read_region_4(tag, bsh, offset, addr, count)
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u_int32_t *addr;
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size_t count;
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{
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volatile u_int32_t *s;
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volatile u_int32_t *s = __BA(tag, bsh, offset);
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s = (volatile u_int32_t *)(bsh + offset);
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while (count--)
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__asm __volatile("lwbrx %0, 0, %1" :
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"=r"(*addr++) : "r"(s++));
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@ -316,9 +301,8 @@ bus_space_read_region_stream_2(tag, bsh, offset, addr, count)
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u_int16_t *addr;
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size_t count;
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{
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volatile u_int16_t *s;
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volatile u_int16_t *s = __BA(tag, bsh, offset);
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s = (volatile u_int16_t *)(bsh + offset);
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while (count--)
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*addr++ = *s++;
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__asm __volatile("eieio; sync");
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@ -332,9 +316,8 @@ bus_space_read_region_stream_4(tag, bsh, offset, addr, count)
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u_int32_t *addr;
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size_t count;
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{
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volatile u_int32_t *s;
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volatile u_int32_t *s = __BA(tag, bsh, offset);
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s = (volatile u_int32_t *)(bsh + offset);
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while (count--)
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*addr++ = *s++;
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__asm __volatile("eieio; sync");
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@ -353,16 +336,16 @@ bus_space_read_region_stream_4(tag, bsh, offset, addr, count)
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* described by tag/handle/offset.
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*/
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#define bus_space_write_1(t, h, o, v) out8((h) + (o), (v))
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#define bus_space_write_2(t, h, o, v) out16rb((h) + (o), (v))
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#define bus_space_write_4(t, h, o, v) out32rb((h) + (o), (v))
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#define bus_space_write_1(t, h, o, v) out8(__BA(t, h, o), (v))
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#define bus_space_write_2(t, h, o, v) out16rb(__BA(t, h, o), (v))
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#define bus_space_write_4(t, h, o, v) out32rb(__BA(t, h, o), (v))
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#define bus_space_write_stream_1(t, h, o, v) out8((h) + (o), (v))
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#define bus_space_write_stream_2(t, h, o, v) out16((h) + (o), (v))
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#define bus_space_write_stream_4(t, h, o, v) out32((h) + (o), (v))
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#define bus_space_write_stream_1(t, h, o, v) out8(__BA(t, h, o), (v))
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#define bus_space_write_stream_2(t, h, o, v) out16(__BA(t, h, o), (v))
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#define bus_space_write_stream_4(t, h, o, v) out32(__BA(t, h, o), (v))
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#if 0 /* Cause a link error for bus_space_write_8 */
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#define bus_space_write_8
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#define bus_space_write_8 !!! unimplemented !!!
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#endif
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/*
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@ -375,31 +358,31 @@ bus_space_read_region_stream_4(tag, bsh, offset, addr, count)
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*/
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#define bus_space_write_multi_1(t, h, o, a, c) do { \
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outsb((u_int8_t *)((h) + (o)), (a), (c)); \
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outsb(__BA(t, h, o), (a), (c)); \
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} while (0)
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#define bus_space_write_multi_2(t, h, o, a, c) do { \
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outsw((u_int16_t *)((h) + (o)), (a), (c)); \
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outsw(__BA(t, h, o), (a), (c)); \
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} while (0)
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#define bus_space_write_multi_4(t, h, o, a, c) do { \
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outsl((u_int32_t *)((h) + (o)), (a), (c)); \
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outsl(__BA(t, h, o), (a), (c)); \
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} while (0)
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#if 0
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#define bus_space_write_multi_8
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#define bus_space_write_multi_8 !!! unimplemented !!!
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#endif
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#define bus_space_write_multi_stream_2(t, h, o, a, c) do { \
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outsw((u_int16_t *)((h) + (o)), (a), (c)); \
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outsw(__BA(t, h, o), (a), (c)); \
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} while (0)
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#define bus_space_write_multi_stream_4(t, h, o, a, c) do { \
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outsl((u_int32_t *)((h) + (o)), (a), (c)); \
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outsl(__BA(t, h, o), (a), (c)); \
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} while (0)
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#if 0
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#define bus_space_write_multi_stream_8
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#define bus_space_write_multi_stream_8 !!! unimplemented !!!
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#endif
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/*
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@ -419,9 +402,8 @@ bus_space_write_region_1(tag, bsh, offset, addr, count)
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const u_int8_t *addr;
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size_t count;
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{
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volatile u_int8_t *d;
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volatile u_int8_t *d = __BA(tag, bsh, offset);
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d = (volatile u_int8_t *)(bsh + offset);
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while (count--)
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*d++ = *addr++;
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__asm __volatile("eieio; sync");
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@ -435,9 +417,8 @@ bus_space_write_region_2(tag, bsh, offset, addr, count)
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const u_int16_t *addr;
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size_t count;
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{
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volatile u_int16_t *d;
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volatile u_int16_t *d = __BA(tag, bsh, offset);
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d = (volatile u_int16_t *)(bsh + offset);
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while (count--)
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__asm __volatile("sthbrx %0, 0, %1" ::
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"r"(*addr++), "r"(d++));
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@ -452,9 +433,8 @@ bus_space_write_region_4(tag, bsh, offset, addr, count)
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const u_int32_t *addr;
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size_t count;
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{
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volatile u_int32_t *d;
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volatile u_int32_t *d = __BA(tag, bsh, offset);
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d = (volatile u_int32_t *)(bsh + offset);
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while (count--)
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__asm __volatile("stwbrx %0, 0, %1" ::
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"r"(*addr++), "r"(d++));
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@ -473,9 +453,8 @@ bus_space_write_region_stream_2(tag, bsh, offset, addr, count)
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const u_int16_t *addr;
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size_t count;
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{
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volatile u_int16_t *d;
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volatile u_int16_t *d = __BA(tag, bsh, offset);
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d = (volatile u_int16_t *)(bsh + offset);
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while (count--)
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*d++ = *addr++;
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__asm __volatile("eieio; sync");
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@ -489,9 +468,8 @@ bus_space_write_region_stream_4(tag, bsh, offset, addr, count)
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const u_int32_t *addr;
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size_t count;
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{
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volatile u_int32_t *d;
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volatile u_int32_t *d = __BA(tag, bsh, offset);
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d = (volatile u_int32_t *)(bsh + offset);
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while (count--)
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*d++ = *addr++;
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__asm __volatile("eieio; sync");
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@ -518,9 +496,8 @@ bus_space_set_multi_1(tag, bsh, offset, val, count)
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u_int8_t val;
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size_t count;
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{
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volatile u_int8_t *d;
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volatile u_int8_t *d = __BA(tag, bsh, offset);
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d = (volatile u_int8_t *)(bsh + offset);
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while (count--)
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*d = val;
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__asm __volatile("eieio; sync");
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@ -534,9 +511,8 @@ bus_space_set_multi_2(tag, bsh, offset, val, count)
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u_int16_t val;
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size_t count;
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{
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volatile u_int16_t *d;
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volatile u_int16_t *d = __BA(tag, bsh, offset);
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d = (volatile u_int16_t *)(bsh + offset);
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while (count--)
|
||||
__asm __volatile("sthbrx %0, 0, %1" ::
|
||||
"r"(val), "r"(d));
|
||||
|
|
@ -551,9 +527,8 @@ bus_space_set_multi_4(tag, bsh, offset, val, count)
|
|||
u_int32_t val;
|
||||
size_t count;
|
||||
{
|
||||
volatile u_int32_t *d;
|
||||
volatile u_int32_t *d = __BA(tag, bsh, offset);
|
||||
|
||||
d = (volatile u_int32_t *)(bsh + offset);
|
||||
while (count--)
|
||||
__asm __volatile("stwbrx %0, 0, %1" ::
|
||||
"r"(val), "r"(d));
|
||||
|
|
@ -572,9 +547,8 @@ bus_space_set_multi_stream_2(tag, bsh, offset, val, count)
|
|||
u_int16_t val;
|
||||
size_t count;
|
||||
{
|
||||
volatile u_int16_t *d;
|
||||
volatile u_int16_t *d = __BA(tag, bsh, offset);
|
||||
|
||||
d = (volatile u_int16_t *)(bsh + offset);
|
||||
while (count--)
|
||||
*d = val;
|
||||
__asm __volatile("eieio; sync");
|
||||
|
|
@ -588,17 +562,15 @@ bus_space_set_multi_stream_4(tag, bsh, offset, val, count)
|
|||
u_int32_t val;
|
||||
size_t count;
|
||||
{
|
||||
volatile u_int32_t *d;
|
||||
volatile u_int32_t *d = __BA(tag, bsh, offset);
|
||||
|
||||
d = (volatile u_int32_t *)(bsh + offset);
|
||||
while (count--)
|
||||
*d = val;
|
||||
__asm __volatile("eieio; sync");
|
||||
}
|
||||
|
||||
#if 0
|
||||
#define bus_space_set_multi_stream_8 \
|
||||
!!! bus_space_set_multi_stream_8 unimplemented !!!
|
||||
#define bus_space_set_multi_stream_8 !!! unimplemented !!!
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -618,9 +590,8 @@ bus_space_set_region_1(tag, bsh, offset, val, count)
|
|||
u_int8_t val;
|
||||
size_t count;
|
||||
{
|
||||
volatile u_int8_t *d;
|
||||
volatile u_int8_t *d = __BA(tag, bsh, offset);
|
||||
|
||||
d = (volatile u_int8_t *)(bsh + offset);
|
||||
while (count--)
|
||||
*d++ = val;
|
||||
__asm __volatile("eieio; sync");
|
||||
|
|
@ -634,9 +605,8 @@ bus_space_set_region_2(tag, bsh, offset, val, count)
|
|||
u_int16_t val;
|
||||
size_t count;
|
||||
{
|
||||
volatile u_int16_t *d;
|
||||
volatile u_int16_t *d = __BA(tag, bsh, offset);
|
||||
|
||||
d = (volatile u_int16_t *)(bsh + offset);
|
||||
while (count--)
|
||||
__asm __volatile("sthbrx %0, 0, %1" ::
|
||||
"r"(val), "r"(d++));
|
||||
|
|
@ -651,9 +621,8 @@ bus_space_set_region_4(tag, bsh, offset, val, count)
|
|||
u_int32_t val;
|
||||
size_t count;
|
||||
{
|
||||
volatile u_int32_t *d;
|
||||
volatile u_int32_t *d = __BA(tag, bsh, offset);
|
||||
|
||||
d = (volatile u_int32_t *)(bsh + offset);
|
||||
while (count--)
|
||||
__asm __volatile("stwbrx %0, 0, %1" ::
|
||||
"r"(val), "r"(d++));
|
||||
|
|
@ -672,9 +641,8 @@ bus_space_set_region_stream_2(tag, bsh, offset, val, count)
|
|||
u_int16_t val;
|
||||
size_t count;
|
||||
{
|
||||
volatile u_int16_t *d;
|
||||
volatile u_int16_t *d = __BA(tag, bsh, offset);
|
||||
|
||||
d = (volatile u_int16_t *)(bsh + offset);
|
||||
while (count--)
|
||||
*d++ = val;
|
||||
__asm __volatile("eieio; sync");
|
||||
|
|
@ -688,17 +656,15 @@ bus_space_set_region_stream_4(tag, bsh, offset, val, count)
|
|||
u_int32_t val;
|
||||
size_t count;
|
||||
{
|
||||
volatile u_int32_t *d;
|
||||
volatile u_int32_t *d = __BA(tag, bsh, offset);
|
||||
|
||||
d = (volatile u_int32_t *)(bsh + offset);
|
||||
while (count--)
|
||||
*d++ = val;
|
||||
__asm __volatile("eieio; sync");
|
||||
}
|
||||
|
||||
#if 0
|
||||
#define bus_space_set_region_stream_8 \
|
||||
!!! bus_space_set_region_stream_8 unimplemented !!!
|
||||
#define bus_space_set_region_stream_8 !!! unimplemented !!!
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -723,10 +689,17 @@ bus_space_set_region_stream_4(tag, bsh, offset, val, count)
|
|||
* Note: the macppc does not currently require barriers, but we must
|
||||
* provide the flags to MI code.
|
||||
*/
|
||||
|
||||
#define bus_space_barrier(t, h, o, l, f) \
|
||||
((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
|
||||
#define BUS_BARRIER_READ 0x01 /* force read barrier */
|
||||
#define BUS_BARRIER_WRITE 0x02 /* force write barrier */
|
||||
#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
|
||||
#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
|
||||
|
||||
#ifdef __BUS_SPACE_COMPAT_OLDDEFS
|
||||
/* compatibility definitions; deprecated */
|
||||
#define BUS_BARRIER_READ BUS_SPACE_BARRIER_READ
|
||||
#define BUS_BARRIER_WRITE BUS_SPACE_BARRIER_WRITE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Bus DMA methods.
|
||||
|
|
|
|||
Loading…
Reference in New Issue