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This commit is contained in:
macallan 2014-12-23 18:48:52 +00:00
parent a7cfe46ea7
commit fa629718a1
3 changed files with 50 additions and 44 deletions
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6
sys/arch/mips/ingenic/apbus.c
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@ -1,4 +1,4 @@
/* $NetBSD: apbus.c,v 1.3 2014/12/23 16:16:03 macallan Exp $ */ /* $NetBSD: apbus.c,v 1.4 2014/12/23 18:48:52 macallan Exp $ */
/*- /*-
* Copyright (c) 2014 Michael Lorenz * Copyright (c) 2014 Michael Lorenz
@ -29,7 +29,7 @@
/* catch-all for on-chip peripherals */ /* catch-all for on-chip peripherals */
#include <sys/cdefs.h> #include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: apbus.c,v 1.3 2014/12/23 16:16:03 macallan Exp $"); __KERNEL_RCSID(0, "$NetBSD: apbus.c,v 1.4 2014/12/23 18:48:52 macallan Exp $");
#include "locators.h" #include "locators.h"
#define _MIPS_BUS_DMA_PRIVATE #define _MIPS_BUS_DMA_PRIVATE
@ -117,7 +117,7 @@ apbus_attach(device_t parent, device_t self, void *aux)
/* wake up the USB part */ /* wake up the USB part */
reg = readreg(JZ_OPCR); reg = readreg(JZ_OPCR);
reg |= SPENDN0 | SPENDN1; reg |= OPCR_SPENDN0 | OPCR_SPENDN1;
writereg(JZ_OPCR, reg); writereg(JZ_OPCR, reg);
#ifdef INGENIC_DEBUG #ifdef INGENIC_DEBUG

20
sys/arch/mips/ingenic/ingenic_dwctwo.c
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@ -1,4 +1,4 @@
/* $NetBSD: ingenic_dwctwo.c,v 1.2 2014/12/23 15:13:30 macallan Exp $ */ /* $NetBSD: ingenic_dwctwo.c,v 1.3 2014/12/23 18:48:52 macallan Exp $ */
/*- /*-
* Copyright (c) 2014 Michael Lorenz * Copyright (c) 2014 Michael Lorenz
@ -27,7 +27,7 @@
*/ */
#include <sys/cdefs.h> #include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ingenic_dwctwo.c,v 1.2 2014/12/23 15:13:30 macallan Exp $"); __KERNEL_RCSID(0, "$NetBSD: ingenic_dwctwo.c,v 1.3 2014/12/23 18:48:52 macallan Exp $");
/* /*
* adapted from bcm2835_dwctwo.c * adapted from bcm2835_dwctwo.c
@ -136,12 +136,15 @@ ingenic_dwc2_attach(device_t parent, device_t self, void *aux)
aprint_normal(": USB controller\n"); aprint_normal(": USB controller\n");
reg = readreg(JZ_USBPCR); reg = readreg(JZ_USBPCR);
reg |= VBUSVLDEXTSEL; reg |= PCR_VBUSVLDEXTSEL;
reg |= VBUSVLDEXT; reg |= PCR_VBUSVLDEXT;
reg |= USB_MODE; reg |= PCR_USB_MODE;
reg |= COMMONONN; reg |= PCR_COMMONONN;
reg &= ~OTG_DISABLE; reg &= ~PCR_OTG_DISABLE;
writereg(JZ_USBPCR, reg); writereg(JZ_USBPCR, reg);
#ifdef INGENIC_DEBUG
printf("JZ_USBPCR %08x\n", reg);
#endif
reg = readreg(JZ_USBPCR1); reg = readreg(JZ_USBPCR1);
reg |= PCR_SYNOPSYS; reg |= PCR_SYNOPSYS;
@ -150,6 +153,9 @@ ingenic_dwc2_attach(device_t parent, device_t self, void *aux)
reg |= PCR_CLK_48; reg |= PCR_CLK_48;
reg |= PCR_WORD_I_F0; reg |= PCR_WORD_I_F0;
writereg(JZ_USBPCR1, reg); writereg(JZ_USBPCR1, reg);
#ifdef INGENIC_DEBUG
printf("JZ_USBPCR1 %08x\n", reg);
#endif
delay(10000); delay(10000);

68
sys/arch/mips/ingenic/ingenic_regs.h
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@ -1,4 +1,4 @@
/* $NetBSD: ingenic_regs.h,v 1.4 2014/12/23 16:15:05 macallan Exp $ */ /* $NetBSD: ingenic_regs.h,v 1.5 2014/12/23 18:48:52 macallan Exp $ */
/*- /*-
* Copyright (c) 2014 Michael Lorenz * Copyright (c) 2014 Michael Lorenz
@ -164,41 +164,41 @@ MFC0(uint32_t r, uint32_t s)
/* power management */ /* power management */
#define JZ_CLKGR0 0x10000020 /* CLocK Gating Registers */ #define JZ_CLKGR0 0x10000020 /* CLocK Gating Registers */
#define JZ_OPCR 0x10000024 /* Oscillator Power Control Reg. */ #define JZ_OPCR 0x10000024 /* Oscillator Power Control Reg. */
#define IDLE_DIS 0x80000000 /* don't stop CPU clk on idle */ #define OPCR_IDLE_DIS 0x80000000 /* don't stop CPU clk on idle */
#define GPU_CLK_STOP 0x40000000 #define OPCR_GPU_CLK_ST 0x40000000 /* stop GPU clock */
#define L2CM_M 0x0c000000 #define OPCR_L2CM_M 0x0c000000
#define L2CM_ON 0x00000000 /* L2 stays on in sleep */ #define OPCR_L2CM_ON 0x00000000 /* L2 stays on in sleep */
#define L2CM_RET 0x04000000 /* L2 retention mode in sleep */ #define OPCR_L2CM_RET 0x04000000 /* L2 retention mode in sleep */
#define L2CM_OFF 0x08000000 /* L2 powers down in sleep */ #define OPCR_L2CM_OFF 0x08000000 /* L2 powers down in sleep */
#define SPENDN0 0x00000080 /* OTG port forced down */ #define OPCR_SPENDN0 0x00000080 /* OTG port forced down */
#define SPENDN1 0x00000040 /* UHC port forced down */ #define OPCR_SPENDN1 0x00000040 /* UHC port forced down */
#define BUS_MODE 0x00000020 /* 1 - bursts */ #define OPCR_BUS_MODE 0x00000020 /* 1 - bursts */
#define O1SE 0x00000010 /* EXTCLK on in sleep */ #define OPCR_O1SE 0x00000010 /* EXTCLK on in sleep */
#define PD 0x00000008 /* P0 down in sleep */ #define OPCR_PD 0x00000008 /* P0 down in sleep */
#define ERCS 0x00000004 /* 1 RTCCLK, 0 EXTCLK/512 */ #define OPCR_ERCS 0x00000004 /* 1 RTCCLK, 0 EXTCLK/512 */
#define CPU_MODE 0x00000002 /* 1 access 'accelerated' */ #define OPCR_CPU_MODE 0x00000002 /* 1 access 'accelerated' */
#define OSE 0x00000001 /* disable EXTCLK */ #define OPCR_OSE 0x00000001 /* disable EXTCLK */
#define JZ_CLKGR1 0x10000028 /* CLocK Gating Registers */ #define JZ_CLKGR1 0x10000028 /* CLocK Gating Registers */
#define JZ_USBPCR 0x1000003c #define JZ_USBPCR 0x1000003c
#define USB_MODE 0x80000000 /* 1 - otg */ #define PCR_USB_MODE 0x80000000 /* 1 - otg */
#define AVLD_REG 0x40000000 #define PCR_AVLD_REG 0x40000000
#define IDPULLUP_MASK 0x30000000 #define PCR_IDPULLUP_MASK 0x30000000
#define INCR_MASK 0x08000000 #define PCR_INCR_MASK 0x08000000
#define TCRISETUNE 0x04000000 #define PCR_TCRISETUNE 0x04000000
#define COMMONONN 0x02000000 #define PCR_COMMONONN 0x02000000
#define VBUSVLDEXT 0x01000000 #define PCR_VBUSVLDEXT 0x01000000
#define VBUSVLDEXTSEL 0x00800000 #define PCR_VBUSVLDEXTSEL 0x00800000
#define POR 0x00400000 #define PCR_POR 0x00400000
#define SIDDQ 0x00200000 #define PCR_SIDDQ 0x00200000
#define OTG_DISABLE 0x00100000 #define PCR_OTG_DISABLE 0x00100000
#define COMPDISTUNE_M 0x000e0000 #define PCR_COMPDISTN_M 0x000e0000
#define OTGTUNE 0x0001c000 #define PCR_OTGTUNE 0x0001c000
#define SQRXTUNE 0x00003800 #define PCR_SQRXTUNE 0x00003800
#define TXFSLSTUNE 0x00000780 #define PCR_TXFSLSTUNE 0x00000780
#define TXPREEMPHTUNE 0x00000040 #define PCR_TXPREEMPHTUNE 0x00000040
#define TXHSXVTUNE 0x00000030 #define PCR_TXHSXVTUNE 0x00000030
#define TXVREFTUNE 0x0000000f #define PCR_TXVREFTUNE 0x0000000f
#define JZ_USBPCR1 0x10000048 #define JZ_USBPCR1 0x10000048
#define PCR_SYNOPSYS 0x10000000 /* Mentor mode otherwise */ #define PCR_SYNOPSYS 0x10000000 /* Mentor mode otherwise */
#define PCR_REFCLK_CORE 0x0c000000 #define PCR_REFCLK_CORE 0x0c000000