Miscellaneous clean-ups:
1. Use proper CRc check for FB-DIMMs rather than simple checksum
2. Provide access to entire SPD ROM contents via sysctl, rather than
only the first 64 bytes
3. Use macros to define i2c bus address checking
4. General fix-up for RAMBUS memory (not that anyone I know has one)
OK garbled@
This commit is contained in:
pgoyette
parent
12f08b06b6
commit
f9eb81cfb1
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@ -1,4 +1,4 @@
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/* $NetBSD: spdmem.c,v 1.8 2008/05/04 15:26:29 xtraeme Exp $ */
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/* $NetBSD: spdmem.c,v 1.9 2008/09/27 06:58:08 pgoyette Exp $ */
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/*
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* Copyright (c) 2007 Nicolas Joly
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@ -35,10 +35,11 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.8 2008/05/04 15:26:29 xtraeme Exp $");
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__KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.9 2008/09/27 06:58:08 pgoyette Exp $");
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/endian.h>
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#include <sys/sysctl.h>
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#include <machine/bswap.h>
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@ -116,29 +117,93 @@ static const uint8_t spdmem_cycle_frac[] = {
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/* sysctl stuff */
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static int hw_node = CTL_EOL;
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/* CRC functions used for certain memory types */
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static uint16_t spdcrc16 (struct spdmem_softc *sc, int count)
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{
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uint16_t crc;
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int i, j;
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uint8_t val;
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crc = 0;
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for (j = 0; j <= count; j++) {
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val = spdmem_read(sc, j);
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crc = crc ^ val << 8;
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for (i = 0; i < 8; ++i)
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if (crc & 0x8000)
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crc = crc << 1 ^ 0x1021;
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else
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crc = crc << 1;
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}
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return (crc & 0xFFFF);
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}
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static int
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spdmem_match(device_t parent, cfdata_t match, void *aux)
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{
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struct i2c_attach_args *ia = aux;
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struct spdmem_softc sc;
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int cksum = 0;
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uint8_t i, val;
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uint8_t i, val, spd_type;
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int spd_len, spd_crc_cover;
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uint16_t crc_calc, crc_spd;
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if (ia->ia_addr < 0x50 || ia->ia_addr > 0x57)
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if ((ia->ia_addr & SPDMEM_ADDRMASK) != SPDMEM_ADDR)
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return 0;
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sc.sc_tag = ia->ia_tag;
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sc.sc_addr = ia->ia_addr;
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for (i = 0; i < 63; i++)
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cksum += spdmem_read(&sc, i);
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spd_type = spdmem_read(&sc, 2);
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val = spdmem_read(&sc, 63);
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/* For older memory types, validate the checksum over 1st 63 bytes */
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if (spd_type <= SPDMEM_MEMTYPE_DDR2SDRAM) {
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for (i = 0; i < 63; i++)
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cksum += spdmem_read(&sc, i);
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if (cksum == 0 || (cksum & 0xff) != val)
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return 0;
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val = spdmem_read(&sc, 63);
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return 1;
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if (cksum == 0 || (cksum & 0xff) != val) {
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aprint_debug("spd addr 0x%2x: ", sc.sc_addr);
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aprint_debug("spd checksum failed, calc = 0x%02x, "
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"spd = 0x%02x\n", cksum, val);
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return 0;
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} else
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return 1;
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}
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/* For FBDIMM and newer, verify the CRC */
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else {
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spd_len = spdmem_read(&sc, 0);
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if (spd_len && SPDMEM_SPDCRC_116)
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spd_crc_cover = 116;
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else
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spd_crc_cover = 125;
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switch (spd_len & SPDMEM_SPDLEN_MASK) {
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case SPDMEM_SPDLEN_128:
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spd_len = 128;
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break;
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case SPDMEM_SPDLEN_176:
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spd_len = 176;
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break;
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case SPDMEM_SPDLEN_256:
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spd_len = 256;
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break;
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default:
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return 0;
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}
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if (spd_crc_cover > spd_len)
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return 0;
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crc_calc = spdcrc16(&sc, spd_crc_cover);
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crc_spd = spdmem_read(&sc, 127) << 8;
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crc_spd |= spdmem_read(&sc, 126);
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if (crc_calc != crc_spd) {
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aprint_debug("spd addr 0x%2x: ", sc.sc_addr);
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aprint_debug("crc16 failed, covers %d bytes, "
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"calc = 0x%04x, spd = 0x%04x\n",
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spd_crc_cover, crc_calc, crc_spd);
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return 0;
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}
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return 1;
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}
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}
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static void
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@ -151,27 +216,65 @@ spdmem_attach(device_t parent, device_t self, void *aux)
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const char *voltage;
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const char *refresh;
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const char *ddr_type_string = NULL;
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const char *rambus_rev = "Reserved";
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int num_banks = 0;
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int per_chip = 0;
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int dimm_size, cycle_time, d_clk, p_clk, bits;
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int i;
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unsigned int spd_len, spd_size;
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const struct sysctlnode *node = NULL;
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sc->sc_tag = ia->ia_tag;
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sc->sc_addr = ia->ia_addr;
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/* All SPD have at least 64 bytes of data including checksum */
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for (i = 0; i < 64; i++) {
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((uint8_t *)s)[i] = spdmem_read(sc, i);
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if (!pmf_device_register(self, NULL, NULL))
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aprint_error_dev(self, "couldn't establish power handler\n");
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/*
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* FBDIMM (and probably all newer) has a different
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* encoding of the SPD EEPROM used/total sizes
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*/
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s->sm_len = spdmem_read(sc, 0);
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s->sm_size = spdmem_read(sc, 1);
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s->sm_type = spdmem_read(sc, 2);
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if (s->sm_type >= SPDMEM_MEMTYPE_FBDIMM) {
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spd_size = 64 << (s->sm_len & SPDMEM_SPDSIZE_MASK);
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switch (s->sm_len & SPDMEM_SPDLEN_MASK) {
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case SPDMEM_SPDLEN_128:
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spd_len = 128;
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break;
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case SPDMEM_SPDLEN_176:
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spd_len = 176;
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break;
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case SPDMEM_SPDLEN_256:
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spd_len = 256;
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break;
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default:
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spd_len = 64;
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break;
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}
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} else {
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spd_size = 1 << s->sm_size;
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spd_len = s->sm_len;
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if (spd_len < 64)
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spd_len = 64;
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}
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if (spd_len > spd_size)
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spd_len = spd_size;
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if (spd_len > sizeof(struct spdmem))
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spd_len = sizeof(struct spdmem);
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for (i = 3; i < spd_len; i++)
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((uint8_t *)s)[i] = spdmem_read(sc, i);
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#ifdef DEBUG
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for (i = 0; i < 64; i += 16) {
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int j;
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for (i = 0; i < spd_len; i += 16) {
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int j, k;
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aprint_debug("\n");
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aprint_debug_dev(self, "0x%02x:", i);
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for(j = 0; j < 16; j++)
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aprint_debug(" %02x", ((uint8_t *)s)[i + j]);
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k = (spd_len > i + 16) ? spd_len : i + 16;
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for (j = i; j < k; j++)
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aprint_debug(" %02x", ((uint8_t *)s)[j]);
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}
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aprint_debug("\n");
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aprint_debug_dev(self, "");
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@ -185,21 +288,41 @@ spdmem_attach(device_t parent, device_t self, void *aux)
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0, CTLTYPE_NODE,
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device_xname(self), NULL, NULL, 0, NULL, 0,
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CTL_HW, CTL_CREATE, CTL_EOL);
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if (node != NULL)
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if (node != NULL && spd_len != 0)
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sysctl_createv(NULL, 0, NULL, NULL,
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0,
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CTLTYPE_STRUCT, "spd_data",
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SYSCTL_DESCR("raw spd data (first 64 bytes)"), NULL,
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0, s, sizeof(*s),
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SYSCTL_DESCR("raw spd data"), NULL,
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0, s, spd_len,
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CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL);
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/*
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* Decode and print SPD contents
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* Decode and print key SPD contents
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*/
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if (IS_RAMBUS_TYPE)
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type = "Rambus";
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else {
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if (s->sm_type <= 10)
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if (IS_RAMBUS_TYPE) {
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if (s->sm_type == SPDMEM_MEMTYPE_RAMBUS)
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type = "Rambus";
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else if (s->sm_type == SPDMEM_MEMTYPE_DIRECTRAMBUS)
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type = "Direct Rambus";
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else
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type = "Rambus (unknown)";
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switch (s->sm_len) {
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case 0:
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rambus_rev = "Invalid";
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break;
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case 1:
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rambus_rev = "0.7";
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break;
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case 2:
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rambus_rev = "1.0";
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break;
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default:
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rambus_rev = "Reserved";
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break;
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}
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} else {
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if (s->sm_type < __arraycount(spdmem_basic_types))
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type = spdmem_basic_types[s->sm_type];
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else
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type = "unknown memory type";
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@ -231,16 +354,20 @@ spdmem_attach(device_t parent, device_t self, void *aux)
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0, sc->sc_type, 0,
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CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL);
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if ((s->sm_type == SPDMEM_MEMTYPE_SDRAM ||
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s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM ||
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s->sm_type == SPDMEM_MEMTYPE_DDR2SDRAM ) &&
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s->sm_config < 8)
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if (IS_RAMBUS_TYPE)
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aprint_normal(", SPD Revision %s", rambus_rev);
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else if (s->sm_config < __arraycount(spdmem_parity_types) &&
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(s->sm_type == SPDMEM_MEMTYPE_SDRAM ||
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s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM ||
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s->sm_type == SPDMEM_MEMTYPE_DDR2SDRAM))
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aprint_normal(", %s", spdmem_parity_types[s->sm_config]);
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/* Extract module size info */
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dimm_size = 0;
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if (IS_RAMBUS_TYPE) {
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aprint_normal(", %dMB",
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1 << (s->sm_rdr.rdr_rows + s->sm_rdr.rdr_cols - 13));
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dimm_size = s->sm_rdr.rdr_rows + s->sm_rdr.rdr_cols - 13;
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num_banks = 1;
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per_chip = 1;
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} else if (s->sm_type == SPDMEM_MEMTYPE_SDRAM) {
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dimm_size = s->sm_sdr.sdr_rows + s->sm_sdr.sdr_cols - 17;
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num_banks = s->sm_sdr.sdr_banks;
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@ -253,9 +380,20 @@ spdmem_attach(device_t parent, device_t self, void *aux)
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dimm_size = s->sm_ddr2.ddr2_rows + s->sm_ddr2.ddr2_cols - 17;
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num_banks = s->sm_ddr2.ddr2_ranks + 1;
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per_chip = s->sm_ddr2.ddr2_banks_per_chip;
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} else if (s->sm_type == SPDMEM_MEMTYPE_FBDIMM ||
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s->sm_type == SPDMEM_MEMTYPE_FBDIMM_PROBE) {
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/*
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* FB-DIMM is quite different from DDR2
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*/
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dimm_size =
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s->sm_fbd.fbdimm_rows + 12 +
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s->sm_fbd.fbdimm_cols + 9 - 20 - 3;
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num_banks = 1 << (s->sm_fbd.fbdimm_banks + 2);
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per_chip = 1;
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}
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if (!(IS_RAMBUS_TYPE) && num_banks <= 8 && per_chip <= 8 &&
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dimm_size > 0 && dimm_size <= 12) {
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if (IS_RAMBUS_TYPE ||
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(num_banks <= 8 && per_chip <= 8 && dimm_size > 0 &&
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dimm_size <= 12)) {
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dimm_size = (1 << dimm_size) * num_banks * per_chip;
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aprint_normal(", %dMB", dimm_size);
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if (node != NULL)
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@ -268,17 +406,21 @@ spdmem_attach(device_t parent, device_t self, void *aux)
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CTL_EOL);
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}
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/* cycle_time is expressed in units of 0.01 ns */
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cycle_time = 0;
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if (s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM ||
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s->sm_type == SPDMEM_MEMTYPE_SDRAM)
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cycle_time = s->sm_ddr.ddr_cycle_whole * 100 +
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s->sm_ddr.ddr_cycle_tenths * 10;
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else if (s->sm_type == SPDMEM_MEMTYPE_DDR2SDRAM) {
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cycle_time = s->sm_ddr2.ddr2_cycle_whole * 100 +
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spdmem_cycle_frac[s->sm_ddr2.ddr2_cycle_frac];
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/* Nothing further for RAMBUS memory */
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if (IS_RAMBUS_TYPE) {
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aprint_normal("\n");
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return;
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}
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/* cycle_time is expressed in units of 0.01 ns */
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cycle_time = 0;
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if (s->sm_type == SPDMEM_MEMTYPE_SDRAM)
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cycle_time = s->sm_sdr.sdr_cycle_whole * 100 +
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s->sm_sdr.sdr_cycle_tenths * 10;
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else if (s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM ||
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s->sm_type == SPDMEM_MEMTYPE_DDR2SDRAM)
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cycle_time = s->sm_ddr2.ddr2_cycle_whole * 100 +
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spdmem_cycle_frac[s->sm_ddr2.ddr2_cycle_frac];
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if (cycle_time != 0) {
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/*
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* cycle time is scaled by a factor of 100 to avoid using
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@ -287,36 +429,26 @@ spdmem_attach(device_t parent, device_t self, void *aux)
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*/
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d_clk = 100 * 1000;
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if (s->sm_type == SPDMEM_MEMTYPE_DDR2SDRAM) {
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/* DDR2 uses quad-pumped clock */
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d_clk *= 4;
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/* DDR2 uses a dual-pumped clock */
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d_clk *= 2;
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bits = s->sm_ddr2.ddr2_datawidth;
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if ((s->sm_config & 0x03) != 0)
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bits -= 8;
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ddr_type_string = "PC2";
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} else if (s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM) {
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/* DDR uses dual-pumped clock */
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/* DDR uses a dual-pumped clock */
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d_clk *= 2;
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#if BYTE_ORDER == BIG_ENDIAN
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bits = bswap16(s->sm_ddr.ddr_datawidth);
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#else
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bits = s->sm_ddr.ddr_datawidth;
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#endif
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bits = le16toh(s->sm_ddr.ddr_datawidth);
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if (s->sm_config == 1 || s->sm_config == 2)
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bits -= 8;
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ddr_type_string = "PC";
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} else { /* SPDMEM_MEMTYPE_SDRAM */
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#if BYTE_ORDER == BIG_ENDIAN
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bits = bswap16(s->sm_ddr.ddr_datawidth);
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#else
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bits = s->sm_ddr.ddr_datawidth;
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#endif
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bits = le16toh(s->sm_sdr.sdr_datawidth);
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if (s->sm_config == 1 || s->sm_config == 2)
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bits -= 8;
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ddr_type_string = "PC";
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}
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d_clk /= cycle_time;
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if (s->sm_type == SPDMEM_MEMTYPE_DDR2SDRAM)
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d_clk = (d_clk + 1) / 2;
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p_clk = d_clk * bits / 8;
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if ((p_clk % 100) >= 50)
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p_clk += 50;
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@ -324,12 +456,12 @@ spdmem_attach(device_t parent, device_t self, void *aux)
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aprint_normal(", %dMHz, %s-%d", d_clk, ddr_type_string, p_clk);
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if (node != NULL)
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sysctl_createv(NULL, 0, NULL, NULL,
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CTLFLAG_IMMEDIATE,
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CTLTYPE_INT, "speed",
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SYSCTL_DESCR("memory speed in MHz"), NULL,
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d_clk, NULL, 0,
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CTL_HW, node->sysctl_num, CTL_CREATE,
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CTL_EOL);
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CTLFLAG_IMMEDIATE,
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CTLTYPE_INT, "speed",
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SYSCTL_DESCR("memory speed in MHz"),
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NULL, d_clk, NULL, 0,
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CTL_HW, node->sysctl_num, CTL_CREATE,
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CTL_EOL);
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}
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aprint_normal("\n");
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@ -377,12 +509,12 @@ spdmem_attach(device_t parent, device_t self, void *aux)
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break;
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}
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if (s->sm_voltage <= 0x5)
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if (s->sm_voltage < __arraycount(spdmem_voltage_types))
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voltage = spdmem_voltage_types[s->sm_voltage];
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else
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voltage = "unknown";
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if (s->sm_refresh <= 0x05)
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if (s->sm_refresh < __arraycount(spdmem_refresh_types))
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refresh = spdmem_refresh_types[s->sm_refresh];
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else
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refresh = "unknown";
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@ -392,9 +524,6 @@ spdmem_attach(device_t parent, device_t self, void *aux)
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if (s->sm_selfrefresh)
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aprint_verbose(" (self-refreshing)");
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aprint_verbose("\n");
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|
||||
if (!pmf_device_register(self, NULL, NULL))
|
||||
aprint_error_dev(self, "couldn't establish power handler\n");
|
||||
}
|
||||
|
||||
static uint8_t
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: spdmemreg.h,v 1.1 2007/08/18 11:26:37 tnn Exp $ */
|
||||
/* $NetBSD: spdmemreg.h,v 1.2 2008/09/27 06:58:09 pgoyette Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007 Paul Goyette
|
||||
|
|
@ -28,6 +28,10 @@
|
|||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* Constants for matching i2c bus address */
|
||||
#define SPDMEM_ADDRMASK 0x78
|
||||
#define SPDMEM_ADDR 0x50
|
||||
|
||||
/* possible values for the memory type */
|
||||
#define SPDMEM_MEMTYPE_FPM 0x01
|
||||
#define SPDMEM_MEMTYPE_EDO 0x02
|
||||
|
|
@ -37,6 +41,24 @@
|
|||
#define SPDMEM_MEMTYPE_DDRSGRAM 0x06
|
||||
#define SPDMEM_MEMTYPE_DDRSDRAM 0x07
|
||||
#define SPDMEM_MEMTYPE_DDR2SDRAM 0x08
|
||||
#define SPDMEM_MEMTYPE_FBDIMM 0x09
|
||||
#define SPDMEM_MEMTYPE_FBDIMM_PROBE 0x0A
|
||||
#define SPDMEM_MEMTYPE_DDR3SDRAM 0x0B
|
||||
|
||||
#define SPDMEM_MEMTYPE_RAMBUS 0x11
|
||||
#define SPDMEM_MEMTYPE_DIRECTRAMBUS 0x01
|
||||
|
||||
/* Encodings of the size used/total byte for certain memory types */
|
||||
#define SPDMEM_SPDSIZE_MASK 0x0F /* SPD EEPROM Size */
|
||||
|
||||
#define SPDMEM_SPDLEN_128 0x00 /* SPD EEPROM Sizes */
|
||||
#define SPDMEM_SPDLEN_176 0x10
|
||||
#define SPDMEM_SPDLEN_256 0x20
|
||||
#define SPDMEM_SPDLEN_MASK 0x70 /* Bits 4 - 6 */
|
||||
|
||||
#define SPDMEM_SPDCRC_116 0x80 /* CRC Bytes covered */
|
||||
#define SPDMEM_SPDCRC_125 0x00
|
||||
#define SPDMEM_SPDCRC_MASK 0x80 /* Bit 7 */
|
||||
|
||||
/* possible values for the supply voltage */
|
||||
#define SPDMEM_VOLTAGE_TTL_5V 0x00
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: spdmemvar.h,v 1.3 2008/05/04 15:26:29 xtraeme Exp $ */
|
||||
/* $NetBSD: spdmemvar.h,v 1.4 2008/09/27 06:58:09 pgoyette Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007 Paul Goyette
|
||||
|
|
@ -29,6 +29,10 @@
|
|||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This information is extracted from JEDEC standard SPD4_01 (www.jedec.org)
|
||||
*/
|
||||
|
||||
#if BYTE_ORDER == BIG_ENDIAN
|
||||
#define SPD_BITFIELD(a, b, c, d) d; c; b; a
|
||||
#else
|
||||
|
|
@ -53,6 +57,7 @@ struct spdmem_fpm { /* FPM and EDO DIMMS */
|
|||
uint8_t fpm_unused2[17];
|
||||
uint8_t fpm_superset;
|
||||
uint8_t fpm_unused3[30];
|
||||
uint8_t fpm_cksum;
|
||||
} __packed;
|
||||
|
||||
struct spdmem_sdram { /* PC66/PC100/PC133 SDRAM */
|
||||
|
|
@ -115,10 +120,11 @@ struct spdmem_sdram { /* PC66/PC100/PC133 SDRAM */
|
|||
uint8_t sdr_tDH;
|
||||
uint8_t sdr_unused2[5];
|
||||
uint8_t sdr_tRC;
|
||||
uint8_t sdr_unused3[20];
|
||||
uint8_t sdr_unused3[18];
|
||||
uint8_t sdr_esdram;
|
||||
uint8_t sdr_super_tech;
|
||||
uint8_t sdr_spdrev;
|
||||
uint8_t sdr_cksum;
|
||||
} __packed;
|
||||
|
||||
struct spdmem_rom {
|
||||
|
|
@ -136,6 +142,7 @@ struct spdmem_rom {
|
|||
uint8_t rom_burstlength;
|
||||
uint8_t rom_unused2[14];
|
||||
uint8_t rom_superset[31];
|
||||
uint8_t rom_cksum;
|
||||
} __packed;
|
||||
|
||||
|
||||
|
|
@ -206,6 +213,7 @@ struct spdmem_ddr { /* Dual Data Rate SDRAM */
|
|||
uint8_t ddr_unused3;
|
||||
uint8_t ddr_height;
|
||||
uint8_t ddr_unused4[15];
|
||||
uint8_t ddr_cksum;
|
||||
} __packed;
|
||||
|
||||
struct spdmem_ddr2 { /* Dual Data Rate 2 SDRAM */
|
||||
|
|
@ -292,6 +300,7 @@ struct spdmem_ddr2 { /* Dual Data Rate 2 SDRAM */
|
|||
uint8_t ddr2_dt_PLL_Active;
|
||||
uint8_t ddr2_dt_Reg_Active;
|
||||
uint8_t ddr2_spdrev;
|
||||
uint8_t ddr2_cksum;
|
||||
} __packed;
|
||||
|
||||
struct spdmem_fbdimm { /* Fully-buffered DIMM */
|
||||
|
|
@ -321,10 +330,10 @@ struct spdmem_fbdimm { /* Fully-buffered DIMM */
|
|||
);
|
||||
uint8_t fbdimm_mtb_dividend;
|
||||
uint8_t fbdimm_mtb_divisor;
|
||||
uint8_t fbdimm_cycle_min;
|
||||
uint8_t fbdimm_cycle_max;
|
||||
uint8_t fbdimm_tCKmin;
|
||||
uint8_t fbdimm_tCKmax;
|
||||
uint8_t fbdimm_tCAS;
|
||||
uint8_t fbdimm_tAA_min;
|
||||
uint8_t fbdimm_tAAmin;
|
||||
SPD_BITFIELD( \
|
||||
uint8_t fbdimm_tWR_min:4, \
|
||||
uint8_t fbdimm_WR_range:4, , \
|
||||
|
|
@ -338,15 +347,15 @@ struct spdmem_fbdimm { /* Fully-buffered DIMM */
|
|||
uint8_t fbdimm_tAL_min:4, \
|
||||
uint8_t fbdimm_tAL_range:4, , \
|
||||
);
|
||||
uint8_t fbdimm_tRCD;
|
||||
uint8_t fbdimm_tRRD;
|
||||
uint8_t fbdimm_tRP;
|
||||
uint8_t fbdimm_tRCDmin;
|
||||
uint8_t fbdimm_tRRDmin;
|
||||
uint8_t fbdimm_tRPmin;
|
||||
SPD_BITFIELD( \
|
||||
uint8_t fbdimm_tRAS_high:4, \
|
||||
uint8_t fbdimm_tRC_high:4, , \
|
||||
uint8_t fbdimm_tRAS_msb:4, \
|
||||
uint8_t fbdimm_tRC_msb:4, , \
|
||||
);
|
||||
uint8_t fbdimm_tRAS_lo;
|
||||
uint8_t fbdimm_tRC_lo;
|
||||
uint8_t fbdimm_tRAS_lsb;
|
||||
uint8_t fbdimm_tRC_lsb;
|
||||
uint16_t fbdimm_tRFC; /* endian-sensitive */
|
||||
uint8_t fbdimm_tWTR;
|
||||
uint8_t fbdimm_tRTP;
|
||||
|
|
@ -367,7 +376,8 @@ struct spdmem_fbdimm { /* Fully-buffered DIMM */
|
|||
uint8_t fbdimm_DT4R_DT4R4W;
|
||||
uint8_t fbdimm_DT5B;
|
||||
uint8_t fbdimm_DT7;
|
||||
uint8_t fbdimm_unused4[21];
|
||||
uint8_t fbdimm_unused4[84];
|
||||
uint16_t fbdimm_crc;
|
||||
} __packed;
|
||||
|
||||
struct spdmem_rambus { /* Direct Rambus DRAM */
|
||||
|
|
@ -390,6 +400,8 @@ struct spdmem {
|
|||
struct spdmem_rambus u1_rdr;
|
||||
struct spdmem_rom u1_rom;
|
||||
} sm_u1;
|
||||
uint8_t sm_extension[128];
|
||||
} __packed;
|
||||
#define sm_fbd sm_u1.u1_fbd
|
||||
#define sm_fpm sm_u1.u1_fpm
|
||||
#define sm_ddr sm_u1.u1_ddr
|
||||
|
|
@ -397,11 +409,10 @@ struct spdmem {
|
|||
#define sm_rdr sm_u1.u1_rdr
|
||||
#define sm_rom sm_u1.u1_rom
|
||||
#define sm_sdr sm_u1.u1_sdr
|
||||
uint8_t sm_cksum;
|
||||
} __packed;
|
||||
|
||||
/* some fields are in the same place for all memory types */
|
||||
|
||||
#define sm_cksum sm_fpm.fpm_cksum
|
||||
#define sm_config sm_fpm.fpm_config
|
||||
#define sm_voltage sm_fpm.fpm_voltage
|
||||
#define sm_refresh sm_fpm.fpm_refresh
|
||||
|
|
|
|||
Loading…
Reference in New Issue