Add support for the SMC91C111 chip, with its internal PHY.
This commit is contained in:
scw
parent
3f3b3242de
commit
f95724bd6b
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@ -1,4 +1,4 @@
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/* $NetBSD: smc91cxx.c,v 1.44 2002/10/22 00:01:57 fair Exp $ */
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/* $NetBSD: smc91cxx.c,v 1.45 2003/04/29 08:47:29 scw Exp $ */
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/*-
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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@ -78,7 +78,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.44 2002/10/22 00:01:57 fair Exp $");
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__KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.45 2003/04/29 08:47:29 scw Exp $");
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#include "opt_inet.h"
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#include "opt_ccitt.h"
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@ -165,7 +165,7 @@ const char *smc91cxx_idstrs[] = {
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NULL, /* 6 */
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"SMC91C100", /* 7 */
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"SMC91C100FD", /* 8 */
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NULL, /* 9 */
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"SMC91C111", /* 9 */
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NULL, /* 10 */
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NULL, /* 11 */
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NULL, /* 12 */
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@ -245,7 +245,7 @@ smc91cxx_attach(sc, myea)
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u_int32_t miicapabilities;
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u_int16_t tmp;
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u_int8_t enaddr[ETHER_ADDR_LEN];
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int i, aui, mult, memsize;
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int i, aui, mult, scale, memsize;
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char pbuf[9];
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/* Make sure the chip is stopped. */
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@ -268,10 +268,19 @@ smc91cxx_attach(sc, myea)
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printf("revision %d, ", RR_REV(tmp));
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SMC_SELECT_BANK(sc, 0);
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mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W));
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switch (sc->sc_chipid) {
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default:
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mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W));
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scale = MIR_SCALE_91C9x;
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break;
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case CHIP_91C111:
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mult = MIR_MULT_91C111;
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scale = MIR_SCALE_91C111;
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}
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memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK;
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if (memsize == 255) memsize++;
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memsize *= 256 * mult;
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memsize *= scale * mult;
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format_bytes(pbuf, sizeof(pbuf), memsize);
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printf("buffer size: %s\n", pbuf);
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@ -325,8 +334,15 @@ smc91cxx_attach(sc, myea)
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*/
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miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX);
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case CHIP_91100FD:
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case CHIP_91C111:
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if (tmp & CR_MII_SELECT) {
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printf("default media MII\n");
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printf("default media MII");
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if (sc->sc_chipid == CHIP_91C111) {
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printf(" (%s PHY)\n", (tmp & CR_AUI_SELECT) ?
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"external" : "internal");
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sc->sc_internal_phy = !(tmp & CR_AUI_SELECT);
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} else
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printf("\n");
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mii_attach(&sc->sc_dev, &sc->sc_mii, miicapabilities,
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MII_PHY_ANY, MII_OFFSET_ANY, 0);
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if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
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@ -340,6 +356,14 @@ smc91cxx_attach(sc, myea)
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}
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sc->sc_flags |= SMC_FLAGS_HAS_MII;
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break;
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} else
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if (sc->sc_chipid == CHIP_91C111) {
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/*
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* XXX: Should bring it out of low-power mode
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*/
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printf("EPH interface in low power mode\n");
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sc->sc_internal_phy = 0;
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return;
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}
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/*FALLTHROUGH*/
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default:
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@ -510,6 +534,19 @@ smc91cxx_init(sc)
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*/
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bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0);
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/*
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* On the 91c111, enable auto-negotiation, and set the LED
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* status pins to something sane.
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* XXX: Should be some way for MD code to decide the latter.
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*/
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SMC_SELECT_BANK(sc, 0);
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if (sc->sc_chipid == CHIP_91C111) {
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bus_space_write_2(bst, bsh, RX_PHY_CONTROL_REG_W,
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RPC_ANEG |
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(RPC_LS_LINK_DETECT << RPC_LSA_SHIFT) |
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(RPC_LS_TXRX << RPC_LSB_SHIFT));
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}
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/*
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* Set current media.
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*/
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@ -551,8 +588,14 @@ smc91cxx_init(sc)
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*/
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SMC_SELECT_BANK(sc, 2);
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bus_space_write_1(bst, bsh, INTR_MASK_REG_B,
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IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | IM_TX_INT);
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if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) {
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bus_space_write_1(bst, bsh, INTR_MASK_REG_B,
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IM_EPH_INT | IM_RX_OVRN_INT |
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IM_RCV_INT | IM_TX_INT | IM_MD_INT);
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} else {
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bus_space_write_1(bst, bsh, INTR_MASK_REG_B,
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IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | IM_TX_INT);
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}
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/* Interface is now running, with no output active. */
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ifp->if_flags |= IFF_RUNNING;
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@ -996,6 +1039,14 @@ smc91cxx_intr(arg)
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ifp->if_timer = 0;
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}
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if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy &&
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(status & IM_MD_INT)) {
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/*
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* Internal PHY status change
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*/
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mii_tick(&sc->sc_mii);
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}
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/*
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* Other errors. Reset the interface.
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*/
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@ -1,4 +1,4 @@
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/* $NetBSD: smc91cxxreg.h,v 1.4 2001/06/12 15:17:23 wiz Exp $ */
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/* $NetBSD: smc91cxxreg.h,v 1.5 2003/04/29 08:47:30 scw Exp $ */
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/*
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* Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
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@ -172,16 +172,38 @@
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#define MIR_FREE_MASK 0xff00 /* Free memory pages available */
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#define MIR_TOTAL_MASK 0x00ff /* Total memory pages available */
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#define MIR_MULT_91C111 1
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#define MIR_SCALE_91C9x 256
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#define MIR_SCALE_91C111 2048
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/*
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* Memory Configuration
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*/
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#define MEM_CFG_REG_W 0x0a
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#define MEM_CFG_REG_W 0x0a
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#define MCR_MEM_MULT(x) (((x)>>9)&7) /* Memory size multiplier */
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#define MCR_TXRSV_MASK 0x001f /* Count of pages reserved for transmit */
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/*
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* Receive/PHY Control Register (SM91C111 only)
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*/
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#define RX_PHY_CONTROL_REG_W 0x0a /* 91C111 only */
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#define RPC_LSB_SHIFT 2 /* Shift for LED-B select bits */
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#define RPC_LSA_SHIFT 5 /* Shift for LED-A select bits */
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#define RPC_LS_MASK 0x7 /* LED Select mask */
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#define RPC_LS_LINK_DETECT 0x0 /* 10/100 link detected */
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#define RPC_LS_LINK_10MBPS 0x2 /* 10 MBPS link detected */
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#define RPC_LS_FULL_DUPLEX 0x3 /* Full duplex operation */
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#define RPC_LS_TXRX 0x4 /* Tx/Rx packet */
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#define RPC_LS_LINK_100MBPS 0x5 /* 100 MBPS link detected */
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#define RPC_LS_RX 0x6 /* Rx packet */
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#define RPC_LS_TX 0x7 /* Tx packet */
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#define RPC_ANEG 0x0800 /* Autonegotiate enable */
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#define RPC_DPLX 0x1000 /* Duplex select (set = Full) */
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#define RPC_SPEED 0x2000 /* Speed (set = 100mbps) */
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/*
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* Bank 0, Register 0x0c is unused in the SMC91C92
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@ -346,6 +368,7 @@
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#define IM_RX_OVRN_INT 0x10 /* Receiver was overrun */
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#define IM_EPH_INT 0x20 /* Misc. EPH conditions (see CONTROL_REG_W) */
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#define IM_ERCV_INT 0x40 /* not on SMC9192 */
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#define IM_MD_INT 0x80 /* SMC91C111 Internal PHY status change */
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/*
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@ -396,6 +419,7 @@
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#define CHIP_9195 5
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#define CHIP_91100 7
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#define CHIP_91100FD 8
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#define CHIP_91C111 9
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: smc91cxxvar.h,v 1.10 2002/09/04 14:54:37 scw Exp $ */
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/* $NetBSD: smc91cxxvar.h,v 1.11 2003/04/29 08:47:30 scw Exp $ */
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/*-
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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@ -63,6 +63,7 @@ struct smc91cxx_softc {
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#define SMC_FLAGS_32BIT_READ 0x0008 /* reads are always 32-bits */
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u_int8_t sc_chipid;
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u_int8_t sc_internal_phy; /* 91C111 only */
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#if NRND > 0
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rndsource_element_t rnd_source;
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