diff --git a/sys/arch/arm/marvell/armadaxpreg.h b/sys/arch/arm/marvell/armadaxpreg.h
index d8542c4aa654..5ab334855cdb 100644
--- a/sys/arch/arm/marvell/armadaxpreg.h
+++ b/sys/arch/arm/marvell/armadaxpreg.h
@@ -204,6 +204,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define ARMADAXP_IRQ_PEX11		63	/* PCIe Port1.1 INTA/B/C/D */
 #define ARMADAXP_IRQ_PEX12		64	/* PCIe Port1.2 INTA/B/C/D */
 #define ARMADAXP_IRQ_PEX13		65	/* PCIe Port1.3 INTA/B/C/D */
+#define ARMADAXP_IRQ_GBE0_SUM		66
 #define ARMADAXP_IRQ_XOR1CH2		94	/* XOR1 Ch2 */
 #define ARMADAXP_IRQ_XOR1CH3		95	/* XOR1 Ch3 */
 #define ARMADAXP_IRQ_PEX2		99	/* PCIe Port2 INTA/B/C/D */
@@ -278,18 +279,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define ARMADAXP_GPIO1_BASE	(MVSOC_DEVBUS_BASE + 0x8120)
 #define ARMADAXP_GPIO2_BASE	(MVSOC_DEVBUS_BASE + 0x8140)
 
-/*
- * Thermal Sensor and Thermal Managemer
- */
-#define ARMADAXP_TS_BASE	(MVSOC_DEVBUS_BASE + 0x82b0)
-#define ARMADAXP_TM_BASE	(MVSOC_DEVBUS_BASE + 0x84c0)
-#define ARMADA370_TM_BASE	(MVSOC_DEVBUS_BASE + 0x8300)
-
-/*
- * Power Management Unit Registers
- */				/* NS16550 compatible */
-#define ARMADAXP_PMU_BASE	(MVSOC_DEVBUS_BASE + 0xc000)
-
 /*
  * Miscellanseous Register
  */
@@ -303,7 +292,18 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define	ARMADAXP_MISC_SSRR		0x64	/* System Soft Reset Register */
 #define	ARMADAXP_MISC_SSRR_GLOBALSOFTRST	(1 << 0)
 
+/*
+ * Thermal Sensor and Thermal Managemer
+ */
+#define ARMADAXP_TS_BASE	(MVSOC_DEVBUS_BASE + 0x82b0)
+#define ARMADAXP_TM_BASE	(MVSOC_DEVBUS_BASE + 0x84c0)
+#define ARMADA370_TM_BASE	(MVSOC_DEVBUS_BASE + 0x8300)
+
 /* Multiprocessor Interrupt Controller Registers */
+#define ARMADAXP_MLMB_CFUCONFIG		  0x228
+#define ARMADAXP_MLMB_CFUCONFIG_POUTOSL2	(1 << 18)
+#define ARMADAXP_MLMB_CFUCONFIG_POCTOSL2	(1 << 18)
+
 #define	ARMADAXP_MLMB_MPIC_BASE			0x20a00
 #define	ARMADAXP_MLMB_MPIC_CPU_BASE		0x21800
 #define	ARMADAXP_MLMB_MPIC_CTRL			0x0
@@ -416,7 +416,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define ARMADAXP_USB1_BASE	(ARMADAXP_USB_BASE + 0x1000)
 #define ARMADAXP_USB2_BASE	(ARMADAXP_USB_BASE + 0x2000)
 
-/* 
+/*
  * XOR Engine Registers
  */
 #define ARMADAXP_XORE0_BASE	(UNITID2PHYS(XORE0))	/* 0x60000 */
@@ -435,7 +435,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #define ARMADAXP_PTP_BASE	(UNITID2PHYS(GBE0))	/* 0x7c000 */
 
-/* 
+/*
  * Cryptographic Engine and Security Accelerator Registers
  */
 #define ARMADAXP_CESA0_BASE	(UNITID2PHYS(CRYPT) + 0xd000)	/* 0x9d000 */