Add driver for 10/100/1000 copper PHY integrated on VIA Networking Technologies
VT6122 gigabit ethernet chips From FreeBSD
This commit is contained in:
jdolecek
parent
b1370d628b
commit
f8cfdfba75
403
sys/dev/mii/ciphy.c
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403
sys/dev/mii/ciphy.c
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@ -0,0 +1,403 @@
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/* $NetBSD: ciphy.c,v 1.1 2005/02/20 16:35:56 jdolecek Exp $ */
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/*-
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* Copyright (c) 2004
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* Bill Paul <wpaul@windriver.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* FreeBSD: src/sys/dev/mii/ciphy.c,v 1.2 2005/01/06 01:42:55 imp Exp
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ciphy.c,v 1.1 2005/02/20 16:35:56 jdolecek Exp $");
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/*
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* Driver for the Cicada CS8201 10/100/1000 copper PHY.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <machine/bus.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/miidevs.h>
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#include <dev/mii/ciphyreg.h>
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static int ciphy_match(struct device *, struct cfdata *, void *);
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static void ciphy_attach(struct device *, struct device *, void *);
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CFATTACH_DECL(ciphy, sizeof(struct mii_softc),
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ciphy_match, ciphy_attach, mii_phy_detach, mii_phy_activate);
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static int ciphy_service(struct mii_softc *, struct mii_data *, int);
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static void ciphy_status(struct mii_softc *);
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static void ciphy_reset(struct mii_softc *);
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static void ciphy_fixup(struct mii_softc *);
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static const struct mii_phy_funcs ciphy_funcs = {
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ciphy_service, ciphy_status, mii_phy_reset,
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};
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static int
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ciphy_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct mii_attach_args *ma = aux;
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if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA &&
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MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201) {
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return(1);
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}
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if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA &&
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MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201A) {
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return(1);
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}
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if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA &&
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MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201B) {
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return(1);
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}
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return(0);
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}
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static void
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ciphy_attach(struct device *parent, struct device *self, void *aux)
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{
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struct mii_softc *sc = (struct mii_softc *)self;
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struct mii_attach_args *ma = aux;
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struct mii_data *mii = ma->mii_data;
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_funcs = &ciphy_funcs;
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sc->mii_pdata = mii;
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sc->mii_flags = ma->mii_flags;
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sc->mii_anegticks = 5;
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sc->mii_flags |= MIIF_NOISOLATE;
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ciphy_reset(sc);
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sc->mii_capabilities =
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PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
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if (sc->mii_capabilities & BMSR_EXTSTAT)
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sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
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aprint_normal("%s: ", sc->mii_dev.dv_xname);
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if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0)
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aprint_error("no media present");
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else
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mii_phy_add_media(sc);
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aprint_normal("\n");
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}
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static int
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ciphy_service(sc, mii, cmd)
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struct mii_softc *sc;
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struct mii_data *mii;
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int cmd;
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int reg, speed, gig;
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switch (cmd) {
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case MII_POLLSTAT:
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/*
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* If we're not polling our PHY instance, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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reg = PHY_READ(sc, MII_BMCR);
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PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
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return (0);
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}
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/*
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* If the interface is not up, don't do anything.
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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ciphy_fixup(sc); /* XXX hardware bug work-around */
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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#ifdef foo
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/*
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* If we're already in auto mode, just return.
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*/
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if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
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return (0);
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#endif
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(void) mii_phy_auto(sc, 0);
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break;
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case IFM_1000_T:
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speed = CIPHY_S1000;
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goto setit;
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case IFM_100_TX:
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speed = CIPHY_S100;
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goto setit;
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case IFM_10_T:
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speed = CIPHY_S10;
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setit:
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if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
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speed |= CIPHY_BMCR_FDX;
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gig = CIPHY_1000CTL_AFD;
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} else {
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gig = CIPHY_1000CTL_AHD;
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}
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PHY_WRITE(sc, CIPHY_MII_1000CTL, 0);
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PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
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PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
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break;
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PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
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PHY_WRITE(sc, CIPHY_MII_BMCR,
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speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG);
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/*
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* When setting the link manually, one side must
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* be the master and the other the slave. However
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* ifmedia doesn't give us a good way to specify
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* this, so we fake it by using one of the LINK
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* flags. If LINK0 is set, we program the PHY to
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* be a master, otherwise it's a slave.
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*/
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if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
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PHY_WRITE(sc, CIPHY_MII_1000CTL,
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gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC);
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} else {
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PHY_WRITE(sc, CIPHY_MII_1000CTL,
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gig|CIPHY_1000CTL_MSE);
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}
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break;
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case IFM_NONE:
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PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
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break;
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case IFM_100_T4:
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default:
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return (EINVAL);
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}
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break;
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case MII_TICK:
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/*
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* If we're not currently selected, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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/*
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* Is the interface even up?
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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return (0);
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/*
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* Only used for autonegotiation.
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*/
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
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break;
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/*
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* Check to see if we have link. If we do, we don't
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* need to restart the autonegotiation process. Read
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* the BMSR twice in case it's latched.
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*/
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reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
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if (reg & BMSR_LINK)
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break;
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/*
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* Only retry autonegotiation every 5 seconds.
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*/
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if (++sc->mii_ticks <= 5/*10*/)
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break;
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sc->mii_ticks = 0;
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mii_phy_auto(sc, 0);
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return (0);
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}
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/* Update the media status. */
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ciphy_status(sc);
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/*
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* Callback if something changed. Note that we need to poke
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* apply fixups for certain PHY revs.
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*/
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if (sc->mii_media_active != mii->mii_media_active ||
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sc->mii_media_status != mii->mii_media_status ||
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cmd == MII_MEDIACHG) {
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ciphy_fixup(sc);
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}
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mii_phy_update(sc, cmd);
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return (0);
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}
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static void
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ciphy_status(sc)
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struct mii_softc *sc;
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{
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struct mii_data *mii = sc->mii_pdata;
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int bmsr, bmcr;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
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if (bmsr & BMSR_LINK)
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mii->mii_media_status |= IFM_ACTIVE;
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bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
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if (bmcr & CIPHY_BMCR_LOOP)
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mii->mii_media_active |= IFM_LOOP;
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if (bmcr & CIPHY_BMCR_AUTOEN) {
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if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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}
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bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
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switch (bmsr & CIPHY_AUXCSR_SPEED) {
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case CIPHY_SPEED10:
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mii->mii_media_active |= IFM_10_T;
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break;
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case CIPHY_SPEED100:
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mii->mii_media_active |= IFM_100_TX;
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break;
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case CIPHY_SPEED1000:
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mii->mii_media_active |= IFM_1000_T;
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break;
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default:
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printf("%s: unknown PHY speed %x\n",
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sc->mii_dev.dv_xname,
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bmsr & CIPHY_AUXCSR_SPEED);
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break;
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}
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if (bmsr & CIPHY_AUXCSR_FDX)
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mii->mii_media_active |= IFM_FDX;
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return;
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}
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static void
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ciphy_reset(struct mii_softc *sc)
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{
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mii_phy_reset(sc);
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DELAY(1000);
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return;
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}
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#define PHY_SETBIT(x, y, z) \
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PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
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#define PHY_CLRBIT(x, y, z) \
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PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
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static void
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ciphy_fixup(struct mii_softc *sc)
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{
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uint16_t model;
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uint16_t status, speed;
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model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
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status = PHY_READ(sc, CIPHY_MII_AUXCSR);
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speed = status & CIPHY_AUXCSR_SPEED;
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switch (model) {
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case MII_MODEL_CICADA_CS8201:
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/* Turn off "aux mode" (whatever that means) */
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PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
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/*
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* Work around speed polling bug in VT3119/VT3216
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* when using MII in full duplex mode.
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*/
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if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
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(status & CIPHY_AUXCSR_FDX)) {
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PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
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} else {
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PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
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}
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/* Enable link/activity LED blink. */
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PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
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break;
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case MII_MODEL_CICADA_CS8201A:
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case MII_MODEL_CICADA_CS8201B:
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/*
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* Work around speed polling bug in VT3119/VT3216
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* when using MII in full duplex mode.
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*/
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if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
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(status & CIPHY_AUXCSR_FDX)) {
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PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
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} else {
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PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
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}
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break;
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default:
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printf("%s: unknown CICADA PHY model %x\n",
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sc->mii_dev.dv_xname, model);
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break;
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}
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return;
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}
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353
sys/dev/mii/ciphyreg.h
Normal file
353
sys/dev/mii/ciphyreg.h
Normal file
@ -0,0 +1,353 @@
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/* $NetBSD: ciphyreg.h,v 1.1 2005/02/20 16:35:56 jdolecek Exp $ */
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/*-
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* Copyright (c) 2004
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* Bill Paul <wpaul@windriver.com>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* FreeBSD: src/sys/dev/mii/ciphyreg.h,v 1.2 2005/01/06 01:42:55 imp Exp
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*/
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#ifndef _DEV_MII_CIPHYREG_H_
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#define _DEV_MII_CIPHYREG_H_
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||||
|
||||
/*
|
||||
* Register definitions for the Cicada CS8201 10/100/1000 gigE copper
|
||||
* PHY, embedded within the VIA Networks VT6122 controller.
|
||||
*/
|
||||
|
||||
/* Command register */
|
||||
#define CIPHY_MII_BMCR 0x00
|
||||
#define CIPHY_BMCR_RESET 0x8000
|
||||
#define CIPHY_BMCR_LOOP 0x4000
|
||||
#define CIPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
|
||||
#define CIPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
|
||||
#define CIPHY_BMCR_PDOWN 0x0800 /* Power down */
|
||||
#define CIPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
|
||||
#define CIPHY_BMCR_FDX 0x0100 /* Duplex mode */
|
||||
#define CIPHY_BMCR_CTEST 0x0080 /* Collision test enable */
|
||||
#define CIPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
|
||||
|
||||
#define CIPHY_S1000 CIPHY_BMCR_SPD1 /* 1000mbps */
|
||||
#define CIPHY_S100 CIPHY_BMCR_SPD0 /* 100mpbs */
|
||||
#define CIPHY_S10 0 /* 10mbps */
|
||||
|
||||
/* Status register */
|
||||
#define CIPHY_MII_BMSR 0x01
|
||||
#define CIPHY_BMSR_100T4 0x8000 /* 100 base T4 capable */
|
||||
#define CIPHY_BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */
|
||||
#define CIPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */
|
||||
#define CIPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */
|
||||
#define CIPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */
|
||||
#define CIPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */
|
||||
#define CIPHY_BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */
|
||||
#define CIPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
|
||||
#define CIPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */
|
||||
#define CIPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
|
||||
#define CIPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
|
||||
#define CIPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
|
||||
#define CIPHY_BMSR_LINK 0x0004 /* Link status */
|
||||
#define CIPHY_BMSR_JABBER 0x0002 /* Jabber detected */
|
||||
#define CIPHY_BMSR_EXT 0x0001 /* Extended capability */
|
||||
|
||||
/* PHY ID registers */
|
||||
#define CIPHY_MII_PHYIDR1 0x02
|
||||
#define CIPHY_MII_PHYIDR2 0x03
|
||||
|
||||
/* Autoneg advertisement */
|
||||
#define CIPHY_MII_ANAR 0x04
|
||||
#define CIPHY_ANAR_NP 0x8000 /* Next page */
|
||||
#define CIPHY_ANAR_RF 0x2000 /* Remote fault */
|
||||
#define CIPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */
|
||||
#define CIPHY_ANAR_PC 0x0400 /* Pause capable */
|
||||
#define CIPHY_ANAR_T4 0x0200 /* local device supports 100bT4 */
|
||||
#define CIPHY_ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */
|
||||
#define CIPHY_ANAR_TX 0x0080 /* local device supports 100bTx */
|
||||
#define CIPHY_ANAR_10_FD 0x0040 /* local device supports 10bT FD */
|
||||
#define CIPHY_ANAR_10 0x0020 /* local device supports 10bT */
|
||||
#define CIPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */
|
||||
|
||||
/* Autoneg link partner ability */
|
||||
#define CIPHY_MII_ANLPAR 0x05
|
||||
#define CIPHY_ANLPAR_NP 0x8000 /* Next page */
|
||||
#define CIPHY_ANLPAR_ACK 0x4000 /* link partner acknowledge */
|
||||
#define CIPHY_ANLPAR_RF 0x2000 /* Remote fault */
|
||||
#define CIPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */
|
||||
#define CIPHY_ANLPAR_PC 0x0400 /* Pause capable */
|
||||
#define CIPHY_ANLPAR_T4 0x0200 /* link partner supports 100bT4 */
|
||||
#define CIPHY_ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */
|
||||
#define CIPHY_ANLPAR_TX 0x0080 /* link partner supports 100bTx */
|
||||
#define CIPHY_ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */
|
||||
#define CIPHY_ANLPAR_10 0x0020 /* link partner supports 10bT */
|
||||
#define CIPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */
|
||||
|
||||
#define CIPHY_SEL_TYPE 0x0001 /* ethernet */
|
||||
|
||||
/* Antoneg expansion register */
|
||||
#define CIPHY_MII_ANER 0x06
|
||||
#define CIPHY_ANER_PDF 0x0010 /* Parallel detection fault */
|
||||
#define CIPHY_ANER_LPNP 0x0008 /* Link partner can next page */
|
||||
#define CIPHY_ANER_NP 0x0004 /* Local PHY can next page */
|
||||
#define CIPHY_ANER_RX 0x0002 /* Next page received */
|
||||
#define CIPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */
|
||||
|
||||
/* Autoneg next page transmit regisyer */
|
||||
#define CIPHY_MII_NEXTP 0x07
|
||||
#define CIPHY_NEXTP_MOREP 0x8000 /* More pages to follow */
|
||||
#define CIPHY_NEXTP_MESS 0x2000 /* 1 = message page, 0 = unformatted */
|
||||
#define CIPHY_NEXTP_ACK2 0x1000 /* MAC acknowledge */
|
||||
#define CIPHY_NEXTP_TOGGLE 0x0800 /* Toggle */
|
||||
#define CIPHY_NEXTP_CODE 0x07FF /* Code bits */
|
||||
|
||||
/* Autoneg link partner next page receive register */
|
||||
#define CIPHY_MII_NEXTP_LP 0x08
|
||||
#define CIPHY_NEXTPLP_MOREP 0x8000 /* More pages to follow */
|
||||
#define CIPHY_NEXTPLP_MESS 0x2000 /* 1 = message page, 0 = unformatted */
|
||||
#define CIPHY_NEXTPLP_ACK2 0x1000 /* MAC acknowledge */
|
||||
#define CIPHY_NEXTPLP_TOGGLE 0x0800 /* Toggle */
|
||||
#define CIPHY_NEXTPLP_CODE 0x07FF /* Code bits */
|
||||
|
||||
/* 1000BT control register */
|
||||
#define CIPHY_MII_1000CTL 0x09
|
||||
#define CIPHY_1000CTL_TST 0xE000 /* test modes */
|
||||
#define CIPHY_1000CTL_MSE 0x1000 /* Master/Slave manual enable */
|
||||
#define CIPHY_1000CTL_MSC 0x0800 /* Master/Slave select */
|
||||
#define CIPHY_1000CTL_RD 0x0400 /* Repeater/DTE */
|
||||
#define CIPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */
|
||||
#define CIPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */
|
||||
|
||||
#define CIPHY_TEST_TX_JITTER 0x2000
|
||||
#define CIPHY_TEST_TX_JITTER_MASTER_MODE 0x4000
|
||||
#define CIPHY_TEST_TX_JITTER_SLAVE_MODE 0x6000
|
||||
#define CIPHY_TEST_TX_DISTORTION 0x8000
|
||||
|
||||
/* 1000BT status register */
|
||||
#define CIPHY_MII_1000STS 0x0A
|
||||
#define CIPHY_1000STS_MSF 0x8000 /* Master/slave fault */
|
||||
#define CIPHY_1000STS_MSR 0x4000 /* Master/slave result */
|
||||
#define CIPHY_1000STS_LRS 0x2000 /* Local receiver status */
|
||||
#define CIPHY_1000STS_RRS 0x1000 /* Remote receiver status */
|
||||
#define CIPHY_1000STS_LPFD 0x0800 /* Link partner can FD */
|
||||
#define CIPHY_1000STS_LPHD 0x0400 /* Link partner can HD */
|
||||
#define CIPHY_1000STS_IEC 0x00FF /* Idle error count */
|
||||
|
||||
#define CIPHY_MII_EXTSTS 0x0F /* Extended status */
|
||||
#define CIPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
|
||||
#define CIPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
|
||||
#define CIPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
|
||||
#define CIPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
|
||||
|
||||
/* 1000BT status extension register #1 */
|
||||
#define CIPHY_MII_1000STS1 0x0F
|
||||
#define CIPHY_1000STS1_1000XFDX 0x8000 /* 1000baseX FDX capable */
|
||||
#define CIPHY_1000STS1_1000XHDX 0x4000 /* 1000baseX HDX capable */
|
||||
#define CIPHY_1000STS1_1000TFDX 0x2000 /* 1000baseT FDX capable */
|
||||
#define CIPHY_1000STS1_1000THDX 0x1000 /* 1000baseT HDX capable */
|
||||
|
||||
/* Vendor-specific PHY registers */
|
||||
|
||||
/* 100baseTX status extention register */
|
||||
#define CIPHY_MII_100STS 0x10
|
||||
#define CIPHY_100STS_DESLCK 0x8000 /* descrambler locked */
|
||||
#define CIPHY_100STS_LKCERR 0x4000 /* lock error detected/lock lost */
|
||||
#define CIPHY_100STS_DISC 0x2000 /* disconnect state */
|
||||
#define CIPHY_100STS_LINK 0x1000 /* current link state */
|
||||
#define CIPHY_100STS_RXERR 0x0800 /* receive error detected */
|
||||
#define CIPHY_100STS_TXERR 0x0400 /* transmit error detected */
|
||||
#define CIPHY_100STS_SSDERR 0x0200 /* false carrier error detected */
|
||||
#define CIPHY_100STS_ESDERR 0x0100 /* premature end of stream error */
|
||||
|
||||
/* 1000BT status extention register #2 */
|
||||
#define CIPHY_MII_1000STS2 0x11
|
||||
#define CIPHY_1000STS2_DESLCK 0x8000 /* descrambler locked */
|
||||
#define CIPHY_1000STS2_LKCERR 0x4000 /* lock error detected/lock lost */
|
||||
#define CIPHY_1000STS2_DISC 0x2000 /* disconnect state */
|
||||
#define CIPHY_1000STS2_LINK 0x1000 /* current link state */
|
||||
#define CIPHY_1000STS2_RXERR 0x0800 /* receive error detected */
|
||||
#define CIPHY_1000STS2_TXERR 0x0400 /* transmit error detected */
|
||||
#define CIPHY_1000STS2_SSDERR 0x0200 /* false carrier error detected */
|
||||
#define CIPHY_1000STS2_ESDERR 0x0100 /* premature end of stream error */
|
||||
#define CIPHY_1000STS2_CARREXT 0x0080 /* carrier extention err detected */
|
||||
#define CIPHY_1000STS2_BCM5400 0x0040 /* non-complient BCM5400 detected */
|
||||
|
||||
/* Bypass control register */
|
||||
#define CIPHY_MII_BYPASS 0x12
|
||||
#define CIPHY_BYPASS_TX 0x8000 /* transmit disable */
|
||||
#define CIPHY_BYPASS_4B5B 0x4000 /* bypass the 4B5B encoder */
|
||||
#define CIPHY_BYPASS_SCRAM 0x2000 /* bypass scrambler */
|
||||
#define CIPHY_BYPASS_DSCAM 0x1000 /* bypass descrambler */
|
||||
#define CIPHY_BYPASS_PCSRX 0x0800 /* bypass PCS receive */
|
||||
#define CIPHY_BYPASS_PCSTX 0x0400 /* bypass PCS transmit */
|
||||
#define CIPHY_BYPASS_LFI 0x0200 /* bypass LFI timer */
|
||||
#define CIPHY_BYPASS_TXCLK 0x0100 /* enable transmit clock on LED4 pin */
|
||||
#define CIPHY_BYPASS_BCM5400_F 0x0080 /* force BCM5400 detect */
|
||||
#define CIPHY_BYPASS_BCM5400 0x0040 /* bypass BCM5400 detect */
|
||||
#define CIPHY_BYPASS_PAIRSWAP 0x0020 /* disable automatic pair swap */
|
||||
#define CIPHY_BYPASS_POLARITY 0x0010 /* disable polarity correction */
|
||||
#define CIPHY_BYPASS_PARALLEL 0x0008 /* parallel detect enable */
|
||||
#define CIPHY_BYPASS_PULSE 0x0004 /* disable pulse shaping filter */
|
||||
#define CIPHY_BYPASS_1000BNP 0x0002 /* disable 1000BT next page exchange */
|
||||
|
||||
/* RX error count register */
|
||||
#define CIPHY_MII_RXERR 0x13
|
||||
|
||||
/* False carrier sense count register */
|
||||
#define CIPHY_MII_FCSERR 0x14
|
||||
|
||||
/* Ddisconnect error counter */
|
||||
#define CIPHY_MII_DISCERR 0x15
|
||||
|
||||
/* 10baseT control/status register */
|
||||
#define CIPHY_MII_10BTCSR 0x16
|
||||
#define CIPHY_10BTCSR_DLIT 0x8000 /* Disable data link integrity test */
|
||||
#define CIPHY_10BTCSR_JABBER 0x4000 /* Disable jabber detect */
|
||||
#define CIPHY_10BTCSR_ECHO 0x2000 /* Disable echo mode */
|
||||
#define CIPHY_10BTCSR_SQE 0x1000 /* Disable signal quality error */
|
||||
#define CIPHY_10BTCSR_SQUENCH 0x0C00 /* Squelch control */
|
||||
#define CIPHY_10BTCSR_EOFERR 0x0100 /* End of Frame error */
|
||||
#define CIPHY_10BTCSR_DISC 0x0080 /* Disconnect status */
|
||||
#define CIPHY_10BTCSR_LINK 0x0040 /* current link state */
|
||||
#define CIPHY_10BTCSR_ITRIM 0x0038 /* current reference trim */
|
||||
#define CIPHY_10BTCSR_CSR 0x0006 /* CSR behavior control */
|
||||
|
||||
#define CIPHY_SQUELCH_300MV 0x0000
|
||||
#define CIPHY_SQUELCH_197MV 0x0400
|
||||
#define CIPHY_SQUELCH_450MV 0x0800
|
||||
#define CIPHY_SQUELCH_RSVD 0x0C00
|
||||
|
||||
#define CIPHY_ITRIM_PLUS2 0x0000
|
||||
#define CIPHY_ITRIM_PLUS4 0x0008
|
||||
#define CIPHY_ITRIM_PLUS6 0x0010
|
||||
#define CIPHY_ITRIM_PLUS6_ 0x0018
|
||||
#define CIPHY_ITRIM_MINUS4 0x0020
|
||||
#define CIPHY_ITRIM_MINUS4_ 0x0028
|
||||
#define CIPHY_ITRIM_MINUS2 0x0030
|
||||
#define CIPHY_ITRIM_ZERO 0x0038
|
||||
|
||||
/* Extended PHY control register #1 */
|
||||
#define CIPHY_MII_ECTL1 0x17
|
||||
#define CIPHY_ECTL1_ACTIPHY 0x0020 /* Enable ActiPHY power saving */
|
||||
|
||||
/* Extended PHY control register #2 */
|
||||
#define CIPHY_MII_ECTL2 0x18
|
||||
#define CIPHY_ECTL2_ERATE 0xE000 /* 10/1000 edge rate control */
|
||||
#define CIPHY_ECTL2_VTRIM 0x1C00 /* voltage reference trim */
|
||||
#define CIPHY_ECTL2_CABLELEN 0x000E /* Cable quality/length */
|
||||
#define CIPHY_ECTL2_ANALOGLOOP 0x0001 /* 1000BT analog loopback */
|
||||
|
||||
#define CIPHY_CABLELEN_0TO10M 0x0000
|
||||
#define CIPHY_CABLELEN_10TO20M 0x0002
|
||||
#define CIPHY_CABLELEN_20TO40M 0x0004
|
||||
#define CIPHY_CABLELEN_40TO80M 0x0006
|
||||
#define CIPHY_CABLELEN_80TO100M 0x0008
|
||||
#define CIPHY_CABLELEN_100TO140M 0x000A
|
||||
#define CIPHY_CABLELEN_140TO180M 0x000C
|
||||
#define CIPHY_CABLELEN_OVER180M 0x000E
|
||||
|
||||
/* Interrupt mask register */
|
||||
#define CIPHY_MII_IMR 0x19
|
||||
#define CIPHY_IMR_PINENABLE 0x8000 /* Interrupt pin enable */
|
||||
#define CIPHY_IMR_SPEED 0x4000 /* speed changed event */
|
||||
#define CIPHY_IMR_LINK 0x2000 /* link change/ActiPHY event */
|
||||
#define CIPHY_IMR_DPX 0x1000 /* duplex change event */
|
||||
#define CIPHY_IMR_ANEGERR 0x0800 /* autoneg error event */
|
||||
#define CIPHY_IMR_ANEGDONE 0x0400 /* autoneg done event */
|
||||
#define CIPHY_IMR_NPRX 0x0200 /* page received event */
|
||||
#define CIPHY_IMR_SYMERR 0x0100 /* symbol error event */
|
||||
#define CIPHY_IMR_LOCKERR 0x0080 /* descrambler lock lost event */
|
||||
#define CIPHY_IMR_XOVER 0x0040 /* MDI crossover change event */
|
||||
#define CIPHY_IMR_POLARITY 0x0020 /* polarity change event */
|
||||
#define CIPHY_IMR_JABBER 0x0010 /* jabber detect event */
|
||||
#define CIPHY_IMR_SSDERR 0x0008 /* false carrier detect event */
|
||||
#define CIPHY_IMR_ESDERR 0x0004 /* parallel detect error event */
|
||||
#define CIPHY_IMR_MASTERSLAVE 0x0002 /* master/slave resolve done event */
|
||||
#define CIPHY_IMR_RXERR 0x0001 /* RX error event */
|
||||
|
||||
/* Interrupt status register */
|
||||
#define CIPHY_MII_ISR 0x1A
|
||||
#define CIPHY_ISR_IPENDING 0x8000 /* Interrupt is pending */
|
||||
#define CIPHY_ISR_SPEED 0x4000 /* speed changed event */
|
||||
#define CIPHY_ISR_LINK 0x2000 /* link change/ActiPHY event */
|
||||
#define CIPHY_ISR_DPX 0x1000 /* duplex change event */
|
||||
#define CIPHY_ISR_ANEGERR 0x0800 /* autoneg error event */
|
||||
#define CIPHY_ISR_ANEGDONE 0x0400 /* autoneg done event */
|
||||
#define CIPHY_ISR_NPRX 0x0200 /* page received event */
|
||||
#define CIPHY_ISR_SYMERR 0x0100 /* symbol error event */
|
||||
#define CIPHY_ISR_LOCKERR 0x0080 /* descrambler lock lost event */
|
||||
#define CIPHY_ISR_XOVER 0x0040 /* MDI crossover change event */
|
||||
#define CIPHY_ISR_POLARITY 0x0020 /* polarity change event */
|
||||
#define CIPHY_ISR_JABBER 0x0010 /* jabber detect event */
|
||||
#define CIPHY_ISR_SSDERR 0x0008 /* false carrier detect event */
|
||||
#define CIPHY_ISR_ESDERR 0x0004 /* parallel detect error event */
|
||||
#define CIPHY_ISR_MASTERSLAVE 0x0002 /* master/slave resolve done event */
|
||||
#define CIPHY_ISR_RXERR 0x0001 /* RX error event */
|
||||
|
||||
/* LED control register */
|
||||
#define CIPHY_MII_LED 0x1B
|
||||
#define CIPHY_LED_LINK10FORCE 0x8000 /* Force on link10 LED */
|
||||
#define CIPHY_LED_LINK10DIS 0x4000 /* Disable link10 LED */
|
||||
#define CIPHY_LED_LINK100FORCE 0x2000 /* Force on link10 LED */
|
||||
#define CIPHY_LED_LINK100DIS 0x1000 /* Disable link100 LED */
|
||||
#define CIPHY_LED_LINK1000FORCE 0x0800 /* Force on link1000 LED */
|
||||
#define CIPHY_LED_LINK1000DIS 0x0400 /* Disable link1000 LED */
|
||||
#define CIPHY_LED_FDXFORCE 0x0200 /* Force on duplex LED */
|
||||
#define CIPHY_LED_FDXDIS 0x0100 /* Disable duplex LED */
|
||||
#define CIPHY_LED_ACTFORCE 0x0080 /* Force on activity LED */
|
||||
#define CIPHY_LED_ACTDIS 0x0040 /* Disable activity LED */
|
||||
#define CIPHY_LED_PULSE 0x0008 /* LED pulse enable */
|
||||
#define CIPHY_LED_LINKACTBLINK 0x0004 /* enable link/activity LED blink */
|
||||
#define CIPHY_LED_BLINKRATE 0x0002 /* blink rate 0=10hz, 1=5hz */
|
||||
|
||||
/* Auxilliary control and status register */
|
||||
#define CIPHY_MII_AUXCSR 0x1C
|
||||
#define CIPHY_AUXCSR_ANEGDONE 0x8000 /* Autoneg complete */
|
||||
#define CIPHY_AUXCSR_ANEGOFF 0x4000 /* Autoneg disabled */
|
||||
#define CIPHY_AUXCSR_XOVER 0x2000 /* MDI/MDI-X crossover indication */
|
||||
#define CIPHY_AUXCSR_PAIRSWAP 0x1000 /* pair swap indication */
|
||||
#define CIPHY_AUXCSR_APOLARITY 0x0800 /* polarity inversion pair A */
|
||||
#define CIPHY_AUXCSR_BPOLARITY 0x0400 /* polarity inversion pair B */
|
||||
#define CIPHY_AUXCSR_CPOLARITY 0x0200 /* polarity inversion pair C */
|
||||
#define CIPHY_AUXCSR_DPOLARITY 0x0100 /* polarity inversion pair D */
|
||||
#define CIPHY_AUXCSR_FDX 0x0020 /* duplex 1=full, 0=half */
|
||||
#define CIPHY_AUXCSR_SPEED 0x0018 /* speed */
|
||||
#define CIPHY_AUXCSR_MDPPS 0x0004 /* No idea, not documented */
|
||||
#define CIPHY_AUXCSR_STICKYREST 0x0002 /* reset clears sticky bits */
|
||||
|
||||
#define CIPHY_SPEED10 0x0000
|
||||
#define CIPHY_SPEED100 0x0008
|
||||
#define CIPHY_SPEED1000 0x0010
|
||||
|
||||
/* Delay skew status register */
|
||||
#define CIPHY_MII_DSKEW 0x1D
|
||||
#define CIPHY_DSKEW_PAIRA 0x7000 /* Pair A skew in symbol times */
|
||||
#define CIPHY_DSKEW_PAIRB 0x0700 /* Pair B skew in symbol times */
|
||||
#define CIPHY_DSKEW_PAIRC 0x0070 /* Pair C skew in symbol times */
|
||||
#define CIPHY_DSKEW_PAIRD 0x0007 /* Pair D skew in symbol times */
|
||||
|
||||
#endif /* _DEV_CIPHY_MIIREG_H_ */
|
||||
@ -1,4 +1,4 @@
|
||||
# $NetBSD: files.mii,v 1.35 2004/12/30 23:03:19 jonathan Exp $
|
||||
# $NetBSD: files.mii,v 1.36 2005/02/20 16:35:56 jdolecek Exp $
|
||||
|
||||
defflag opt_mii.h MIIVERBOSE
|
||||
|
||||
@ -113,3 +113,7 @@ file dev/mii/urlphy.c urlphy
|
||||
device ukphy: mii_phy, ukphy_subr
|
||||
attach ukphy at mii
|
||||
file dev/mii/ukphy.c ukphy
|
||||
|
||||
device ciphy: mii_phy
|
||||
attach ciphy at mii
|
||||
file dev/mii/ciphy.c ciphy
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
$NetBSD: miidevs,v 1.56 2005/01/17 13:16:19 scw Exp $
|
||||
$NetBSD: miidevs,v 1.57 2005/02/20 16:35:56 jdolecek Exp $
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
|
||||
@ -55,6 +55,7 @@ $NetBSD: miidevs,v 1.56 2005/01/17 13:16:19 scw Exp $
|
||||
oui ALTIMA 0x0010a9 Altima Communications
|
||||
oui AMD 0x00001a Advanced Micro Devices
|
||||
oui BROADCOM 0x001018 Broadcom Corporation
|
||||
oui CICADA 0x0003F1 Cicada Semiconductor
|
||||
oui DAVICOM 0x00606e Davicom Semiconductor
|
||||
oui ENABLESEMI 0x0010dd Enable Semiconductor
|
||||
oui ICS 0x00a0be Integrated Circuit Systems
|
||||
@ -134,6 +135,11 @@ model BROADCOM BCM5704 0x0019 BCM5704 1000BASE-T media interface
|
||||
model BROADCOM BCM5705 0x001a BCM5705 1000BASE-T media interface
|
||||
model BROADCOM BCM5750 0x0018 BCM5750 1000BASE-T media interface
|
||||
|
||||
/* Cicada Semiconductor PHYs (now owned by Vitesse?) */
|
||||
model CICADA CS8201 0x0001 Cicada CS8201 10/100/1000TX PHY
|
||||
model CICADA CS8201A 0x0020 Cicada CS8201 10/100/1000TX PHY
|
||||
model CICADA CS8201B 0x0021 Cicada CS8201 10/100/1000TX PHY
|
||||
|
||||
/* Davicom Semiconductor PHYs */
|
||||
/* AMD Am79C873 seems to be a relabeled DM9101 */
|
||||
model xxDAVICOM DM9101 0x0000 DM9101 (AMD Am79C873) 10/100 media interface
|
||||
|
||||
Loading…
Reference in New Issue
Block a user