Support Kirkwood's GbE.
This commit is contained in:
kiyohara
parent
d7b57ebb2b
commit
f876f061d1
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@ -1,4 +1,4 @@
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/* $NetBSD: if_mvgbe.c,v 1.2 2010/07/11 08:43:36 kiyohara Exp $ */
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/* $NetBSD: if_mvgbe.c,v 1.3 2010/10/02 05:57:42 kiyohara Exp $ */
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/*
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* Copyright (c) 2007, 2008 KIYOHARA Takashi
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* All rights reserved.
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@ -25,7 +25,7 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.2 2010/07/11 08:43:36 kiyohara Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.3 2010/10/02 05:57:42 kiyohara Exp $");
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#include "rnd.h"
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@ -180,11 +180,13 @@ struct mvgbec_softc {
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bus_space_handle_t sc_ioh;
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kmutex_t sc_mtx;
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int sc_fix_tqtb;
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};
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struct mvgbe_softc {
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device_t sc_dev;
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int sc_port; /* port num (0 or 1) */
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int sc_port;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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@ -267,23 +269,39 @@ CFATTACH_DECL_NEW(mvgbe, sizeof(struct mvgbe_softc),
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struct mvgbe_port {
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int model;
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int unit;
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int ports;
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int irqs[4];
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int irqs[3];
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int flags;
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#define FLAGS_FIX_TQTB (1 << 0)
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} mvgbe_ports[] = {
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{ MARVELL_DISCOVERY_II, 3, { 32, 33, 34 } },
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{ MARVELL_DISCOVERY_III, 3, { 32, 33, 34 } },
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{ MARVELL_DISCOVERY_II, 0, 3, { 32, 33, 34 }, 0 },
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{ MARVELL_DISCOVERY_III, 0, 3, { 32, 33, 34 }, 0 },
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#if 0
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{ MARVELL_DISCOVERY_LT, ?, { } },
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{ MARVELL_DISCOVERY_V, ?, { } },
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{ MARVELL_DISCOVERY_VI, ?, { } },
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{ MARVELL_DISCOVERY_LT, 0, ?, { }, 0 },
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{ MARVELL_DISCOVERY_V, 0, ?, { }, 0 },
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{ MARVELL_DISCOVERY_VI, 0, ?, { }, 0 },
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#endif
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{ MARVELL_ORION_1_88F5082, 1, { 21 } },
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{ MARVELL_ORION_1_88F5180N, 1, { 21 } },
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{ MARVELL_ORION_1_88F5181, 1, { 21 } },
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{ MARVELL_ORION_1_88F5182, 1, { 21 } },
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{ MARVELL_ORION_2_88F5281, 1, { 21 } },
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{ MARVELL_ORION_1_88F6082, 1, { 21 } },
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{ MARVELL_ORION_1_88W8660, 1, { 21 } },
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{ MARVELL_ORION_1_88F5082, 0, 1, { 21 }, 0 },
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{ MARVELL_ORION_1_88F5180N, 0, 1, { 21 }, 0 },
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{ MARVELL_ORION_1_88F5181, 0, 1, { 21 }, 0 },
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{ MARVELL_ORION_1_88F5182, 0, 1, { 21 }, 0 },
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{ MARVELL_ORION_2_88F5281, 0, 1, { 21 }, 0 },
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{ MARVELL_ORION_1_88F6082, 0, 1, { 21 }, 0 },
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{ MARVELL_ORION_1_88W8660, 0, 1, { 21 }, 0 },
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{ MARVELL_KIRKWOOD_88F6180, 0, 1, { 11 }, FLAGS_FIX_TQTB },
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{ MARVELL_KIRKWOOD_88F6192, 0, 1, { 11 }, FLAGS_FIX_TQTB },
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{ MARVELL_KIRKWOOD_88F6192, 1, 1, { 14 }, FLAGS_FIX_TQTB },
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{ MARVELL_KIRKWOOD_88F6281, 0, 1, { 11 }, FLAGS_FIX_TQTB },
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{ MARVELL_KIRKWOOD_88F6281, 1, 1, { 14 }, FLAGS_FIX_TQTB },
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{ MARVELL_MV78XX0_MV78100, 0, 1, { 40 }, FLAGS_FIX_TQTB },
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{ MARVELL_MV78XX0_MV78100, 1, 1, { 44 }, FLAGS_FIX_TQTB },
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{ MARVELL_MV78XX0_MV78200, 0, 1, { 40 }, FLAGS_FIX_TQTB },
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{ MARVELL_MV78XX0_MV78200, 1, 1, { 44 }, FLAGS_FIX_TQTB },
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{ MARVELL_MV78XX0_MV78200, 2, 1, { 48 }, FLAGS_FIX_TQTB },
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{ MARVELL_MV78XX0_MV78200, 3, 1, { 52 }, FLAGS_FIX_TQTB },
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};
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@ -296,7 +314,6 @@ mvgbec_match(device_t parent, struct cfdata *match, void *aux)
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if (strcmp(mva->mva_name, match->cf_name) != 0)
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return 0;
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if (mva->mva_offset == MVA_OFFSET_DEFAULT)
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return 0;
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@ -343,9 +360,12 @@ mvgbec_attach(device_t parent, device_t self, void *aux)
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memset(&gbea, 0, sizeof(gbea));
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for (i = 0; i < __arraycount(mvgbe_ports); i++) {
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if (mvgbe_ports[i].model != mva->mva_model)
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if (mvgbe_ports[i].model != mva->mva_model ||
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mvgbe_ports[i].unit != mva->mva_unit)
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continue;
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sc->sc_fix_tqtb = mvgbe_ports[i].flags & FLAGS_FIX_TQTB;
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for (j = 0; j < mvgbe_ports[i].ports; j++) {
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gbea.mva_name = "mvgbe";
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gbea.mva_model = mva->mva_model;
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@ -362,6 +382,7 @@ mvgbec_attach(device_t parent, device_t self, void *aux)
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phyaddr |= MVGBE_PHYADDR_PHYAD(j, mii->mii_phy);
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}
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}
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break;
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}
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MVGBE_WRITE(sc, MVGBE_PHYADDR, phyaddr);
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}
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@ -919,8 +940,9 @@ static int
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mvgbe_init(struct ifnet *ifp)
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{
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struct mvgbe_softc *sc = ifp->if_softc;
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struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev));
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struct mii_data *mii = &sc->sc_mii;
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uint32_t reg, val;
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uint32_t reg;
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int i, s;
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DPRINTFN(2, ("mvgbe_init\n"));
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@ -959,20 +981,33 @@ mvgbe_init(struct ifnet *ifp)
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MVGBE_PSC_FLFAIL | /* Do NOT Force Link Fail */
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MVGBE_PSC_MRU(MVGBE_PSC_MRU_9700) | /* Always 9700 OK */
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MVGBE_PSC_SETFULLDX); /* Set_FullDx */
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/* XXXX: mvgbe(4) always use RGMII. */
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MVGBE_WRITE(sc, MVGBE_PSC1,
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MVGBE_READ(sc, MVGBE_PSC1) | MVGBE_PSC1_RGMIIEN);
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/* XXXX: Also always Weighted Round-Robin Priority Mode */
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MVGBE_WRITE(sc, MVGBE_TQFPC, MVGBE_TQFPC_EN(0));
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MVGBE_WRITE(sc, MVGBE_CRDP(0), MVGBE_RX_RING_ADDR(sc, 0));
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MVGBE_WRITE(sc, MVGBE_TCQDP, MVGBE_TX_RING_ADDR(sc, 0));
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val = 0x3fffffff;
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for (i = 0; i < 8; i++) {
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if (csc->sc_fix_tqtb) {
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/*
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* Queue 0 must be programmed to 0x3fffffff. Queue 1 through 7
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* must be programmed to 0x00000000.
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* Queue 0 (offset 0x72700) must be programmed to 0x3fffffff.
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* And offset 0x72704 must be programmed to 0x03ffffff.
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* Queue 1 through 7 must be programmed to 0x0.
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*/
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MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), val);
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MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), val);
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val = 0x00000000;
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}
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MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(0), 0x3fffffff);
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MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(0), 0x03ffffff);
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for (i = 1; i < 8; i++) {
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MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x0);
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MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0x0);
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}
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} else
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for (i = 1; i < 8; i++) {
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MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x3fffffff);
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MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0xffff7fff);
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MVGBE_WRITE(sc, MVGBE_TQAC(i), 0xfc0000ff);
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}
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MVGBE_WRITE(sc, MVGBE_PXC, MVGBE_PXC_RXCS);
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MVGBE_WRITE(sc, MVGBE_PXCX, 0);
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@ -1291,7 +1326,7 @@ mvgbe_newbuf(struct mvgbe_softc *sc, int i, struct mbuf *m,
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r->bufsize = MVGBE_JLEN & ~MVGBE_BUF_MASK;
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r->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_ENABLE_INTERRUPT;
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MVGBE_CDRXSYNC(sc, i, BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
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MVGBE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
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return 0;
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}
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@ -1554,7 +1589,7 @@ mvgbe_encap(struct mvgbe_softc *sc, struct mbuf *m_head,
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/* Sync descriptors before handing to chip */
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MVGBE_CDTXSYNC(sc, *txidx, txmap->dm_nsegs,
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BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
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BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
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sc->sc_cdata.mvgbe_tx_cnt += i;
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*txidx = current;
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@ -1,4 +1,4 @@
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/* $NetBSD: mvgbereg.h,v 1.1 2010/06/02 06:18:11 kiyohara Exp $ */
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/* $NetBSD: mvgbereg.h,v 1.2 2010/10/02 05:57:42 kiyohara Exp $ */
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/*
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* Copyright (c) 2007 KIYOHARA Takashi
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* All rights reserved.
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@ -76,10 +76,11 @@
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#define MVGBE_MACAH 0x018 /* MAC Address High */
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#define MVGBE_SDC 0x01c /* SDMA Configuration */
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#define MVGBE_DSCP(n) (0x020 + ((n) << 2))
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#define MVGBE_PSC 0x03c
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#define MVGBE_PSC 0x03c /* Port Serial Control0 */
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#define MVGBE_VPT2P 0x040 /* VLAN Priority Tag to Priority */
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#define MVGBE_PS 0x044 /* Ethernet Port Status */
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#define MVGBE_TQC 0x048 /* Transmit Queue Command */
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#define MVGBE_PSC1 0x04c /* Port Serial Control1 */
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#define MVGBE_MTU 0x058 /* Max Transmit Unit */
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#define MVGBE_IC 0x060 /* Port Interrupt Cause */
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#define MVGBE_ICE 0x064 /* Port Interrupt Cause Extend */
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@ -91,6 +92,7 @@
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#define MVGBE_PXDFC 0x084 /* Port Rx Discard Frame Counter */
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#define MVGBE_POFC 0x088 /* Port Overrun Frame Counter */
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#define MVGBE_PIAE 0x094 /* Port Internal Address Error */
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#define MVGBE_TQFPC 0x0dc /* Transmit Queue Fixed Priority Cfg */
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#define MVGBE_CRDP(n) (0x20c + ((n) << 4))
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/* Ethernet Current Receive Descriptor Pointers */
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#define MVGBE_RQC 0x280 /* Receive Queue Command */
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@ -282,6 +284,11 @@
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#define MVGBE_TQC_ENQ (1 << 0) /* Enable Q */
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#define MVGBE_TQC_DISQ (1 << 8) /* Disable Q */
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/* Port Serial Control 1 (MVGBE_PSC1) */
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#define MVGBE_PSC1_PCSLB (1 << 1)
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#define MVGBE_PSC1_RGMIIEN (1 << 3) /* RGMII */
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#define MVGBE_PSC1_PRST (1 << 4) /* Port Reset */
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/* Port Interrupt Cause (MVGBE_IC) */
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#define MVGBE_IC_RXBUF (1 << 0)
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#define MVGBE_IC_EXTEND (1 << 1)
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@ -307,6 +314,9 @@
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#define MVGBE_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c)
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/* RxMFS = 40,44,48,52,56,60,64 bytes */
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/* Transmit Queue Fixed Priority Configuration */
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#define MVGBE_TQFPC_EN(q) (1 << (q))
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/* Receive Queue Command (MVGBE_RQC) */
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#define MVGBE_RQC_ENQ_MASK (0xff << 0) /* Enable Q */
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#define MVGBE_RQC_ENQ(n) (1 << (0 + (n)))
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