Flesh out allwinner support.
This commit is contained in:
matt
parent
8bfbe2803e
commit
f85d39dabc
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@ -31,8 +31,9 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: awin_ahcisata.c,v 1.2 2013/09/04 09:09:25 jmcneill Exp $");
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__KERNEL_RCSID(1, "$NetBSD: awin_ahcisata.c,v 1.3 2013/09/07 00:35:52 matt Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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@ -71,6 +72,38 @@ awin_ahci_match(device_t parent, cfdata_t cf, void *aux)
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return 1;
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}
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static void inline
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awin_ahci_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh,
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bus_size_t o, uint32_t set_mask, uint32_t clr_mask)
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{
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const uint32_t old = bus_space_read_4(bst, bsh, o);
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const uint32_t new = set_mask | (old & ~clr_mask);
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if (old != new) {
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bus_space_write_4(bst, bsh, o, new);
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}
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}
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static void
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awin_ahci_enable(bus_space_tag_t bst, bus_space_handle_t bsh)
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{
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/*
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* SATA needs PLL6 to be a 100MHz clock.
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*/
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awin_pll6_enable();
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/*
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* Make sure it's enabled for the AHB.
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*/
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awin_ahci_set_clear(bst, bsh, AWIN_AHB_GATING0_REG,
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AWIN_AHB_GATING0_SATA, 0);
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delay(10000);
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/*
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* Now turn it on.
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*/
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bus_space_write_4(bst, bsh, AWIN_SATA_CLK_REG, AWIN_CLK_ENABLE);
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}
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static void
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awin_ahci_attach(device_t parent, device_t self, void *aux)
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{
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@ -79,6 +112,8 @@ awin_ahci_attach(device_t parent, device_t self, void *aux)
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struct awinio_attach_args * const aio = aux;
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const struct awin_locators * const loc = &aio->aio_loc;
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awin_ahci_enable(aio->aio_core_bst, aio->aio_ccm_bsh);
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sc->sc_atac.atac_dev = self;
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sc->sc_dmat = aio->aio_dmat;
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sc->sc_ahcit = aio->aio_core_bst;
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@ -1,4 +1,4 @@
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/* $NetBSD: awin_board.c,v 1.2 2013/09/04 17:45:40 matt Exp $ */
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/* $NetBSD: awin_board.c,v 1.3 2013/09/07 00:35:52 matt Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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@ -34,7 +34,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.2 2013/09/04 17:45:40 matt Exp $");
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__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.3 2013/09/07 00:35:52 matt Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -64,7 +64,7 @@ struct arm32_bus_dma_tag awin_dma_tag = {
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#include <dev/ic/comreg.h>
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#include <dev/cons.h>
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static volatile uin32t_t *uart_base;
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static volatile uint32_t *uart_base;
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static int
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awin_cngetc(dev_t dv)
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@ -95,7 +95,7 @@ static struct consdev awin_earlycons = {
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.cn_getc = awin_cngetc,
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.cn_pollc = nullcnpollc,
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};
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#endif /* BCM53XX_CONSOLE_EARLY */
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#endif /* AWIN_CONSOLE_EARLY */
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static void
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awin_cpu_clk(void)
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@ -104,7 +104,7 @@ awin_cpu_clk(void)
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const uint32_t cpu0_cfg = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
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AWIN_CCM_OFFSET + AWIN_CPU_AHB_APB0_CFG_REG);
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const u_int cpu_clk_sel = __SHIFTIN(cpu0_cfg, AWIN_CPU_CLK_SRC_SEL);
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switch (cpu_clk_sel) {
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switch (__SHIFTOUT(cpu_clk_sel, AWIN_CPU_CLK_SRC_SEL)) {
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case AWIN_CPU_CLK_SRC_SEL_LOSC:
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ci->ci_data.cpu_cc_freq = 32768;
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break;
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@ -119,7 +119,7 @@ awin_cpu_clk(void)
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u_int k = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_K) + 1;
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u_int m = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_M) + 1;
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ci->ci_data.cpu_cc_freq =
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(AWIN_REF_FREQ * (n ? n : 1) * k / m) >> p;
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((uint64_t)AWIN_REF_FREQ * (n ? n : 1) * k / m) >> p;
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break;
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}
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case AWIN_CPU_CLK_SRC_SEL_200MHZ:
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@ -136,16 +136,23 @@ awin_bootstrap(vaddr_t iobase, vaddr_t uartbase)
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#ifdef AWIN_CONSOLE_EARLY
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uart_base = (volatile uint32_t *)uartbase;
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cn_tab = &awin_earlycons;
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printf("Early console started\n");
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#endif
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error = bus_space_map(&awin_bs_tag, AWIN_CORE_PBASE,
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AWIN_CORE_SIZE, 0, &awin_core_bsh);
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if (error)
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panic("%s: failed to map BCM53xx %s registers: %d",
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panic("%s: failed to map a[12]0 %s registers: %d",
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__func__, "io", error);
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KASSERT(awin_core_bsh == iobase);
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printf("CPU Speed is");
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awin_cpu_clk();
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printf(" %"PRIu64"\n", curcpu()->ci_data.cpu_cc_freq);
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printf("Determining GPIO configuration");
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awin_gpio_init();
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printf("\n");
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}
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#ifdef MULTIPROCESSOR
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@ -170,3 +177,29 @@ awin_memprobe(void)
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#endif
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return memsize;
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}
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void
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awin_pll6_enable(void)
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{
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bus_space_tag_t bst = &awin_bs_tag;
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bus_space_handle_t bsh = awin_core_bsh;
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/*
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* SATA needs PLL6 to be a 100MHz clock.
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*/
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const uint32_t ocfg = bus_space_read_4(bst, bsh, AWIN_PLL6_CFG_REG);
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const u_int k = __SHIFTOUT(ocfg, AWIN_PLL_CFG_FACTOR_K);
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/*
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* Output freq is 24MHz * n * k / m / 6.
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* To get to 100MHz, k & m must be equal and n must be 25.
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*/
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uint32_t ncfg = ocfg;
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ncfg &= ~(AWIN_PLL_CFG_FACTOR_M|AWIN_PLL_CFG_FACTOR_N);
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ncfg |= __SHIFTIN(k, AWIN_PLL_CFG_FACTOR_M);
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ncfg |= __SHIFTIN(25, AWIN_PLL_CFG_FACTOR_N);
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ncfg |= AWIN_PLL_CFG_ENABLE | AWIN_PLL6_CFG_SATA_CLK_EN;
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if (ncfg != ocfg) {
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bus_space_write_4(bst, bsh, AWIN_PLL6_CFG_REG, ncfg);
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}
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}
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@ -31,7 +31,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: awin_com.c,v 1.1 2013/09/04 02:39:01 matt Exp $");
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__KERNEL_RCSID(1, "$NetBSD: awin_com.c,v 1.2 2013/09/07 00:35:52 matt Exp $");
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#include <sys/bus.h>
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#include <sys/device.h>
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@ -53,6 +53,29 @@ struct awin_com_softc {
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void *asc_ih;
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};
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static const struct awin_gpio_pinset awin_com_pinsets[] = {
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{ 'B', AWIN_PIO_PB_UART0_FUNC, AWIN_PIO_PB_UART0_PINS },
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{ 'A', AWIN_PIO_PA_UART1_FUNC, AWIN_PIO_PA_UART1_PINS },
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{ 'I', AWIN_PIO_PI_UART2_FUNC, AWIN_PIO_PI_UART2_PINS },
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{ 'H', AWIN_PIO_PH_UART3_FUNC, AWIN_PIO_PH_UART3_PINS },
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{ 'H', AWIN_PIO_PH_UART4_FUNC, AWIN_PIO_PH_UART4_PINS },
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{ 'H', AWIN_PIO_PH_UART5_FUNC, AWIN_PIO_PH_UART5_PINS },
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{ 'I', AWIN_PIO_PI_UART6_FUNC, AWIN_PIO_PI_UART6_PINS },
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{ 'I', AWIN_PIO_PI_UART7_FUNC, AWIN_PIO_PI_UART7_PINS },
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};
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/* alternative pinnings */
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static const struct awin_gpio_pinset awin_com_alt_pinsets[] = {
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{ 'F', AWIN_PIO_PF_UART0_FUNC, AWIN_PIO_PF_UART0_PINS },
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{ 0, 0, 0},
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{ 'A', AWIN_PIO_PA_UART2_FUNC, AWIN_PIO_PA_UART2_PINS },
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{ 'G', AWIN_PIO_PG_UART3_FUNC, AWIN_PIO_PG_UART3_PINS },
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{ 'G', AWIN_PIO_PG_UART4_FUNC, AWIN_PIO_PG_UART4_PINS },
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{ 'I', AWIN_PIO_PI_UART5_FUNC, AWIN_PIO_PI_UART5_PINS },
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{ 'A', AWIN_PIO_PA_UART6_FUNC, AWIN_PIO_PA_UART6_PINS },
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{ 'A', AWIN_PIO_PA_UART7_FUNC, AWIN_PIO_PA_UART7_PINS },
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};
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CFATTACH_DECL_NEW(awin_com, sizeof(struct awin_com_softc),
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awin_com_match, awin_com_attach, NULL, NULL);
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@ -63,42 +86,54 @@ awin_com_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct awinio_attach_args * const aio = aux;
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const struct awin_locators * const loc = &aio->aio_loc;
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const int port = cf->cf_loc[AWINIOCF_PORT];
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bus_space_tag_t iot = aio->aio_core_a4x_bst;
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bus_space_handle_t bsh;
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bus_space_handle_t bsh;
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const struct awin_gpio_pinset * const pinset = loc->loc_port +
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((cf->cf_flags & 1) ? awin_com_alt_pinsets : awin_com_pinsets);
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if (strcmp(cf->cf_name, loc->loc_name))
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return 0;
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KASSERT(loc->loc_offset >= AWIN_UART0_OFFSET);
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KASSERT(!strcmp(cf->cf_name, loc->loc_name));
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KASSERT(loc->loc_offset >= AWIN_UART0_OFFSET);
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KASSERT(loc->loc_offset <= AWIN_UART7_OFFSET);
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KASSERT((loc->loc_offset & 0x3ff) == 0);
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KASSERT((awin_com_ports & __BIT(loc->loc_port)) == 0);
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KASSERT((awin_com_ports & __BIT(loc->loc_port)) == 0);
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KASSERT(cf->cf_loc[AWINIOCF_PORT] == AWINIOCF_PORT_DEFAULT
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|| cf->cf_loc[AWINIOCF_PORT] == loc->loc_port);
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if (port != AWINIOCF_PORT_DEFAULT && port != loc->loc_port)
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return 0;
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if (!awin_gpio_pinset_available(pinset))
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return 0;
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if (com_is_console(iot, AWIN_CORE_PBASE + loc->loc_offset, NULL))
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return 1;
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if (com_is_console(iot, AWIN_CORE_PBASE + loc->loc_offset, NULL))
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return 1;
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bus_space_subregion(iot, aio->aio_core_bsh,
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loc->loc_offset, loc->loc_size, &bsh);
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awin_gpio_pinset_acquire(pinset);
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return comprobe1(iot, bsh);
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bus_space_subregion(iot, aio->aio_core_bsh,
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loc->loc_offset, loc->loc_size, &bsh);
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const int rv = comprobe1(iot, bsh);
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awin_gpio_pinset_release(pinset);
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return rv;
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}
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static void
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awin_com_attach(device_t parent, device_t self, void *aux)
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{
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cfdata_t cf = device_cfdata(self);
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struct awin_com_softc * const asc = device_private(self);
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struct com_softc * const sc = &asc->asc_sc;
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struct awinio_attach_args * const aio = aux;
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const struct awin_locators * const loc = &aio->aio_loc;
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bus_space_tag_t iot = aio->aio_core_a4x_bst;
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const bus_addr_t iobase = AWIN_CORE_PBASE + loc->loc_offset;
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const struct awin_gpio_pinset * const pinset = loc->loc_port +
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((cf->cf_flags & 1) ? awin_com_alt_pinsets : awin_com_pinsets);
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bus_space_handle_t ioh;
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awin_com_ports |= __BIT(loc->loc_port);
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awin_com_ports |= __BIT(loc->loc_port);
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awin_gpio_pinset_acquire(pinset);
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sc->sc_dev = self;
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sc->sc_frequency = AWIN_UART_FREQ;
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@ -31,23 +31,62 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: awin_gpio.c,v 1.1 2013/09/04 02:39:01 matt Exp $");
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__KERNEL_RCSID(1, "$NetBSD: awin_gpio.c,v 1.2 2013/09/07 00:35:52 matt Exp $");
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/gpio.h>
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#include <dev/gpio/gpiovar.h>
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#include <arm/allwinner/awin_reg.h>
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#include <arm/allwinner/awin_var.h>
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static int awin_gpio_match(device_t, cfdata_t, void *);
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static void awin_gpio_attach(device_t, device_t, void *);
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struct awin_gpio_softc {
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static const int ist_maps[] = {
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[IST_LEVEL_LOW] = AWIN_PIO_EINT_LOW_LEVEL,
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[IST_LEVEL_HIGH] = AWIN_PIO_EINT_HIGH_LEVEL,
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[IST_EDGE_FALLING] = AWIN_PIO_EINT_POSITIVE_EDGE,
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[IST_EDGE_RISING] = AWIN_PIO_EINT_NEGATIVE_EDGE,
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[IST_EDGE_BOTH] = AWIN_PIO_EINT_DOUBLE_EDGE,
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};
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struct awin_gpio_pin_cfg {
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uint32_t val[4];
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};
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static struct awin_gpio_pin_group {
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uint32_t grp_pin_mask;
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uint32_t grp_pin_inuse_mask;
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bus_space_handle_t grp_bsh;
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struct awin_gpio_pin_cfg grp_cfg;
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} pin_groups[] = {
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[0] = { .grp_pin_mask = __BIT(AWIN_PIO_PA_PINS) - 1 },
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[1] = { .grp_pin_mask = __BIT(AWIN_PIO_PB_PINS) - 1 },
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[2] = { .grp_pin_mask = __BIT(AWIN_PIO_PC_PINS) - 1 },
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[3] = { .grp_pin_mask = __BIT(AWIN_PIO_PD_PINS) - 1 },
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[4] = { .grp_pin_mask = __BIT(AWIN_PIO_PE_PINS) - 1 },
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[5] = { .grp_pin_mask = __BIT(AWIN_PIO_PF_PINS) - 1 },
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[6] = { .grp_pin_mask = __BIT(AWIN_PIO_PG_PINS) - 1 },
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[7] = { .grp_pin_mask = __BIT(AWIN_PIO_PH_PINS) - 1 },
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[8] = { .grp_pin_mask = __BIT(AWIN_PIO_PI_PINS) - 1 },
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};
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struct awin_eint_info {
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uint32_t grp_pin ;
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};
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static struct awin_gpio_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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} awin_gpio_sc = {
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.sc_bst = &awin_bs_tag,
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};
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CFATTACH_DECL_NEW(awin_gpio, sizeof(struct awin_gpio_softc),
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@ -59,18 +98,20 @@ awin_gpio_match(device_t parent, cfdata_t cf, void *aux)
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struct awinio_attach_args * const aio = aux;
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const struct awin_locators * const loc = &aio->aio_loc;
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if (strcmp(cf->cf_name, loc->loc_name))
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return 0;
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KASSERT(!strcmp(cf->cf_name, loc->loc_name));
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KASSERT(loc->loc_port == AWINIOCF_PORT_DEFAULT);
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KASSERT(cf->cf_loc[AWINIOCF_PORT] == AWINIOCF_PORT_DEFAULT);
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if (awin_gpio_sc.sc_dev != NULL)
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return 0;
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return 1;
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}
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static void
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awin_gpio_attach(device_t parent, device_t self, void *aux)
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{
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struct awin_gpio_softc * const sc = device_private(self);
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struct awin_gpio_softc * const sc = &awin_gpio_sc;
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struct awinio_attach_args * const aio = aux;
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const struct awin_locators * const loc = &aio->aio_loc;
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@ -83,3 +124,204 @@ awin_gpio_attach(device_t parent, device_t self, void *aux)
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aprint_naive("\n");
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aprint_normal("\n");
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}
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static u_int
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awin_gpio_get_pin_func(const struct awin_gpio_pin_cfg *cfg, u_int pin)
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{
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const u_int shift = (pin & 7) << 2;
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const u_int i = pin >> 3;
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return (cfg->val[i] >> shift) & 0x0f;
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}
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static void
|
||||
awin_gpio_set_pin_func(struct awin_gpio_pin_cfg *cfg, u_int pin, u_int func)
|
||||
{
|
||||
const u_int shift = (pin & 7) << 2;
|
||||
const u_int i = pin >> 3;
|
||||
|
||||
cfg->val[i] &= ~(0x0f << shift);
|
||||
cfg->val[i] |= func << shift;
|
||||
}
|
||||
|
||||
static void
|
||||
awin_gpio_update_cfg_regs(bus_space_tag_t bst, struct awin_gpio_pin_group *grp,
|
||||
const struct awin_gpio_pin_cfg *ncfg)
|
||||
{
|
||||
for (u_int i = 0; i < 4; i++) {
|
||||
if (grp->grp_cfg.val[i] != ncfg->val[i]) {
|
||||
bus_space_write_4(bst, grp->grp_bsh,
|
||||
AWIN_PIO_CFG0_REG + 4 * i, ncfg->val[i]);
|
||||
grp->grp_cfg.val[i] = ncfg->val[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
awin_gpio_init(void)
|
||||
{
|
||||
struct awin_gpio_softc * const sc = &awin_gpio_sc;
|
||||
bus_size_t offset = AWIN_PIO_OFFSET;
|
||||
|
||||
printf(" free");
|
||||
for (u_int i = 0;
|
||||
i < __arraycount(pin_groups);
|
||||
i++, offset += AWIN_PIO_GRP_SIZE) {
|
||||
struct awin_gpio_pin_group * const grp = &pin_groups[i];
|
||||
bus_space_subregion(sc->sc_bst, awin_core_bsh,
|
||||
offset, AWIN_PIO_GRP_SIZE, &grp->grp_bsh);
|
||||
|
||||
for (u_int j = 0; j < 4; j++) {
|
||||
grp->grp_cfg.val[j] = bus_space_read_4(sc->sc_bst,
|
||||
grp->grp_bsh, AWIN_PIO_CFG0_REG + j * 4);
|
||||
}
|
||||
|
||||
for (uint32_t j = 0, mask = 1;
|
||||
(mask & grp->grp_pin_mask) != 0;
|
||||
j++, mask <<= 1) {
|
||||
u_int func = awin_gpio_get_pin_func(&grp->grp_cfg, j);
|
||||
if (func > AWIN_PIO_FUNC_OUTPUT) {
|
||||
grp->grp_pin_inuse_mask |= mask;
|
||||
}
|
||||
}
|
||||
printf(" P%c=%d", 'A' + i,
|
||||
popcount32(grp->grp_pin_mask & ~grp->grp_pin_inuse_mask));
|
||||
}
|
||||
}
|
||||
|
||||
bool
|
||||
awin_gpio_pinset_available(const struct awin_gpio_pinset *req)
|
||||
{
|
||||
KASSERT(req != NULL);
|
||||
|
||||
if (!req->pinset_group)
|
||||
return false;
|
||||
|
||||
KASSERT('A' <= req->pinset_group && req->pinset_group <= 'I');
|
||||
|
||||
struct awin_gpio_pin_group * const grp =
|
||||
&pin_groups[req->pinset_group - 'A'];
|
||||
|
||||
/*
|
||||
* If there are unconnected pins, then they've been remove from
|
||||
* the groups pin mask. If we want pins that are unconnected,
|
||||
* fail the request.
|
||||
*/
|
||||
if (req->pinset_mask & ~grp->grp_pin_mask)
|
||||
return false;
|
||||
|
||||
/*
|
||||
* If none of the pins are in use, they must be available.
|
||||
*/
|
||||
if (req->pinset_mask & ~grp->grp_pin_inuse_mask)
|
||||
return true;
|
||||
|
||||
/*
|
||||
* Check to see if the pins are already setup for this function.
|
||||
*/
|
||||
for (uint32_t j = 0, inuse = req->pinset_mask & grp->grp_pin_inuse_mask;
|
||||
inuse != 0;
|
||||
j++, inuse >>= 1) {
|
||||
const u_int n = ffs(inuse) - 1;
|
||||
j += n;
|
||||
inuse >>= n;
|
||||
/*
|
||||
* If this pin is in use but it's for a different
|
||||
* function, fail the request.
|
||||
*/
|
||||
if (awin_gpio_get_pin_func(&grp->grp_cfg, j) != req->pinset_func)
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
* Nothing incompatible encountered so the pins must be available.
|
||||
*/
|
||||
return true;
|
||||
}
|
||||
|
||||
void
|
||||
awin_gpio_pinset_acquire(const struct awin_gpio_pinset *req)
|
||||
{
|
||||
KASSERT(awin_gpio_pinset_available(req));
|
||||
|
||||
struct awin_gpio_pin_group * const grp =
|
||||
&pin_groups[req->pinset_group - 'A'];
|
||||
|
||||
|
||||
/*
|
||||
* If all the pins already have right function, just return.
|
||||
*/
|
||||
if ((req->pinset_mask & ~grp->grp_pin_inuse_mask) == 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Copy the current config.
|
||||
*/
|
||||
struct awin_gpio_pin_cfg ncfg = grp->grp_cfg;
|
||||
|
||||
/*
|
||||
* For each pin not inuse, update the cloned config's function for it.
|
||||
*/
|
||||
for (uint32_t j = 0, todo = req->pinset_mask & ~grp->grp_pin_inuse_mask;
|
||||
todo != 0;
|
||||
j++, todo >>= 1) {
|
||||
const u_int n = ffs(todo) - 1;
|
||||
j += n;
|
||||
todo >>= n;
|
||||
/*
|
||||
* Change the function of this pin.
|
||||
*/
|
||||
awin_gpio_set_pin_func(&ncfg, j, req->pinset_func);
|
||||
}
|
||||
|
||||
/*
|
||||
* Now update any config register that changed.
|
||||
*/
|
||||
awin_gpio_update_cfg_regs(&awin_bs_tag, grp, &ncfg);
|
||||
|
||||
/*
|
||||
* Mark all these pins as in use.
|
||||
*/
|
||||
grp->grp_pin_inuse_mask |= req->pinset_mask;
|
||||
}
|
||||
|
||||
void
|
||||
awin_gpio_pinset_release(const struct awin_gpio_pinset *req)
|
||||
{
|
||||
KASSERT(awin_gpio_pinset_available(req));
|
||||
|
||||
struct awin_gpio_pin_group * const grp =
|
||||
&pin_groups[req->pinset_group - 'A'];
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* Copy the current config.
|
||||
*/
|
||||
struct awin_gpio_pin_cfg ncfg = grp->grp_cfg;
|
||||
|
||||
/*
|
||||
* For each pin not inuse, update the cloned config's function for it.
|
||||
*/
|
||||
for (uint32_t j = 0, todo = req->pinset_mask;
|
||||
todo != 0;
|
||||
j++, todo >>= 1) {
|
||||
const u_int n = ffs(todo) - 1;
|
||||
j += n;
|
||||
todo >>= n;
|
||||
/*
|
||||
* Change the function of this pin.
|
||||
*/
|
||||
awin_gpio_set_pin_func(&ncfg, AWIN_PIO_FUNC_INPUT);
|
||||
}
|
||||
|
||||
/*
|
||||
* Now update any config register that changed.
|
||||
*/
|
||||
awin_gpio_update_cfg_regs(sc->sc_bst, grp, &ncfg);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Clear these pins as being in use.
|
||||
*/
|
||||
grp->grp_pin_inuse_mask &= ~req->pinset_mask;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: awin_intr.h,v 1.2 2013/09/04 02:39:01 matt Exp $ */
|
||||
/* $NetBSD: awin_intr.h,v 1.3 2013/09/07 00:35:52 matt Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2013 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
|
|
@ -31,8 +31,8 @@
|
|||
#ifndef _ARM_ALLWINNER_AWIN_INTR_H_
|
||||
#define _ARM_ALLWINNER_AWIN_INTR_H_
|
||||
|
||||
#define PIC_MAXSOURCES 128
|
||||
#define PIC_MAXMAXSOURCES 256
|
||||
#define PIC_MAXSOURCES 160
|
||||
#define PIC_MAXMAXSOURCES 192
|
||||
|
||||
/*
|
||||
* The Allwinner can use a generic interrupt controller so pull in that stuff.
|
||||
|
|
@ -81,8 +81,8 @@
|
|||
#define AWIN_IRQ_MS 68
|
||||
#define AWIN_IRQ_NAND 69
|
||||
#define AWIN_IRQ_USB0 70
|
||||
#define AWIN_IRQ_USB1 71
|
||||
#define AWIN_IRQ_USB2 72
|
||||
#define AWIN_IRQ_USB1 71 // EHCI0
|
||||
#define AWIN_IRQ_USB2 72 // EHCI1
|
||||
#define AWIN_IRQ_SCR 73
|
||||
#define AWIN_IRQ_CSI0 74
|
||||
#define AWIN_IRQ_CSI1 75
|
||||
|
|
@ -106,8 +106,8 @@
|
|||
#define AWIN_IRQ_TVD 93
|
||||
#define AWIN_IRQ_PS2_0 94
|
||||
#define AWIN_IRQ_PS2_1 95
|
||||
#define AWIN_IRQ_USB3 96
|
||||
#define AWIN_IRQ_USB4 97
|
||||
#define AWIN_IRQ_USB3 96 // OHCI0
|
||||
#define AWIN_IRQ_USB4 97 // OHCI1
|
||||
#define AWIN_IRQ_PERFM 98
|
||||
#define AWIN_IRQ_TMR4 99
|
||||
#define AWIN_IRQ_TMR5 100
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.1 2013/09/04 02:39:01 matt Exp $");
|
||||
__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.2 2013/09/07 00:35:52 matt Exp $");
|
||||
|
||||
#include <sys/bus.h>
|
||||
#include <sys/cpu.h>
|
||||
|
|
@ -53,6 +53,7 @@ static struct awinio_softc {
|
|||
bus_space_tag_t sc_bst;
|
||||
bus_space_tag_t sc_a4x_bst;
|
||||
bus_space_handle_t sc_bsh;
|
||||
bus_space_handle_t sc_ccm_bsh;
|
||||
bus_dma_tag_t sc_dmat;
|
||||
} awinio_sc;
|
||||
|
||||
|
|
@ -99,12 +100,13 @@ static const struct awin_locators awin_locators[] = {
|
|||
{ "com", OFFANDSIZE(UART6), 6, AWIN_IRQ_UART6, AANY },
|
||||
{ "com", OFFANDSIZE(UART7), 7, AWIN_IRQ_UART7, AANY },
|
||||
{ "awinwdt", OFFANDSIZE(TMR), NOPORT, NOINTR, AANY },
|
||||
{ "awinusb", OFFANDSIZE(USB1), 0, AWIN_IRQ_USB1, AANY },
|
||||
{ "awinusb", OFFANDSIZE(USB2), 1, AWIN_IRQ_USB2, AANY },
|
||||
{ "awinusb", OFFANDSIZE(USB1), 0, NOINTR, AANY },
|
||||
{ "awinusb", OFFANDSIZE(USB2), 1, NOINTR, AANY },
|
||||
{ "sdhc", OFFANDSIZE(SDMMC0), 0, AWIN_IRQ_SDMMC0, AANY },
|
||||
{ "sdhc", OFFANDSIZE(SDMMC1), 1, AWIN_IRQ_SDMMC1, AANY },
|
||||
{ "sdhc", OFFANDSIZE(SDMMC2), 2, AWIN_IRQ_SDMMC2, AANY },
|
||||
{ "sdhc", OFFANDSIZE(SDMMC3), 3, AWIN_IRQ_SDMMC3, AANY },
|
||||
{ "sdhc", OFFANDSIZE(SDMMC1), 4, AWIN_IRQ_SDMMC1, AANY },
|
||||
{ "ahcisata", OFFANDSIZE(SATA), NOPORT, AWIN_IRQ_SATA, AANY },
|
||||
{ "twi", OFFANDSIZE(TWI0), 0, AWIN_IRQ_TWI0, AANY },
|
||||
{ "twi", OFFANDSIZE(TWI1), 1, AWIN_IRQ_TWI1, AANY },
|
||||
|
|
@ -148,6 +150,9 @@ awinio_attach(device_t parent, device_t self, void *aux)
|
|||
sc->sc_bsh = awin_core_bsh;
|
||||
sc->sc_dmat = &awin_dma_tag;
|
||||
|
||||
bus_space_subregion(sc->sc_bst, sc->sc_bsh, AWIN_CCM_OFFSET, 0x1000,
|
||||
&sc->sc_ccm_bsh);
|
||||
|
||||
aprint_naive("\n");
|
||||
aprint_normal("\n");
|
||||
|
||||
|
|
@ -165,6 +170,7 @@ awinio_attach(device_t parent, device_t self, void *aux)
|
|||
.aio_core_bst = sc->sc_bst,
|
||||
.aio_core_a4x_bst = sc->sc_a4x_bst,
|
||||
.aio_core_bsh = sc->sc_bsh,
|
||||
.aio_ccm_bsh = sc->sc_ccm_bsh,
|
||||
.aio_dmat = sc->sc_dmat,
|
||||
};
|
||||
cfdata_t cf = config_search_ia(awinio_find,
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
#define AWIN_LOSC_FREQ (32*1024) /* 32KHz */
|
||||
#define AWIN_REF_FREQ (24*1000*1000) /* 24MHz */
|
||||
|
||||
#define AWIN_CPUBIST_PBASE 0x3f501000
|
||||
#define AWIN_CPUBIST_PBASE 0x3F501000
|
||||
#define AWIN_CPUBIST_SIZE 0x00001000
|
||||
#define AWIN_SRAM_PBASE 0x00000000
|
||||
#define AWIN_SRAM_SIZE 0x00100000 /* round to 1MB */
|
||||
|
|
@ -44,14 +44,14 @@
|
|||
#define AWIN_SRAMA2_SIZE 0x00004000
|
||||
#define AWIN_SRAMA3_PBASE 0x00008000
|
||||
#define AWIN_SRAMA3_SIZE 0x00003400
|
||||
#define AWIN_SRAMA4_PBASE 0x0000b400
|
||||
#define AWIN_SRAMA4_SIZE 0x00000c00
|
||||
#define AWIN_SRAMA4_PBASE 0x0000B400
|
||||
#define AWIN_SRAMA4_SIZE 0x00000C00
|
||||
#define AWIN_SRAMD_PBASE 0x00010000
|
||||
#define AWIN_SRAMD_SIZE 0x00001000
|
||||
#define AWIN_SRAMB_PBASE 0x00020000 /* Secure */
|
||||
#define AWIN_SRAMB_SIZE 0x00010000 /* Secure */
|
||||
|
||||
#define AWIN_CORE_PBASE 0x01c00000
|
||||
#define AWIN_CORE_PBASE 0x01C00000
|
||||
#define AWIN_CORE_SIZE 0x00300000
|
||||
#define AWIN_SRAM_OFFSET 0x00000000
|
||||
#define AWIN_DRAM_OFFSET 0x00001000
|
||||
|
|
@ -63,12 +63,12 @@
|
|||
#define AWIN_MS_OFFSET 0x00007000
|
||||
#define AWIN_TVD_OFFSET 0x00008000
|
||||
#define AWIN_CSI0_OFFSET 0x00009000
|
||||
#define AWIN_TVE0_OFFSET 0x0000a000
|
||||
#define AWIN_EMAC_OFFSET 0x0000b000
|
||||
#define AWIN_LCD0_OFFSET 0x0000c000
|
||||
#define AWIN_LCD1_OFFSET 0x0000d000
|
||||
#define AWIN_VE_OFFSET 0x0000e000
|
||||
#define AWIN_SDMMC0_OFFSET 0x0000f000
|
||||
#define AWIN_TVE0_OFFSET 0x0000A000
|
||||
#define AWIN_EMAC_OFFSET 0x0000B000
|
||||
#define AWIN_LCD0_OFFSET 0x0000C000
|
||||
#define AWIN_LCD1_OFFSET 0x0000D000
|
||||
#define AWIN_VE_OFFSET 0x0000E000
|
||||
#define AWIN_SDMMC0_OFFSET 0x0000F000
|
||||
#define AWIN_SDMMC1_OFFSET 0x00010000
|
||||
#define AWIN_SDMMC2_OFFSET 0x00011000
|
||||
#define AWIN_SDMMC3_OFFSET 0x00012000
|
||||
|
|
@ -79,64 +79,64 @@
|
|||
#define AWIN_SPI2_OFFSET 0x00017000
|
||||
#define AWIN_SATA_OFFSET 0x00018000 /* A20 */
|
||||
#define AWIN_PATA_OFFSET 0x00019000 /* A10 */
|
||||
#define AWIN_ACE_OFFSET 0x0001a000
|
||||
#define AWIN_TVE1_OFFSET 0x0001b000
|
||||
#define AWIN_USB2_OFFSET 0x0001c000
|
||||
#define AWIN_CSI1_OFFSET 0x0001d000
|
||||
#define AWIN_TZASC_OFFSET 0x0001e000 /* A10 */
|
||||
#define AWIN_SPI3_OFFSET 0x0001f000
|
||||
#define AWIN_ACE_OFFSET 0x0001A000
|
||||
#define AWIN_TVE1_OFFSET 0x0001B000
|
||||
#define AWIN_USB2_OFFSET 0x0001C000
|
||||
#define AWIN_CSI1_OFFSET 0x0001D000
|
||||
#define AWIN_TZASC_OFFSET 0x0001E000 /* A10 */
|
||||
#define AWIN_SPI3_OFFSET 0x0001F000
|
||||
#define AWIN_CCM_OFFSET 0x00020000
|
||||
#define AWIN_INTC_OFFSET 0x00020400
|
||||
#define AWIN_PIO_OFFSET 0x00020800
|
||||
#define AWIN_TMR_OFFSET 0x00020c00
|
||||
#define AWIN_TMR_OFFSET 0x00020C00
|
||||
#define AWIN_SPDIF_OFFSET 0x00021000 /* A20 */
|
||||
#define AWIN_AC97_OFFSET 0x00021400
|
||||
#define AWIN_IR0_OFFSET 0x00021800
|
||||
#define AWIN_IR1_OFFSET 0x00021c00
|
||||
#define AWIN_IR1_OFFSET 0x00021C00
|
||||
#define AWIN_IIS0_OFFSET 0x00022000
|
||||
#define AWIN_IIS1_OFFSET 0x00022400
|
||||
#define AWIN_LRADC_OFFSET 0x00022800
|
||||
#define AWIN_ADDA_OFFSET 0x00022c00
|
||||
#define AWIN_ADDA_OFFSET 0x00022C00
|
||||
#define AWIN_KEYPAD_OFFSET 0x00023000
|
||||
#define AWIN_TZPC_OFFSET 0x00023400 /* A10 */
|
||||
#define AWIN_SID_OFFSET 0x00023800
|
||||
#define AWIN_SJTAG_OFFSET 0x00023c00
|
||||
#define AWIN_SJTAG_OFFSET 0x00023C00
|
||||
#define AWIN__RSVD3_OFFSET 0x00024000
|
||||
#define AWIN_IIS2_OFFSET 0x00024400
|
||||
#define AWIN__RSVD4_OFFSET 0x00024800
|
||||
#define AWIN__RSVD5_OFFSET 0x00024c00
|
||||
#define AWIN__RSVD5_OFFSET 0x00024C00
|
||||
#define AWIN_TP_OFFSET 0x00025000
|
||||
#define AWIN_PMU_OFFSET 0x00025400
|
||||
#define AWIN__RSVD6_OFFSET 0x00025800
|
||||
#define AWIN_CPUCNF_OFFSET 0x00025c00
|
||||
#define AWIN_CPUCNF_OFFSET 0x00025C00
|
||||
#define AWIN__RSVD7_OFFSET 0x00026000
|
||||
#define AWIN__RSVD8_OFFSET 0x00026400
|
||||
#define AWIN__RSVD9_OFFSET 0x00026800
|
||||
#define AWIN__RSVD10_OFFSET 0x00026c00
|
||||
#define AWIN__RSVD10_OFFSET 0x00026C00
|
||||
#define AWIN__RSVD11_OFFSET 0x00027000
|
||||
#define AWIN__RSVD12_OFFSET 0x00027400
|
||||
#define AWIN__RSVD13_OFFSET 0x00027800
|
||||
#define AWIN__RSVD14_OFFSET 0x00027c00
|
||||
#define AWIN__RSVD14_OFFSET 0x00027C00
|
||||
#define AWIN_UART_FREQ AWIN_REF_FREQ /* 24MHz */
|
||||
#define AWIN_UART_SIZE 0x00000100
|
||||
#define AWIN_UART0_OFFSET 0x00028000
|
||||
#define AWIN_UART1_OFFSET 0x00028400
|
||||
#define AWIN_UART2_OFFSET 0x00028800
|
||||
#define AWIN_UART3_OFFSET 0x00028c00
|
||||
#define AWIN_UART3_OFFSET 0x00028C00
|
||||
#define AWIN_UART4_OFFSET 0x00029000
|
||||
#define AWIN_UART5_OFFSET 0x00029400
|
||||
#define AWIN_UART6_OFFSET 0x00029800
|
||||
#define AWIN_UART7_OFFSET 0x00029c00
|
||||
#define AWIN_PS20_OFFSET 0x0002a000
|
||||
#define AWIN_PS21_OFFSET 0x0002a400
|
||||
#define AWIN__RSVD15_OFFSET 0x0002a800
|
||||
#define AWIN_TWI0_OFFSET 0x0002ac00
|
||||
#define AWIN_TWI1_OFFSET 0x0002b000
|
||||
#define AWIN_TWI2_OFFSET 0x0002b400
|
||||
#define AWIN_TWI3_OFFSET 0x0002b800
|
||||
#define AWIN_CAN_OFFSET 0x0002bc00
|
||||
#define AWIN_TWI4_OFFSET 0x0002c000 /* A20 */
|
||||
#define AWIN_SCR_OFFSET 0x0002c400
|
||||
#define AWIN_UART7_OFFSET 0x00029C00
|
||||
#define AWIN_PS20_OFFSET 0x0002A000
|
||||
#define AWIN_PS21_OFFSET 0x0002A400
|
||||
#define AWIN__RSVD15_OFFSET 0x0002A800
|
||||
#define AWIN_TWI0_OFFSET 0x0002AC00 /* Marvell I2C */
|
||||
#define AWIN_TWI1_OFFSET 0x0002B000 /* Marvell I2C */
|
||||
#define AWIN_TWI2_OFFSET 0x0002B400 /* Marvell I2C */
|
||||
#define AWIN_TWI3_OFFSET 0x0002B800 /* Marvell I2C */
|
||||
#define AWIN_CAN_OFFSET 0x0002BC00
|
||||
#define AWIN_TWI4_OFFSET 0x0002C000 /* A20 */
|
||||
#define AWIN_SCR_OFFSET 0x0002C400
|
||||
#define AWIN_GPS_OFFSET 0x00030000
|
||||
#define AWIN_MALI400_OFFSET 0x00040000
|
||||
#define AWIN_GMAC_OFFSET 0x00050000
|
||||
|
|
@ -157,47 +157,49 @@
|
|||
#define AWIN_DRAM_CCR_REG 0x0000
|
||||
#define AWIN_DRAM_DCR_REG 0x0004
|
||||
#define AWIN_DRAM_IOCR_REG 0x0008
|
||||
#define AWIN_DRAM_CSR_REG 0x000c
|
||||
#define AWIN_DRAM_CSR_REG 0x000C
|
||||
#define AWIN_DRAM_DRR_REG 0x0010
|
||||
#define AWIN_DRAM_TPR0_REG 0x0014
|
||||
#define AWIN_DRAM_TPR1_REG 0x0018
|
||||
#define AWIN_DRAM_TPR2_REG 0x001c
|
||||
#define AWIN_DRAM_TPR2_REG 0x001C
|
||||
#define AWIN_DRAM_GDLLCR_REG 0x0020
|
||||
#define AWIN_DRAM_RSLR0_REG 0x004c
|
||||
#define AWIN_DRAM_RSLR0_REG 0x004C
|
||||
#define AWIN_DRAM_RSLR1_REG 0x0050
|
||||
#define AWIN_DRAM_RDGR0_REG 0x005c
|
||||
#define AWIN_DRAM_RDGR0_REG 0x005C
|
||||
#define AWIN_DRAM_RDGR1_REG 0x0060
|
||||
#define AWIN_DRAM_ODTCR_REG 0x0098
|
||||
#define AWIN_DRAM_DTR0_REG 0x009c
|
||||
#define AWIN_DRAM_DTR1_REG 0x00a0
|
||||
#define AWIN_DRAM_DTAR_REG 0x00a4
|
||||
#define AWIN_DRAM_ZQCR0_REG 0x00a8
|
||||
#define AWIN_DRAM_ZQCR1_REG 0x00ac
|
||||
#define AWIN_DRAM_ZQSR_REG 0x00b0
|
||||
#define AWIN_DRAM_IDCR_REG 0x00b4
|
||||
#define AWIN_DRAM_MR_REG 0x01f0
|
||||
#define AWIN_DRAM_EMR1_REG 0x01f4
|
||||
#define AWIN_DRAM_EMR2_REG 0x01f8
|
||||
#define AWIN_DRAM_EMR3_REG 0x01fc
|
||||
#define AWIN_DRAM_DTR0_REG 0x009C
|
||||
#define AWIN_DRAM_DTR1_REG 0x00A0
|
||||
#define AWIN_DRAM_DTAR_REG 0x00A4
|
||||
#define AWIN_DRAM_ZQCR0_REG 0x00A8
|
||||
#define AWIN_DRAM_ZQCR1_REG 0x00AC
|
||||
#define AWIN_DRAM_ZQSR_REG 0x00B0
|
||||
#define AWIN_DRAM_IDCR_REG 0x00B4
|
||||
#define AWIN_DRAM_MR_REG 0x01F0
|
||||
#define AWIN_DRAM_EMR1_REG 0x01F4
|
||||
#define AWIN_DRAM_EMR2_REG 0x01F8
|
||||
#define AWIN_DRAM_EMR3_REG 0x01FC
|
||||
#define AWIN_DRAM_DLLCTR_REG 0x0200
|
||||
#define AWIN_DRAM_DLLCR0_REG 0x0204
|
||||
#define AWIN_DRAM_DLLCR1_REG 0x0208
|
||||
#define AWIN_DRAM_DLLCR2_REG 0x020c
|
||||
#define AWIN_DRAM_DLLCR2_REG 0x020C
|
||||
#define AWIN_DRAM_DLLCR3_REG 0x0210
|
||||
#define AWIN_DRAM_DLLCR4_REG 0x0214
|
||||
#define AWIN_DRAM_DQTR0_REG 0x0218
|
||||
#define AWIN_DRAM_DQTR1_REG 0x021c
|
||||
#define AWIN_DRAM_DQTR1_REG 0x021C
|
||||
#define AWIN_DRAM_DQTR2_REG 0x0220
|
||||
#define AWIN_DRAM_DQTR3_REG 0x0224
|
||||
#define AWIN_DRAM_DQSTR_REG 0x0228
|
||||
#define AWIN_DRAM_DQSBTR_REG 0x022c
|
||||
#define AWIN_DRAM_DQSBTR_REG 0x022C
|
||||
#define AWIN_DRAM_MCR_REG 0x0230
|
||||
#define AWIN_DRAM_PPWRSCTRL_REG 0x0240
|
||||
#define AWIN_DRAM_APR_REG 0x0244
|
||||
#define AWIN_DRAM_PLDTR_REG 0x023c
|
||||
#define AWIN_DRAM_PLDTR_REG 0x023C
|
||||
#define AWIN_DRAM_HPCR0_REG 0x0240
|
||||
#define AWIN_DRAM_HPCRn_REG(n) (0x0240+4*(n))
|
||||
#define AWIN_DRAM_CSEL_REG 0x02e0
|
||||
#define AWIN_DRAM_HPCR_USB1 AWIN_DRAM_HPCRn_REG(4)
|
||||
#define AWIN_DRAM_HPCR_USB2 AWIN_DRAM_HPCRn_REG(5)
|
||||
#define AWIN_DRAM_CSEL_REG 0x02E0
|
||||
|
||||
#define AWIN_DRAM_DCR_IO_WIDTH __BITS(2,1)
|
||||
#define AWIN_DRAM_DCR_IO_WIDTH_16BIT 2
|
||||
|
|
@ -215,45 +217,130 @@
|
|||
#define AWIN_DRAM_DCR_BUS_WIDTH_8BIT 0
|
||||
#define AWIN_DRAM_DCR_RANK_SEL __BITS(11,10)
|
||||
|
||||
#define AWIN_DRAM_HPCR_READ_CNT_EN __BIT(31)
|
||||
#define AWIN_DRAM_HPCR_RWRITE_CNT_EN __BIT(30)
|
||||
#define AWIN_DRAM_HPCR_COMMAND_NUM __BIT(8)
|
||||
#define AWIN_DRAM_HPCR_WAIT_STATE __BIT(4)
|
||||
#define AWIN_DRAM_HPCR_PRIORITY_LEVEL __BIT(2)
|
||||
#define AWIN_DRAM_HPCR_ACCESS_EN __BIT(0)
|
||||
|
||||
#define AWIN_EMAC_CTL_REG 0x0000
|
||||
#define AWIN_EMAC_TX_MODE_REG 0x0004
|
||||
#define AWIN_EMAC_TX_FLOW_REG 0x0008
|
||||
#define AWIN_EMAC_TX_CTL0_REG 0x000C
|
||||
#define AWIN_EMAC_TX_CTL1_REG 0x0010
|
||||
#define AWIN_EMAC_TX_INS_REG 0x0014
|
||||
#define AWIN_EMAC_TX_PL0_REG 0x0018
|
||||
#define AWIN_EMAC_TX_PL1_REG 0x001C
|
||||
#define AWIN_EMAC_TX_STA_REG 0x0020
|
||||
#define AWIN_EMAC_TX_IO_DATA0_REG 0x0024
|
||||
#define AWIN_EMAC_TX_IO_DATA1_REG 0x0028
|
||||
#define AWIN_EMAC_TX_TSVL0_REG 0x002C
|
||||
#define AWIN_EMAC_TX_TSVH0_REG 0x0030
|
||||
#define AWIN_EMAC_TX_TSVL1_REG 0x0034
|
||||
#define AWIN_EMAC_TX_TSVH1_REG 0x0038
|
||||
#define AWIN_EMAC_RX_CTL_REG 0x003C
|
||||
#define AWIN_EMAC_RX_HASH0_REG 0x0040
|
||||
#define AWIN_EMAC_RX_HASH1_REG 0x0044
|
||||
#define AWIN_EMAC_RX_STA_REG 0x0048
|
||||
#define AWIN_EMAC_RX_IO_DATA_REG 0x004C
|
||||
#define AWIN_EMAC_RX_FBC_REG 0x0050
|
||||
#define AWIN_EMAC_INT_CTL_REG 0x0054
|
||||
#define AWIN_EMAC_INT_STA_REG 0x0058
|
||||
#define AWIN_EMAC_MAC_CTL0_REG 0x005C
|
||||
#define AWIN_EMAC_MAC_CTL1_REG 0x0060
|
||||
#define AWIN_EMAC_MAC_IPGT_REG 0x0064
|
||||
#define AWIN_EMAC_MAC_IPGR_REG 0x0068
|
||||
#define AWIN_EMAC_MAC_CLRT_REG 0x006C
|
||||
#define AWIN_EMAC_MAC_MAXF_REG 0x0070
|
||||
#define AWIN_EMAC_MAC_SUPP_REG 0x0074
|
||||
#define AWIN_EMAC_MAC_TEST_REG 0x0078
|
||||
#define AWIN_EMAC_MAC_MCFG_REG 0x007C
|
||||
#define AWIN_EMAC_MAC_MCMD_REG 0x0080
|
||||
#define AWIN_EMAC_MAC_MADR_REG 0x0084
|
||||
#define AWIN_EMAC_MAC_MWTD_REG 0x0088
|
||||
#define AWIN_EMAC_MAC_MRDD_REG 0x008C
|
||||
#define AWIN_EMAC_MAC_MIND_REG 0x0090
|
||||
#define AWIN_EMAC_MAC_SSRR_REG 0x0094
|
||||
#define AWIN_EMAC_MAC_A0_REG 0x0098
|
||||
#define AWIN_EMAC_MAC_A1_REG 0x009C
|
||||
#define AWIN_EMAC_MAC_A2_REG 0x00A0
|
||||
#define AWIN_EMAC_SAFX0_L_REG 0x00A4
|
||||
#define AWIN_EMAC_SAFX0_H_REG 0x00A8
|
||||
#define AWIN_EMAC_SAFX1_L_REG 0x00AC
|
||||
#define AWIN_EMAC_SAFX1_H_REG 0x00B0
|
||||
#define AWIN_EMAC_SAFX2_L_REG 0x00B4
|
||||
#define AWIN_EMAC_SAFX2_H_REG 0x00B8
|
||||
#define AWIN_EMAC_SAFX3_L_REG 0x00BC
|
||||
#define AWIN_EMAC_SAFX3_H_REG 0x00C0
|
||||
|
||||
#define AWIN_ACHI_BISTAFR_REG 0x00A0
|
||||
#define AWIN_AHCI_BISTCR_REG 0x00A4
|
||||
#define AWIN_AHCI_BISTFCTR_REG 0x00A8
|
||||
#define AWIN_AHCI_BISTSR_REG 0x00AC
|
||||
#define AWIN_AHCI_BISTDECR_REG 0x00B0
|
||||
#define AWIN_AHCI_DIAGNR_REG 0x00B4
|
||||
#define AWIN_AHCI_DIAGNR1_REG 0x00B8
|
||||
#define AWIN_AHCI_OOBR_REG 0x00BC
|
||||
#define AWIN_AHCI_PHYCS0R_REG 0x00C0
|
||||
#define AWIN_AHCI_PHYCS1R_REG 0x00C4
|
||||
#define AWIN_AHCI_PHYCS2R_REG 0x00C8
|
||||
#define AWIN_AHCI_TIMER1MS_REG 0x00E0
|
||||
#define AWIN_AHCI_GPARAM1R_REG 0x00E8
|
||||
#define AWIN_AHCI_GPARAM2R_REG 0x00EC
|
||||
#define AWIN_AHCI_PPARAMR_REG 0x00F0
|
||||
#define AWIN_AHCI_TESTR_REG 0x00F4
|
||||
#define AWIN_AHCI_VERSIONR_REG 0x00F8
|
||||
#define AWIN_AHCI_IDR_REG 0x00FC
|
||||
#define AWIN_AHCI_RWCR_REG 0x00FC
|
||||
|
||||
#define AWIN_AHCI_P0DMACR_REG 0x0170
|
||||
#define AWIN_AHCI_P0PHYCR_REG 0x0178
|
||||
#define AWIN_AHCI_P0PHYSR_REG 0x017C
|
||||
|
||||
|
||||
#define AWIN_PLL1_CFG_REG 0x0000
|
||||
#define AWIN_PLL1_TUN_REG 0x0004
|
||||
#define AWIN_PLL2_CFG_REG 0x0008
|
||||
#define AWIN_PLL2_TUN_REG 0x000c
|
||||
#define AWIN_PLL2_TUN_REG 0x000C
|
||||
#define AWIN_PLL3_CFG_REG 0x0010
|
||||
#define AWIN_PLL4_CFG_REG 0x0018
|
||||
#define AWIN_PLL5_CFG_REG 0x0020
|
||||
#define AWIN_PLL5_TUN_REG 0x0024
|
||||
#define AWIN_PLL6_CFG_REG 0x0028
|
||||
#define AWIN_PLL6_TUN_REG 0x002c
|
||||
#define AWIN_PLL6_TUN_REG 0x002C
|
||||
#define AWIN_PLL7_CFG_REG 0x0030
|
||||
#define AWIN_PLL1_TUN2_REG 0x0038
|
||||
#define AWIN_PLL6_TUN2_REG 0x003c
|
||||
#define AWIN_PLL6_TUN2_REG 0x003C
|
||||
#define AWIN_PLL8_CFG_REG 0x0040
|
||||
#define AWIN_OSC24M_CFG_REG 0x0050
|
||||
#define AWIN_CPU_AHB_APB0_CFG_REG 0x0054
|
||||
#define AWIN_APB1_CLK_DIV_REG 0x0058
|
||||
#define AWIN_AXI_GATING_REG 0x005c
|
||||
#define AWIN_AXI_GATING_REG 0x005C
|
||||
#define AWIN_AHB_GATING0_REG 0x0060
|
||||
#define AWIN_AHB_GATING1_REG 0x0064
|
||||
#define AWIN_APB0_GATING_REG 0x0068
|
||||
#define AWIN_APB1_GATING_REG 0x006c
|
||||
#define AWIN_APB1_GATING_REG 0x006C
|
||||
#define AWIN_NAND_SCLK_CFG_REG 0x0080
|
||||
#define AWIN_MS_SCLK_CFG_REG 0x0084
|
||||
#define AWIN_SD0_CLK_REG 0x0088
|
||||
#define AWIN_SD1_CLK_REG 0x008c
|
||||
#define AWIN_SD1_CLK_REG 0x008C
|
||||
#define AWIN_SD2_CLK_REG 0x0090
|
||||
#define AWIN_SD3_CLK_REG 0x0094
|
||||
#define AWIN_TS_CLK_REG 0x0098
|
||||
#define AWIN_SS_CLK_REG 0x009c
|
||||
#define AWIN_SPI0_CLK_REG 0x00a0
|
||||
#define AWIN_SPI1_CLK_REG 0x00a4
|
||||
#define AWIN_SPI2_CLK_REG 0x00a8
|
||||
#define AWIN_IR0_CLK_REG 0x00b9
|
||||
#define AWIN_IR1_CLK_REG 0x00b4
|
||||
#define AWIN_IIS_CLK_REG 0x00b8
|
||||
#define AWIN_AC97_CLK_REG 0x00bc
|
||||
#define AWIN_KEYPAD_CLK_REG 0x00c4
|
||||
#define AWIN_USB_CLK_REG 0x00cc
|
||||
#define AWIN_SPI3_CLK_REG 0x00d4
|
||||
#define AWIN_SS_CLK_REG 0x009C
|
||||
#define AWIN_SPI0_CLK_REG 0x00A0
|
||||
#define AWIN_SPI1_CLK_REG 0x00A4
|
||||
#define AWIN_SPI2_CLK_REG 0x00A8
|
||||
#define AWIN_IR0_CLK_REG 0x00B9
|
||||
#define AWIN_IR1_CLK_REG 0x00B4
|
||||
#define AWIN_IIS_CLK_REG 0x00B8
|
||||
#define AWIN_AC97_CLK_REG 0x00BC
|
||||
#define AWIN_SPDIF_CLK_REG 0x00C0
|
||||
#define AWIN_KEYPAD_CLK_REG 0x00C4
|
||||
#define AWIN_SATA_CLK_REG 0x00C8
|
||||
#define AWIN_USB_CLK_REG 0x00CC
|
||||
#define AWIN_SPI3_CLK_REG 0x00D4
|
||||
#define AWIN_DRAM_CLK_REG 0x0100
|
||||
#define AWIN_BE0_SCLK_CFG_REG 0x0100
|
||||
#define AWIN_BE0_SCLK_CFG_REG 0x0100
|
||||
|
|
@ -261,28 +348,43 @@
|
|||
#define AWIN_FE1_CLK_REG 0x0110
|
||||
#define AWIN_MP_CLK_REG 0x0114
|
||||
#define AWIN_LCD0_CH0_CLK_REG 0x0118
|
||||
#define AWIN_LCD1_CH0_CLK_REG 0x011c
|
||||
#define AWIN_LCD1_CH0_CLK_REG 0x011C
|
||||
#define AWIN_CSI_ISP_CLK_REG 0x0120
|
||||
#define AWIN_TVD_CLK_REG 0x0128
|
||||
#define AWIN_LCD0_CH1_CLK_REG 0x012c
|
||||
#define AWIN_LCD0_CH1_CLK_REG 0x012C
|
||||
#define AWIN_LCD1_CH1_CLK_REG 0x0130
|
||||
#define AWIN_CSI0_CLK_REG 0x0134
|
||||
#define AWIN_CSI1_CLK_REG 0x0138
|
||||
#define AWIN_VE_CLK_REG 0x013c
|
||||
#define AWIN_VE_CLK_REG 0x013C
|
||||
#define AWIN_AUDIO_CODEC_CLK_REG 0x0140
|
||||
#define AWIN_AVS_CLK_REG 0x0144
|
||||
#define AWIN_ACE_CLK_REG 0x0148
|
||||
#define AWIN_LVDS_CLK_REG 0x014c
|
||||
#define AWIN_LVDS_CLK_REG 0x014C
|
||||
#define AWIN_HDMI_CLK_REG 0x0150
|
||||
#define AWIN_MALI400_CLK_REG 0x0154
|
||||
#define AWIN_MBUF_SCLK_CFG_REG 0x015C
|
||||
#define AWIN_GMAC_CLK_REG 0x0164
|
||||
#define AWIN_HDM1_RST_REG 0x0170
|
||||
#define AWIN_HDM1_CTLR_REG 0x0174
|
||||
#define AWIN_HDM1_SLOW_CLK_REG 0x0178
|
||||
#define AWIN_HDM1_REPPEAT_CLK_REG 0x017C
|
||||
#define AWIN_CLK_OUTA_REG 0x01F0
|
||||
#define AWIN_CLK_OUTB_REG 0x01F4
|
||||
|
||||
#define AWIN_OSC24M_CFG_ENABLE __BIT(0)
|
||||
|
||||
#define AWIN_PLL_CFG_ENABLE __BIT(31)
|
||||
#define AWIN_PLL_CFG_BYPASS __BIT(30)
|
||||
#define AWIN_PLL5_CFG_DDR_CLK_EN __BIT(29)
|
||||
#define AWIN_PLL_CFG_EXG_MODE __BIT(25)
|
||||
#define AWIN_PLL_CFG_OUT_EXP_DIVP __BITS(17,16)
|
||||
#define AWIN_PLL6_CFG_SATA_CLK_EN __BIT(14)
|
||||
#define AWIN_PLL_CFG_FACTOR_N __BITS(12,8)
|
||||
#define AWIN_PLL5_CFG_LDO_EN __BIT(7)
|
||||
#define AWIN_PLL_CFG_FACTOR_K __BITS(5,4)
|
||||
#define AWIN_PLL5_CFG_FACTOR_M1 __BITS(3,2)
|
||||
#define AWIN_PLL1_SIG_DELT_PAT_IN __BIT(3)
|
||||
#define AWIN_PLL1_SIG_DELT_PAT_EN __BIT(2)
|
||||
#define AWIN_PLL_CFG_FACTOR_M __BITS(1,0)
|
||||
|
||||
#define AWIN_CPU_CLK_SRC_SEL __BITS(17,16)
|
||||
|
|
@ -292,7 +394,8 @@
|
|||
#define AWIN_CPU_CLK_SRC_SEL_200MHZ 3
|
||||
#define AWIN_APB0_CLK_RATIO __BITS(9,8)
|
||||
|
||||
#define AWIN_AHB_GATING0_NC25 __BIT(25)
|
||||
#define AWIN_AHB_GATING0_STIMER __BIT(28)
|
||||
#define AWIN_AHB_GATING0_SATA __BIT(25)
|
||||
#define AWIN_AHB_GATING0_PATA __BIT(24)
|
||||
#define AWIN_AHB_GATING0_SPI3 __BIT(23)
|
||||
#define AWIN_AHB_GATING0_SPI2 __BIT(22)
|
||||
|
|
@ -311,12 +414,15 @@
|
|||
#define AWIN_AHB_GATING0_BIST __BIT(7)
|
||||
#define AWIN_AHB_GATING0_DMA __BIT(6)
|
||||
#define AWIN_AHB_GATING0_SS __BIT(5)
|
||||
#define AWIN_AHB_GATING0_USB_OHCI1 __BIT(4)
|
||||
#define AWIN_AHB_GATING0_USB_EHCI1 __BIT(3)
|
||||
#define AWIN_AHB_GATING0_USB_OHCI0 __BIT(1)
|
||||
#define AWIN_AHB_GATING0_USB_EHCI0 __BIT(1)
|
||||
#define AWIN_AHB_GATING0_USB0 __BIT(0)
|
||||
|
||||
#define AWIN_AHB_GATING1_MALI400 __BIT(20)
|
||||
#define AWIN_AHB_GATING1_MP __BIT(18)
|
||||
#define AWIN_AHB_GATING1_GMAC __BIT(17)
|
||||
#define AWIN_AHB_GATING1_DE_FE1 __BIT(15)
|
||||
#define AWIN_AHB_GATING1_DE_FE0 __BIT(14)
|
||||
#define AWIN_AHB_GATING1_DE_BE1 __BIT(13)
|
||||
|
|
@ -331,42 +437,94 @@
|
|||
#define AWIN_AHB_GATING1_TVD __BIT(1)
|
||||
#define AWIN_AHB_GATING1_VE __BIT(0)
|
||||
|
||||
#define AWIN_APB_GATING0_KEYPAD __BIT(10)
|
||||
#define AWIN_APB_GATING0_IIS2 __BIT(8)
|
||||
#define AWIN_APB_GATING0_IR1 __BIT(7)
|
||||
#define AWIN_APB_GATING0_IR0 __BIT(6)
|
||||
#define AWIN_APB_GATING0_PIO __BIT(5)
|
||||
#define AWIN_APB_GATING0_IIS1 __BIT(4)
|
||||
#define AWIN_APB_GATING0_IIS0 __BIT(3)
|
||||
#define AWIN_APB_GATING0_AC97 __BIT(2)
|
||||
#define AWIN_APB_GATING0_SPDIF __BIT(1)
|
||||
#define AWIN_APB_GATING0_CODEC __BIT(0)
|
||||
|
||||
#define AWIN_APB_GATING1_UART7 __BIT(23)
|
||||
#define AWIN_APB_GATING1_UART6 __BIT(22)
|
||||
#define AWIN_APB_GATING1_UART5 __BIT(21)
|
||||
#define AWIN_APB_GATING1_UART4 __BIT(20)
|
||||
#define AWIN_APB_GATING1_UART3 __BIT(19)
|
||||
#define AWIN_APB_GATING1_UART2 __BIT(18)
|
||||
#define AWIN_APB_GATING1_UART1 __BIT(17)
|
||||
#define AWIN_APB_GATING1_UART0 __BIT(16)
|
||||
#define AWIN_APB_GATING1_TWI4 __BIT(15)
|
||||
#define AWIN_APB_GATING1_PS21 __BIT(7)
|
||||
#define AWIN_APB_GATING1_PS20 __BIT(6)
|
||||
#define AWIN_APB_GATING1_SCR __BIT(5)
|
||||
#define AWIN_APB_GATING1_CAN __BIT(4)
|
||||
#define AWIN_APB_GATING1_TWI3 __BIT(3)
|
||||
#define AWIN_APB_GATING1_TWI2 __BIT(2)
|
||||
#define AWIN_APB_GATING1_TWI1 __BIT(1)
|
||||
#define AWIN_APB_GATING1_TWI0 __BIT(0)
|
||||
|
||||
#define AWIN_CLK_ENABLE __BIT(31)
|
||||
#define AWIN_CLK_SRC_SEL __BITS(25,24)
|
||||
#define AWIN_CLK_SRC_SEL_OSC24M 0
|
||||
#define AWIN_CLK_SRC_SEL_PLL6 1
|
||||
#define AWIN_CLK_SRC_SEL_PLL5 2
|
||||
#define AWIN_CLK_SRC_SEL_LOSC 3
|
||||
#define AWIN_CLK_SRC_SEL_KEYPAD_LOSC 2
|
||||
#define AWIN_CLK_SRC_SEL_SATA_PLL6 0 /* 100 MHz */
|
||||
#define AWIN_CLK_SRC_SEL_SATA_EXT 1
|
||||
#define AWIN_CLK_SRC_SEL_DE_PLL3 0
|
||||
#define AWIN_CLK_SRC_SEL_DE_PLL7 1
|
||||
#define AWIN_CLK_SRC_SEL_DE_PLL5 2
|
||||
#define AWIN_CLK_DIV_RATIO_N __BITS(17,16)
|
||||
#define AWIN_CLK_DIV_RATIO_M __BITS(3,0)
|
||||
|
||||
/* SDMMC definitions */
|
||||
#define AWIN_SDMMC_GCTRL_REG 0x0000
|
||||
#define AWIN_SDMMC_CLKCR_REG 0x0004
|
||||
#define AWIN_SDMMC_TIMEOUT_REG 0x0008
|
||||
#define AWIN_SDMMC_WIDTH_REG 0x000c
|
||||
#define AWIN_SDMMC_BLKSZ_REG 0x0010
|
||||
#define AWIN_SDMMC_BYTECNT_REG 0x0014
|
||||
#define AWIN_SDMMC_CMD_REG 0x0018
|
||||
#define AWIN_SDMMC_ARG_REG 0x001c
|
||||
#define AWIN_SDMMC_RESP0_REG 0x0020
|
||||
#define AWIN_SDMMC_RESP1_REG 0x0024
|
||||
#define AWIN_SDMMC_RESP2_REG 0x0028
|
||||
#define AWIN_SDMMC_RESP3_REG 0x002c
|
||||
#define AWIN_SDMMC_IMASK_REG 0x0030
|
||||
#define AWIN_SDMMC_MINT_REG 0x0034
|
||||
#define AWIN_SDMMC_RINT_REG 0x0038
|
||||
#define AWIN_SDMMC_STATUS_REG 0x003c
|
||||
#define AWIN_SDMMC_FTRGLVL_REG 0x0040
|
||||
#define AWIN_SDMMC_FUNCSEL_REG 0x0044
|
||||
#define AWIN_SDMMC_CBCR_REG 0x0048
|
||||
#define AWIN_SDMMC_BBCR_REG 0x004c
|
||||
#define AWIN_SDMMC_DMAC_REG 0x0080
|
||||
#define AWIN_SDMMC_DLBA_REG 0x0084
|
||||
#define AWIN_SDMMC_IDST_REG 0x0088
|
||||
#define AWIN_SDMMC_IDIE_REG 0x008c
|
||||
#define AWIN_SDMMC_CHDA_REG 0x0090
|
||||
#define AWIN_SDMMC_CBDA_REG 0x0094
|
||||
#define AWIN_SDMMC_FIFO_REG 0x0100
|
||||
#define AWIN_ISS_CLK_SRC_SEL __BITS(17,16)
|
||||
|
||||
#define AWIN_USB_CLK_USBPHY_ENABLE __BIT(8)
|
||||
#define AWIN_USB_CLK_OHCI1_ENABLE __BIT(7)
|
||||
#define AWIN_USB_CLK_OHCI0_ENABLE __BIT(6)
|
||||
#define AWIN_USB_CLK_PHY2_ENABLE __BIT(2)
|
||||
#define AWIN_USB_CLK_PHY1_ENABLE __BIT(1)
|
||||
#define AWIN_USB_CLK_PHY0_ENABLE __BIT(0)
|
||||
|
||||
#define AWIN_DRAM_CLK_ACE_DCLK_ENABLE __BIT(29)
|
||||
#define AWIN_DRAM_CLK_DE_MP_DCLK_ENABLE __BIT(28)
|
||||
#define AWIN_DRAM_CLK_BE1_DCLK_ENABLE __BIT(27)
|
||||
#define AWIN_DRAM_CLK_BE0_DCLK_ENABLE __BIT(26)
|
||||
#define AWIN_DRAM_CLK_FE1_DCLK_ENABLE __BIT(25)
|
||||
#define AWIN_DRAM_CLK_FE0_DCLK_ENABLE __BIT(24)
|
||||
#define AWIN_DRAM_CLK_DCLK_OUT_ENABLE __BIT(16)
|
||||
#define AWIN_DRAM_CLK_TVE1_DCLK_ENABLE __BIT(6)
|
||||
#define AWIN_DRAM_CLK_TVE0_DCLK_ENABLE __BIT(5)
|
||||
#define AWIN_DRAM_CLK_TVD_DCLK_ENABLE __BIT(4)
|
||||
#define AWIN_DRAM_CLK_TS_DCLK_ENABLE __BIT(3)
|
||||
#define AWIN_DRAM_CLK_CSI1_DCLK_ENABLE __BIT(2)
|
||||
#define AWIN_DRAM_CLK_CSI0_DCLK_ENABLE __BIT(1)
|
||||
#define AWIN_DRAM_CLK_VE_DCLK_ENABLE __BIT(0)
|
||||
|
||||
#define AWIN_GMAC_CLK_TXC_DIV __BITS(9,8)
|
||||
#define AWIN_GMAC_CLK_TXC_DIV_1000 0
|
||||
#define AWIN_GMAC_CLK_TXC_DIV_100 1
|
||||
#define AWIN_GMAC_CLK_TXC_DIV_10 2
|
||||
#define AWIN_GMAC_CLK_RXDC __BITS(7,5)
|
||||
#define AWIN_GMAC_CLK_RXIE __BIT(4)
|
||||
#define AWIN_GMAC_CLK_TXIE __BIT(3)
|
||||
#define AWIN_GMAC_CLK_PIT __BIT(2)
|
||||
#define AWIN_GMAC_CLK_TCS __BITS(1,0)
|
||||
#define AWIN_GMAC_CLK_TCS_MII 0
|
||||
#define AWIN_GMAC_CLK_TCS_EXT_125 1
|
||||
#define AWIN_GMAC_CLK_TCS_INT_RGMII 2
|
||||
|
||||
#define AWIN_CLK_OUT_ENABLE __BIT(31)
|
||||
#define AWIN_CLK_OUT_SRC_SEL __BITS(25,24)
|
||||
#define AWIN_CLK_OUT_SRC_SEL_32K 0
|
||||
#define AWIN_CLK_OUT_SRC_SEL_LOSC 1
|
||||
#define AWIN_CLK_OUT_SRC_SEL_OSC24M 2
|
||||
#define AWIN_CLK_OUT_SRC_FACTOR_N __BITS(21,20)
|
||||
#define AWIN_CLK_OUT_SRC_FACTOR_M __BITS(12,8)
|
||||
|
||||
/* USB device offsets */
|
||||
#define AWIN_EHCI_OFFSET 0x0000
|
||||
|
|
@ -408,6 +566,207 @@
|
|||
#define AWIN_INTC_PRIO3_REG 0x008C
|
||||
#define AWIN_INTC_PRIO4_REG 0x0090
|
||||
|
||||
/* [G]PIO Definitions */
|
||||
#define AWIN_PIO_CFG0_REG 0x0000
|
||||
#define AWIN_PIO_CFG1_REG 0x0004
|
||||
#define AWIN_PIO_CFG2_REG 0x0008
|
||||
#define AWIN_PIO_CFG3_REG 0x000c
|
||||
#define AWIN_PIO_DAT_REG 0x0010
|
||||
#define AWIN_PIO_DRV0_REG 0x0014
|
||||
#define AWIN_PIO_DRV1_REG 0x0018
|
||||
#define AWIN_PIO_PUL0_REG 0x001c
|
||||
#define AWIN_PIO_PUL1_REG 0x0020
|
||||
#define AWIN_PIO_GRP_SIZE 0x0024
|
||||
#define AWIN_PIO_INT_CFG0_REG 0x0200
|
||||
#define AWIN_PIO_INT_CFG1_REG 0x0204
|
||||
#define AWIN_PIO_INT_CFG2_REG 0x0208
|
||||
#define AWIN_PIO_INT_CFG3_REG 0x020c
|
||||
#define AWIN_PIO_INT_CTL_REG 0x0210
|
||||
#define AWIN_PIO_INT_STA_REG 0x0214
|
||||
#define AWIN_PIO_INT_DEB_REG 0x0218
|
||||
#define AWIN_PIO_SDR_PAD_DEV_REG 0x0220
|
||||
#define AWIN_PIO_SDR_PAD_PUL_REG 0x0224
|
||||
|
||||
#define AWIN_PIO_CFG_PINMASK(pin) (7 << (4*((pin) & 7)))
|
||||
#define AWIN_PIO_DRV_MASK(pin) ((x) << (2*((pin) & 15)))
|
||||
|
||||
#define AWIN_PIO_FUNC_INPUT 0x0
|
||||
#define AWIN_PIO_FUNC_OUTPUT 0x0
|
||||
|
||||
#define AWIN_PIO_EINT_POSITIVE_EDGE 0x0
|
||||
#define AWIN_PIO_EINT_NEGATIVE_EDGE 0x1
|
||||
#define AWIN_PIO_EINT_HIGH_LEVEL 0x2
|
||||
#define AWIN_PIO_EINT_LOW_LEVEL 0x3
|
||||
#define AWIN_PIO_EINT_DOUBLE_EDGE 0x4
|
||||
|
||||
#define AWIN_PIO_PA_PINS 18
|
||||
#define AWIN_PIO_PA_EMAC_PINS 0x0003ffff /* PA pins 17-0 */
|
||||
#define AWIN_PIO_PA_EMAC_FUNC 2
|
||||
#define AWIN_PIO_PA_CAN_PINS 0x00030000 /* PA pins 17-16 */
|
||||
#define AWIN_PIO_PA_CAN_FUNC 3
|
||||
#define AWIN_PIO_PA_UART7_PINS 0x0000c000 /* PA pins 15-14 */
|
||||
#define AWIN_PIO_PA_UART7_FUNC 3
|
||||
#define AWIN_PIO_PA_UART6_PINS 0x00003000 /* PA pins 13-12 */
|
||||
#define AWIN_PIO_PA_UART6_FUNC 3
|
||||
#define AWIN_PIO_PA_SPI3_PINS 0x000003e0 /* PA pins 9-5 */
|
||||
#define AWIN_PIO_PA_SPI3_FUNC 3
|
||||
#define AWIN_PIO_PA_SPI1_PINS 0x0000001f /* PA pins 0-4 */
|
||||
#define AWIN_PIO_PA_SPI1_FUNC 3
|
||||
#define AWIN_PIO_PA_UART1_PINS 0x0003fc00 /* PA pins 17-10 */
|
||||
#define AWIN_PIO_PA_UART1_FUNC 4
|
||||
#define AWIN_PIO_PA_UART2_PINS 0x0000000f /* PA pins 3-0 */
|
||||
#define AWIN_PIO_PA_UART2_FUNC 4
|
||||
#define AWIN_PIO_PA_GMAC_PINS 0x0003ffff /* PA pins 17-0 */
|
||||
#define AWIN_PIO_PA_GMAC_FUNC 5
|
||||
#define AWIN_PIO_PA_I2S1_PINS 0x0003c200 /* PA pins 17-14,9 */
|
||||
#define AWIN_PIO_PA_I2S1_FUNC 5
|
||||
|
||||
#define AWIN_PIO_PB_PINS 24
|
||||
#define AWIN_PIO_PB_UART0_PINS 0x00c00000 /* PB pins 23-22 */
|
||||
#define AWIN_PIO_PB_UART0_FUNC 2
|
||||
#define AWIN_PIO_PB_TWI2_PINS 0x00300000 /* PB pins 21-20 */
|
||||
#define AWIN_PIO_PB_TWI2_FUNC 2
|
||||
#define AWIN_PIO_PB_TWI1_PINS 0x000c0000 /* PB pins 19-18 */
|
||||
#define AWIN_PIO_PB_TWI1_FUNC 2
|
||||
#define AWIN_PIO_PB_SPI2_PINS 0x0003e000 /* PB pins 17-13 */
|
||||
#define AWIN_PIO_PB_SPI2_FUNC 2
|
||||
#define AWIN_PIO_PB_I2S_PINS 0x00001fe0 /* PB pins 12-5 */
|
||||
#define AWIN_PIO_PB_I2S_FUNC 2
|
||||
#define AWIN_PIO_PB_IR0_PINS 0x00000018 /* PB pins 4-3 */
|
||||
#define AWIN_PIO_PB_IR0_FUNC 2
|
||||
#define AWIN_PIO_PB_PWN_PINS 0x00000004 /* PB pins 2-2 */
|
||||
#define AWIN_PIO_PB_PWN_FUNC 2
|
||||
#define AWIN_PIO_PB_TWI0_PINS 0x00000003 /* PB pins 1-0 */
|
||||
#define AWIN_PIO_PB_TWI0_FUNC 2
|
||||
#define AWIN_PIO_PB_IR1_PINS 0x00c00000 /* PB pins 23-22 */
|
||||
#define AWIN_PIO_PB_IR1_FUNC 3
|
||||
#define AWIN_PIO_PB_JTAG_PINS 0x0003c000 /* PB pins 17-14 */
|
||||
#define AWIN_PIO_PB_JTAG_FUNC 3
|
||||
#define AWIN_PIO_PB_AC97_PINS 0x000011e0 /* PB pins 12,8-5 */
|
||||
#define AWIN_PIO_PB_AC97_FUNC 3
|
||||
#define AWIN_PIO_PB_SPDIF_PINS 0x00003008 /* PB pins 13-12,3-3 */
|
||||
#define AWIN_PIO_PB_SPDIF_FUNC 4
|
||||
#define AWIN_PIO_PB_STANBYWFI_PINS 0x00000008 /* PB pins 3-3 */
|
||||
#define AWIN_PIO_PB_STANBYWFI_FUNC 6
|
||||
|
||||
#define AWIN_PIO_PC_PINS 25
|
||||
#define AWIN_PIO_PC_NAND_PINS 0x017fffff /* PC pins 24,22-0 */
|
||||
#define AWIN_PIO_PC_NAND_FUNC 2
|
||||
#define AWIN_PIO_PC_SPI0_PINS 0x00800007 /* PC pins 23-23,3-0 */
|
||||
#define AWIN_PIO_PC_SPI0_FUNC 3
|
||||
#define AWIN_PIO_PC_SPI2_PINS 0x00f80000 /* PC pins 23-19 */
|
||||
#define AWIN_PIO_PC_SPI2_FUNC 3
|
||||
#define AWIN_PIO_PC_SDC2_PINS 0x00000fc0 /* PC pins 11-6 */
|
||||
#define AWIN_PIO_PC_SDC2_FUNC 3
|
||||
#define AWIN_PIO_PC_EINT_PINS 0x00780000 /* PC pins 22-19 */
|
||||
#define AWIN_PIO_PC_EINT_FUNC 3
|
||||
|
||||
#define AWIN_PIO_PD_PINS 28
|
||||
#define AWIN_PIO_PD_LCD0_PINS 0x0fffffff /* PD pins 27-0 */
|
||||
#define AWIN_PIO_PD_LCD0_FUNC 2
|
||||
#define AWIN_PIO_PD_SMC_PINS 0x0fe00000 /* PD pins 27-21 */
|
||||
#define AWIN_PIO_PD_SMC_FUNC 3
|
||||
#define AWIN_PIO_PD_CSI1_PINS 0x00100000 /* PD pins 20-20 */
|
||||
#define AWIN_PIO_PD_CSI1_FUNC 3
|
||||
#define AWIN_PIO_PD_LVDS1_PINS 0x000ffc00 /* PD pins 19-10 */
|
||||
#define AWIN_PIO_PD_LVDS1_FUNC 3
|
||||
#define AWIN_PIO_PD_LVDS0_PINS 0x000003ff /* PD pins 9-0 */
|
||||
#define AWIN_PIO_PD_LVDS0_FUNC 3
|
||||
|
||||
#define AWIN_PIO_PE_PINS 12
|
||||
#define AWIN_PIO_PE_TS_PINS 0x00000fff /* PE pins 11-0 */
|
||||
#define AWIN_PIO_PE_TS_FUNC 2
|
||||
#define AWIN_PIO_PE_CSI0_PINS 0x00000fff /* PE pins 11-0 */
|
||||
#define AWIN_PIO_PE_CSI0_FUNC 3
|
||||
#define AWIN_PIO_PE_SMC_PINS 0x00000020 /* PE pins 5-5 */
|
||||
#define AWIN_PIO_PE_SMC_FUNC 4
|
||||
|
||||
#define AWIN_PIO_PF_PINS 6
|
||||
#define AWIN_PIO_PF_SDC0_PINS 0x0000003f /* PF pins 5-0 */
|
||||
#define AWIN_PIO_PF_SDC0_FUNC 2
|
||||
#define AWIN_PIO_PF_UART0_PINS 0x00000014 /* PF pins 4,2 */
|
||||
#define AWIN_PIO_PF_UART0_FUNC 3
|
||||
#define AWIN_PIO_PF_JTAG_PINS 0x0000002b /* PF pins 5,3,1-0 */
|
||||
#define AWIN_PIO_PF_JTAG_FUNC 4
|
||||
|
||||
#define AWIN_PIO_PG_PINS 12
|
||||
#define AWIN_PIO_PG_TS1_PINS 0x00000fff /* PG pins 11-0 */
|
||||
#define AWIN_PIO_PG_TS1_FUNC 2
|
||||
#define AWIN_PIO_PG_CSI1_PINS 0x00000fff /* PG pins 11-0 */
|
||||
#define AWIN_PIO_PG_CSI1_FUNC 3
|
||||
#define AWIN_PIO_PG_UART4_PINS 0x00000c00 /* PG pins 11-10 */
|
||||
#define AWIN_PIO_PG_UART4_FUNC 4
|
||||
#define AWIN_PIO_PG_UART3_PINS 0x00000300 /* PG pins 9-8 */
|
||||
#define AWIN_PIO_PG_UART3_FUNC 4
|
||||
#define AWIN_PIO_PG_SDC1_PINS 0x0000003f /* PG pins 5-0 */
|
||||
#define AWIN_PIO_PG_SDC1_FUNC 4
|
||||
#define AWIN_PIO_PG_CSI0_PINS 0x00000ff0 /* PG pins 11-4 */
|
||||
#define AWIN_PIO_PG_CSI0_FUNC 5
|
||||
|
||||
#define AWIN_PIO_PH_PINS 28
|
||||
#define AWIN_PIO_PH_LCD1_PINS 0x0fffffff /* PH pins 27-0 */
|
||||
#define AWIN_PIO_PH_LCD1_FUNC 2
|
||||
#define AWIN_PIO_PH_PATA_PINS 0x0fffffff /* PH pins 27-0 */
|
||||
#define AWIN_PIO_PH_PATA_FUNC 3
|
||||
#define AWIN_PIO_PH_EMAC_PINS 0x0fffcf00 /* PH pins 27-14,11-8 */
|
||||
#define AWIN_PIO_PH_EMAC_FUNC 3
|
||||
#define AWIN_PIO_PH_KP_PINS 0x0fcfcf00 /* PH pins 27-22,19-14,11-8 */
|
||||
#define AWIN_PIO_PH_KP_FUNC 4
|
||||
#define AWIN_PIO_PH_CAN_PINS 0x00300000 /* PH pins 21-20 */
|
||||
#define AWIN_PIO_PH_CAN_FUNC 4
|
||||
#define AWIN_PIO_PH_PS21_PINS 0x00003000 /* PH pins 13-12 */
|
||||
#define AWIN_PIO_PH_PS21_FUNC 4
|
||||
#define AWIN_PIO_PH_UART5_PINS 0x000000c0 /* PH pins 7-6 */
|
||||
#define AWIN_PIO_PH_UART5_FUNC 4
|
||||
#define AWIN_PIO_PH_UART4_PINS 0x00000030 /* PH pins 5-4 */
|
||||
#define AWIN_PIO_PH_UART4_FUNC 4
|
||||
#define AWIN_PIO_PH_UART3_PINS 0x0000000f /* PH pins 3-0 */
|
||||
#define AWIN_PIO_PH_UART3_FUNC 4
|
||||
#define AWIN_PIO_PH_SDC1_PINS 0x0fc00000 /* PH pins 27-23 */
|
||||
#define AWIN_PIO_PH_SDC1_FUNC 5
|
||||
#define AWIN_PIO_PH_SMC_PINS 0x000fe000 /* PH pins 19-13 */
|
||||
#define AWIN_PIO_PH_SMC_FUNC 5
|
||||
#define AWIN_PIO_PH_MS_PINS 0x00000fc0 /* PH pins 11-6 */
|
||||
#define AWIN_PIO_PH_MS_FUNC 5
|
||||
#define AWIN_PIO_PH_EINT_PINS 0x003fffff /* PH pins 21-0 */
|
||||
#define AWIN_PIO_PH_EINT_FUNC 6
|
||||
#define AWIN_PIO_PH_CSI1_PINS 0x0fffffff /* PH pins 27-0 */
|
||||
#define AWIN_PIO_PH_CSI1_FUNC 7
|
||||
|
||||
#define AWIN_PIO_PI_PINS 22
|
||||
#define AWIN_PIO_PI_PS20_PINS 0x00300000 /* PI pins 21-20 */
|
||||
#define AWIN_PIO_PI_PS20_FUNC 2
|
||||
#define AWIN_PIO_PI_SPI1_PINS 0x000f0000 /* PI pins 7-4 */
|
||||
#define AWIN_PIO_PI_SPI1_FUNC 2
|
||||
#define AWIN_PIO_PI_SDC3_PINS 0x000003f0 /* PI pins 9-4 */
|
||||
#define AWIN_PIO_PI_SDC3_FUNC 2
|
||||
#define AWIN_PIO_PI_PWM1_PINS 0x00000008 /* PI pins 3-3 */
|
||||
#define AWIN_PIO_PI_PWM1_FUNC 2
|
||||
#define AWIN_PIO_PI_UART7_PINS 0x00300000 /* PI pins 21-20 */
|
||||
#define AWIN_PIO_PI_UART7_FUNC 3
|
||||
#define AWIN_PIO_PI_UART2_PINS 0x000f0000 /* PI pins 19-16 */
|
||||
#define AWIN_PIO_PI_UART2_FUNC 3
|
||||
#define AWIN_PIO_PI_PS21_PINS 0x0000c000 /* PI pins 15-14 */
|
||||
#define AWIN_PIO_PI_PS21_FUNC 3
|
||||
#define AWIN_PIO_PI_UART6_PINS 0x00003000 /* PI pins 13-12 */
|
||||
#define AWIN_PIO_PI_UART6_FUNC 3
|
||||
#define AWIN_PIO_PI_UART5_PINS 0x00000c00 /* PI pins 11-10 */
|
||||
#define AWIN_PIO_PI_UART5_FUNC 3
|
||||
#define AWIN_PIO_PI_TWI4_PINS 0x0000000c /* PI pins 3-2 */
|
||||
#define AWIN_PIO_PI_TWI4_FUNC 3
|
||||
#define AWIN_PIO_PI_TWI3_PINS 0x00000003 /* PI pins 1-0 */
|
||||
#define AWIN_PIO_PI_TWI3_FUNC 3
|
||||
#define AWIN_PIO_PI_HSXX_PINS 0x00300000 /* PI pins 21-20 */
|
||||
#define AWIN_PIO_PI_HSXX_FUNC 4
|
||||
#define AWIN_PIO_PI_TCLKIN_PINS 0x0000c000 /* PI pins 15-14 */
|
||||
#define AWIN_PIO_PI_TCLKIN_FUNC 4
|
||||
#define AWIN_PIO_PI_CLKOUTB_PINS 0x00002000 /* PI pins 13-13 */
|
||||
#define AWIN_PIO_PI_CLKOUTB_FUNC 4
|
||||
#define AWIN_PIO_PI_CLKOUTA_PINS 0x00002000 /* PI pins 12-12 */
|
||||
#define AWIN_PIO_PI_CLKOUTA_FUNC 4
|
||||
#define AWIN_PIO_PI_EINT_PINS 0x000ffc00 /* PI pins 19-10 */
|
||||
#define AWIN_PIO_PI_EINT_FUNC 6
|
||||
|
||||
/* Standard Timer (A10) */
|
||||
#define AWIN_TMR_IRQ_EN_REG 0x0000
|
||||
#define AWIN_TMR_IRQ_STA_REG 0x0004
|
||||
|
|
@ -451,6 +810,27 @@
|
|||
#define AWIN_TMR_GP_DATA3_REG 0x012C
|
||||
#define AWIN_CPU_CFG_REG 0x0140
|
||||
|
||||
#define AWIN_TMR_IRQ_WDOG __BIT(8)
|
||||
#define AWIN_TMR_IRQ_TIMER5 __BIT(5)
|
||||
#define AWIN_TMR_IRQ_TIMER4 __BIT(4)
|
||||
#define AWIN_TMR_IRQ_TIMER3 __BIT(3)
|
||||
#define AWIN_TMR_IRQ_TIMER2 __BIT(2)
|
||||
#define AWIN_TMR_IRQ_TIMER1 __BIT(1)
|
||||
#define AWIN_TMR_IRQ_TIMER0 __BIT(0)
|
||||
|
||||
#define AWIN_TMR_CTRL_SINGLE_SHOT __BIT(7)
|
||||
#define AWIN_TMR_CTRL_PRESCALE __BITS(6,4)
|
||||
#define AWIN_TMR_CTRL_CLK_SRC __BITS(3,2)
|
||||
#define AWIN_TMR_CTRL_CLK_SRC_LOSC 0
|
||||
#define AWIN_TMR_CTRL_CLK_SRC_OSC24M 1
|
||||
#define AWIN_TMR_CTRL_CLK_SRC_PLL6_DIV6 2
|
||||
#define AWIN_TMR_CTRL_RELOAD __BIT(1)
|
||||
#define AWIN_TMR_CTRL_ENABLE __BIT(0)
|
||||
|
||||
#define AWIN_CNT64_CTRL_PLL6_DIV6 __BIT(2)
|
||||
#define AWIN_CNT64_CTRL_RL_ENABLE __BIT(1)
|
||||
#define AWIN_CNT64_CTRL_CLR_ENABLE __BIT(0)
|
||||
|
||||
#define AWIN_WDOG_CTRL_RSTART __BIT(1)
|
||||
#define AWIN_WDOG_MODE_INTV __BITS(6,3)
|
||||
#define AWIN_WDOG_MODE_INTV_HALFSEC 0
|
||||
|
|
@ -499,7 +879,7 @@
|
|||
#define AWIN_CPU1_STATUS_REG 0x0088
|
||||
#define AWIN_GENER_CTRL_REG 0x0184
|
||||
#define AWIN_EVENT_IN_REG 0x0190
|
||||
#define AWIN_PRIVATE_REG 0x01a4
|
||||
#define AWIN_PRIVATE_REG 0x01A4
|
||||
#define AWIN_IDLE_CNT0_LOW_REG 0x0200
|
||||
#define AWIN_IDLE_CNT0_HIGH_REG 0x0204
|
||||
#define AWIN_IDLE_CNT0_CTRL_REG 0x0208
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
__KERNEL_RCSID(1, "$NetBSD: awin_sdhc.c,v 1.2 2013/09/04 09:14:57 jmcneill Exp $");
|
||||
__KERNEL_RCSID(1, "$NetBSD: awin_sdhc.c,v 1.3 2013/09/07 00:35:52 matt Exp $");
|
||||
|
||||
#include <sys/bus.h>
|
||||
#include <sys/device.h>
|
||||
|
|
@ -55,26 +55,41 @@ struct awin_sdhc_softc {
|
|||
void *asc_ih;
|
||||
};
|
||||
|
||||
static const struct awin_gpio_pinset awin_sdhc_pinsets[] = {
|
||||
{ 'F', AWIN_PIO_PF_SDC0_FUNC, AWIN_PIO_PF_SDC0_PINS },
|
||||
{ 'G', AWIN_PIO_PG_SDC1_FUNC, AWIN_PIO_PG_SDC1_PINS },
|
||||
{ 'C', AWIN_PIO_PC_SDC2_FUNC, AWIN_PIO_PC_SDC2_PINS },
|
||||
{ 'I', AWIN_PIO_PI_SDC3_FUNC, AWIN_PIO_PI_SDC3_PINS },
|
||||
};
|
||||
|
||||
static const struct awin_gpio_pinset awin_sdhc_alt_pinsets[] = {
|
||||
{ 0, 0, 0 },
|
||||
{ 'H', AWIN_PIO_PH_SDC1_FUNC, AWIN_PIO_PH_SDC1_PINS },
|
||||
{ 0, 0, 0 },
|
||||
{ 0, 0, 0 },
|
||||
};
|
||||
|
||||
CFATTACH_DECL_NEW(awin_sdhc, sizeof(struct awin_sdhc_softc),
|
||||
awin_sdhc_match, awin_sdhc_attach, NULL, NULL);
|
||||
|
||||
static int awinsdhc_ports;
|
||||
static int awin_sdhc_ports;
|
||||
|
||||
static int
|
||||
awin_sdhc_match(device_t parent, cfdata_t cf, void *aux)
|
||||
{
|
||||
struct awinio_attach_args * const aio = aux;
|
||||
const struct awin_locators * const loc = &aio->aio_loc;
|
||||
const int port = cf->cf_loc[AWINIOCF_PORT];
|
||||
const struct awin_gpio_pinset * const pinset = loc->loc_port
|
||||
+ ((cf->cf_flags & 1) ? awin_sdhc_alt_pinsets : awin_sdhc_pinsets);
|
||||
|
||||
if (strcmp(cf->cf_name, loc->loc_name))
|
||||
KASSERT(!strcmp(cf->cf_name, loc->loc_name));
|
||||
KASSERT(cf->cf_loc[AWINIOCF_PORT] == AWINIOCF_PORT_DEFAULT
|
||||
|| cf->cf_loc[AWINIOCF_PORT] == loc->loc_port);
|
||||
KASSERT((awin_sdhc_ports & __BIT(loc->loc_port)) == 0);
|
||||
|
||||
if (!awin_gpio_pinset_available(pinset))
|
||||
return 0;
|
||||
|
||||
if (port != AWINIOCF_PORT_DEFAULT && port != loc->loc_port)
|
||||
return 0;
|
||||
|
||||
KASSERT((awinsdhc_ports & __BIT(loc->loc_port)) == 0);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
@ -85,9 +100,15 @@ awin_sdhc_attach(device_t parent, device_t self, void *aux)
|
|||
struct sdhc_softc * const sc = &asc->asc_sc;
|
||||
struct awinio_attach_args * const aio = aux;
|
||||
const struct awin_locators * const loc = &aio->aio_loc;
|
||||
cfdata_t cf = device_cfdata(self);
|
||||
const struct awin_gpio_pinset * const pinset = loc->loc_port
|
||||
+ ((cf->cf_flags & 1) ? awin_sdhc_alt_pinsets : awin_sdhc_pinsets);
|
||||
int error;
|
||||
|
||||
awinsdhc_ports |= __BIT(loc->loc_port);
|
||||
awin_sdhc_ports |= __BIT(loc->loc_port);
|
||||
|
||||
awin_gpio_pinset_acquire(pinset);
|
||||
|
||||
asc->asc_bst = aio->aio_core_bst;
|
||||
bus_space_subregion(asc->asc_bst, aio->aio_core_bsh,
|
||||
loc->loc_offset, loc->loc_size, &asc->asc_bsh);
|
||||
|
|
|
|||
|
|
@ -31,13 +31,16 @@
|
|||
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
__KERNEL_RCSID(1, "$NetBSD: awin_twi.c,v 1.1 2013/09/04 02:39:01 matt Exp $");
|
||||
__KERNEL_RCSID(1, "$NetBSD: awin_twi.c,v 1.2 2013/09/07 00:35:52 matt Exp $");
|
||||
|
||||
#include <sys/bus.h>
|
||||
#include <sys/device.h>
|
||||
#include <sys/intr.h>
|
||||
#include <sys/systm.h>
|
||||
|
||||
#include <dev/i2c/i2cvar.h>
|
||||
#include <dev/i2c/gttwsivar.h>
|
||||
|
||||
#include <arm/allwinner/awin_reg.h>
|
||||
#include <arm/allwinner/awin_var.h>
|
||||
|
||||
|
|
@ -45,10 +48,18 @@ static int awin_twi_match(device_t, cfdata_t, void *);
|
|||
static void awin_twi_attach(device_t, device_t, void *);
|
||||
|
||||
struct awin_twi_softc {
|
||||
device_t sc_dev;
|
||||
bus_space_tag_t sc_bst;
|
||||
bus_space_handle_t sc_bsh;
|
||||
bus_dma_tag_t sc_dmat;
|
||||
struct gttwsi_softc asc_sc;
|
||||
void *asc_ih;
|
||||
};
|
||||
|
||||
static int awin_twi_ports;
|
||||
|
||||
static const struct awin_gpio_pinset awin_twi_pinsets[] = {
|
||||
[0] = { 'B', AWIN_PIO_PB_TWI0_FUNC, AWIN_PIO_PB_TWI0_PINS },
|
||||
[1] = { 'B', AWIN_PIO_PB_TWI1_FUNC, AWIN_PIO_PB_TWI1_PINS },
|
||||
[2] = { 'B', AWIN_PIO_PB_TWI2_FUNC, AWIN_PIO_PB_TWI2_PINS },
|
||||
[3] = { 'I', AWIN_PIO_PI_TWI3_FUNC, AWIN_PIO_PI_TWI3_PINS },
|
||||
[4] = { 'I', AWIN_PIO_PI_TWI4_FUNC, AWIN_PIO_PI_TWI4_PINS },
|
||||
};
|
||||
|
||||
CFATTACH_DECL_NEW(awin_twi, sizeof(struct awin_twi_softc),
|
||||
|
|
@ -60,10 +71,20 @@ awin_twi_match(device_t parent, cfdata_t cf, void *aux)
|
|||
struct awinio_attach_args * const aio = aux;
|
||||
const struct awin_locators * const loc = &aio->aio_loc;
|
||||
|
||||
if (strcmp(cf->cf_name, loc->loc_name))
|
||||
KASSERT(!strcmp(cf->cf_name, loc->loc_name));
|
||||
KASSERT(cf->cf_loc[AWINIOCF_PORT] == AWINIOCF_PORT_DEFAULT
|
||||
|| cf->cf_loc[AWINIOCF_PORT] == loc->loc_port);
|
||||
KASSERT((awin_twi_ports & __BIT(loc->loc_port)) == 0);
|
||||
|
||||
/*
|
||||
* We don't have alternative mappings so if one is requested
|
||||
* fail the match.
|
||||
*/
|
||||
if (cf->cf_flags & 1)
|
||||
return 0;
|
||||
|
||||
KASSERT(cf->cf_loc[AWINIOCF_PORT] == AWINIOCF_PORT_DEFAULT);
|
||||
if (!awin_gpio_pinset_available(&awin_twi_pinsets[loc->loc_port]))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -71,17 +92,43 @@ awin_twi_match(device_t parent, cfdata_t cf, void *aux)
|
|||
static void
|
||||
awin_twi_attach(device_t parent, device_t self, void *aux)
|
||||
{
|
||||
struct awin_twi_softc * const sc = device_private(self);
|
||||
struct awin_twi_softc * const asc = device_private(self);
|
||||
struct awinio_attach_args * const aio = aux;
|
||||
const struct awin_locators * const loc = &aio->aio_loc;
|
||||
bus_space_handle_t bsh;
|
||||
|
||||
sc->sc_dev = self;
|
||||
awin_twi_ports |= __BIT(loc->loc_port);
|
||||
|
||||
sc->sc_bst = aio->aio_core_bst;
|
||||
sc->sc_dmat = aio->aio_dmat;
|
||||
bus_space_subregion(sc->sc_bst, aio->aio_core_bsh,
|
||||
loc->loc_offset, loc->loc_size, &sc->sc_bsh);
|
||||
/*
|
||||
* Acquite the PIO pins needed for the TWI port.
|
||||
*/
|
||||
awin_gpio_pinset_acquire(&awin_twi_pinsets[loc->loc_port]);
|
||||
|
||||
aprint_naive("\n");
|
||||
aprint_normal("\n");
|
||||
/*
|
||||
* Get a bus space handle for this TWI port.
|
||||
*/
|
||||
bus_space_subregion(aio->aio_core_bst, aio->aio_core_bsh,
|
||||
loc->loc_offset, loc->loc_size, &bsh);
|
||||
|
||||
/*
|
||||
* Do the MI attach
|
||||
*/
|
||||
gttwsi_attach_subr(self, aio->aio_core_bst, bsh);
|
||||
|
||||
/*
|
||||
* Establish interrupt for it
|
||||
*/
|
||||
asc->asc_ih = intr_establish(loc->loc_intr, IPL_BIO, IST_LEVEL,
|
||||
gttwsi_intr, &asc->asc_sc);
|
||||
if (asc->asc_ih == NULL) {
|
||||
aprint_error_dev(self, "failed to establish interrupt %d\n",
|
||||
loc->loc_intr);
|
||||
return;
|
||||
}
|
||||
aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
|
||||
|
||||
/*
|
||||
* Configure its children
|
||||
*/
|
||||
gttwsi_config_children(self);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@
|
|||
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
__KERNEL_RCSID(1, "$NetBSD: awin_usb.c,v 1.1 2013/09/04 02:39:01 matt Exp $");
|
||||
__KERNEL_RCSID(1, "$NetBSD: awin_usb.c,v 1.2 2013/09/07 00:35:52 matt Exp $");
|
||||
|
||||
#include <sys/bus.h>
|
||||
#include <sys/device.h>
|
||||
|
|
@ -64,9 +64,8 @@ struct awinusb_softc {
|
|||
|
||||
device_t usbsc_ohci_dev;
|
||||
device_t usbsc_ehci_dev;
|
||||
void *usbsc_ohci_sc;
|
||||
void *usbsc_ehci_sc;
|
||||
void *usbsc_ih;
|
||||
void *usbsc_ohci_ih;
|
||||
void *usbsc_ehci_ih;
|
||||
};
|
||||
|
||||
struct awinusb_attach_args {
|
||||
|
|
@ -74,9 +73,14 @@ struct awinusb_attach_args {
|
|||
bus_dma_tag_t usbaa_dmat;
|
||||
bus_space_tag_t usbaa_bst;
|
||||
bus_space_handle_t usbaa_bsh;
|
||||
bus_space_handle_t usbaa_ccm_bsh;
|
||||
bus_size_t usbaa_size;
|
||||
int usbaa_port;
|
||||
};
|
||||
|
||||
static const int awinusb_ohci_irqs[2] = { AWIN_IRQ_USB3, AWIN_IRQ_USB4 };
|
||||
static const int awinusb_ehci_irqs[2] = { AWIN_IRQ_USB1, AWIN_IRQ_USB2 };
|
||||
|
||||
#ifdef OHCI_DEBUG
|
||||
#define OHCI_DPRINTF(x) if (ohcidebug) printf x
|
||||
extern int ohcidebug;
|
||||
|
|
@ -104,11 +108,17 @@ ohci_awinusb_match(device_t parent, cfdata_t cf, void *aux)
|
|||
static void
|
||||
ohci_awinusb_attach(device_t parent, device_t self, void *aux)
|
||||
{
|
||||
struct awinusb_softc * const usbsc = device_private(parent);
|
||||
struct ohci_softc * const sc = device_private(self);
|
||||
struct awinusb_attach_args * const usbaa = aux;
|
||||
|
||||
sc->sc_dev = self;
|
||||
|
||||
#if 0
|
||||
awinusb_enable(usbaa->usbaa_bst, usbaa->usbaa_ccm_bsh,
|
||||
AWIN_USB_CLK_USBPHY1_RST, AWIN_APB_GATING1_OHCI0);
|
||||
#endif
|
||||
|
||||
sc->iot = usbaa->usbaa_bst;
|
||||
sc->ioh = usbaa->usbaa_bsh;
|
||||
sc->sc_size = usbaa->usbaa_size;
|
||||
|
|
@ -128,6 +138,16 @@ ohci_awinusb_attach(device_t parent, device_t self, void *aux)
|
|||
/* Attach usb device. */
|
||||
sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint);
|
||||
}
|
||||
|
||||
const int irq = awinusb_ohci_irqs[usbaa->usbaa_port];
|
||||
usbsc->usbsc_ohci_ih = intr_establish(irq, IPL_USB,
|
||||
IST_LEVEL, ohci_intr, sc);
|
||||
if (usbsc->usbsc_ohci_ih == NULL) {
|
||||
aprint_error_dev(self, "failed to establish interrupt %d\n",
|
||||
irq);
|
||||
return;
|
||||
}
|
||||
aprint_normal_dev(self, "interrupting on irq %d\n", irq);
|
||||
}
|
||||
|
||||
#ifdef EHCI_DEBUG
|
||||
|
|
@ -187,24 +207,16 @@ ehci_awinusb_attach(device_t parent, device_t self, void *aux)
|
|||
/* Attach usb device. */
|
||||
sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* There's only IRQ shared between both OCHI and EHCI devices.
|
||||
*/
|
||||
static int
|
||||
awinusb_intr(void *arg)
|
||||
{
|
||||
struct awinusb_softc * const usbsc = arg;
|
||||
int rv0 = 0, rv1 = 0;
|
||||
|
||||
if (usbsc->usbsc_ohci_sc)
|
||||
rv0 = ohci_intr(usbsc->usbsc_ohci_sc);
|
||||
|
||||
if (usbsc->usbsc_ehci_sc)
|
||||
rv1 = ehci_intr(usbsc->usbsc_ehci_sc);
|
||||
|
||||
return rv0 ? rv0 : rv1;
|
||||
const int irq = awinusb_ehci_irqs[usbaa->usbaa_port];
|
||||
usbsc->usbsc_ehci_ih = intr_establish(irq, IPL_USB,
|
||||
IST_LEVEL, ehci_intr, sc);
|
||||
if (usbsc->usbsc_ehci_ih == NULL) {
|
||||
aprint_error_dev(self, "failed to establish interrupt %d\n",
|
||||
irq);
|
||||
return;
|
||||
}
|
||||
aprint_normal_dev(self, "interrupting on irq %d\n", irq);
|
||||
}
|
||||
|
||||
static int awinusb_match(device_t, cfdata_t, void *);
|
||||
|
|
@ -257,9 +269,13 @@ awinusb_attach(device_t parent, device_t self, void *aux)
|
|||
/*
|
||||
* Bring the PHYs out of reset.
|
||||
*/
|
||||
bus_space_write_4(usbsc->usbsc_bst, usbsc->usbsc_ehci_bsh,
|
||||
uint32_t v = bus_space_read_4(usbsc->usbsc_bst, aio->aio_ccm_bsh,
|
||||
AWIN_USB_CLK_REG);
|
||||
|
||||
v &= ~(loc->loc_port == 0 ? AWIN_USB_CLK_PHY1_RST : AWIN_USB_CLK_PHY2_RST);
|
||||
bus_space_write_4(usbsc->usbsc_bst, aio->aio_ccm_bsh,
|
||||
USBH_PHY_CTRL_P0, USBH_PHY_CTRL_INIT);
|
||||
bus_space_write_4(usbsc->usbsc_bst, usbsc->usbsc_ehci_bsh,
|
||||
bus_space_write_4(usbsc->usbsc_bst, aio->aio_ccm_bsh,
|
||||
USBH_PHY_CTRL_P1, USBH_PHY_CTRL_INIT);
|
||||
#endif
|
||||
|
||||
|
|
@ -281,31 +297,23 @@ awinusb_attach(device_t parent, device_t self, void *aux)
|
|||
.usbaa_dmat = usbsc->usbsc_dmat,
|
||||
.usbaa_bst = usbsc->usbsc_bst,
|
||||
.usbaa_bsh = usbsc->usbsc_ohci_bsh,
|
||||
.usbaa_ccm_bsh = aio->aio_ccm_bsh,
|
||||
.usbaa_size = AWIN_OHCI_SIZE,
|
||||
.usbaa_port = loc->loc_port,
|
||||
};
|
||||
|
||||
usbsc->usbsc_ohci_dev = config_found(self, &usbaa_ohci, NULL);
|
||||
if (usbsc->usbsc_ohci_dev != NULL)
|
||||
usbsc->usbsc_ohci_sc = device_private(usbsc->usbsc_ohci_dev);
|
||||
|
||||
struct awinusb_attach_args usbaa_ehci = {
|
||||
.usbaa_name = "ehci",
|
||||
.usbaa_dmat = usbsc->usbsc_dmat,
|
||||
.usbaa_bst = usbsc->usbsc_bst,
|
||||
.usbaa_bsh = usbsc->usbsc_ehci_bsh,
|
||||
.usbaa_ccm_bsh = aio->aio_ccm_bsh,
|
||||
.usbaa_size = AWIN_EHCI_SIZE,
|
||||
.usbaa_port = loc->loc_port,
|
||||
};
|
||||
|
||||
usbsc->usbsc_ehci_dev = config_found(self, &usbaa_ehci, NULL);
|
||||
if (usbsc->usbsc_ehci_dev != NULL)
|
||||
usbsc->usbsc_ehci_sc = device_private(usbsc->usbsc_ehci_dev);
|
||||
config_found(self, &usbaa_ehci, NULL);
|
||||
|
||||
usbsc->usbsc_ih = intr_establish(loc->loc_intr, IPL_USB, IST_LEVEL,
|
||||
awinusb_intr, usbsc);
|
||||
if (usbsc->usbsc_ih == NULL) {
|
||||
aprint_error_dev(self, "failed to establish interrupt %d\n",
|
||||
loc->loc_intr);
|
||||
return;
|
||||
}
|
||||
aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: awin_var.h,v 1.3 2013/09/04 17:45:40 matt Exp $ */
|
||||
/* $NetBSD: awin_var.h,v 1.4 2013/09/07 00:35:52 matt Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2013 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
|
|
@ -53,9 +53,16 @@ struct awinio_attach_args {
|
|||
bus_space_tag_t aio_core_bst;
|
||||
bus_space_tag_t aio_core_a4x_bst;
|
||||
bus_space_handle_t aio_core_bsh;
|
||||
bus_space_handle_t aio_ccm_bsh;
|
||||
bus_dma_tag_t aio_dmat;
|
||||
};
|
||||
|
||||
struct awin_gpio_pinset {
|
||||
uint8_t pinset_group;
|
||||
uint8_t pinset_func;
|
||||
uint32_t pinset_mask;
|
||||
};
|
||||
|
||||
extern struct bus_space awin_bs_tag;
|
||||
extern struct bus_space awin_a4x_bs_tag;
|
||||
extern bus_space_handle_t awin_core_bsh;
|
||||
|
|
@ -63,6 +70,12 @@ extern struct arm32_bus_dma_tag awin_dma_tag;
|
|||
|
||||
psize_t awin_memprobe(void);
|
||||
void awin_bootstrap(vaddr_t, vaddr_t);
|
||||
void awin_pll6_enable(void);
|
||||
|
||||
void awin_gpio_init(void);
|
||||
bool awin_gpio_pinset_available(const struct awin_gpio_pinset *);
|
||||
void awin_gpio_pinset_acquire(const struct awin_gpio_pinset *);
|
||||
void awin_gpio_pinset_release(const struct awin_gpio_pinset *);
|
||||
|
||||
void awin_wdog_reset(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# $NetBSD: files.awin,v 1.3 2013/09/04 17:45:40 matt Exp $
|
||||
# $NetBSD: files.awin,v 1.4 2013/09/07 00:35:52 matt Exp $
|
||||
#
|
||||
# Configuration info for Allwinner ARM Peripherals
|
||||
#
|
||||
|
|
@ -54,10 +54,10 @@ file arch/arm/allwinner/awin_com.c awin_com
|
|||
# A10/A20 GPIO
|
||||
device awingpio : gpiobus
|
||||
attach awingpio at awinio with awin_gpio
|
||||
file arch/arm/allwinner/awin_gpio.c awin_gpio
|
||||
file arch/arm/allwinner/awin_gpio.c awin_gpio | awin_io needs-flag
|
||||
|
||||
# A10/A20 TWI (IIC)
|
||||
device awiniic : i2cbus, i2cexec
|
||||
device awiniic : i2cbus, i2cexec, mvi2c
|
||||
attach awiniic at awinio with awin_twi
|
||||
file arch/arm/allwinner/awin_twi.c awin_twi
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue