For OMAP3530/TIAM37XX and OMAP4430, read the PLL regisers and calculate the
real CPU clock rate.
This commit is contained in:
matt
parent
bbab09f832
commit
f7f3afd51f
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@ -1,4 +1,4 @@
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/* $NetBSD: beagle.h,v 1.6 2012/08/23 01:27:25 matt Exp $ */
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/* $NetBSD: beagle.h,v 1.7 2012/08/29 18:05:41 matt Exp $ */
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/*
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* Copyright (c) 2007 Microsoft
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* All rights reserved.
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@ -56,6 +56,8 @@
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#define OMAP_L4_PERIPHERAL_SIZE OMAP4430_L4_PERIPHERAL_SIZE
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#define OMAP_L4_WAKEUP_BASE OMAP4430_L4_WAKEUP_BASE
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#define OMAP_L4_WAKEUP_SIZE OMAP4430_L4_WAKEUP_SIZE
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#define OMAP_L4_ABE_BASE OMAP4430_L4_ABE_BASE
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#define OMAP_L4_ABE_SIZE OMAP4430_L4_ABE_SIZE
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#endif
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#ifdef TI_AM335X
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@ -80,12 +82,18 @@
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* We devmap IO starting at KERNEL_VM_BASE + KERNEL_VM_SIZE
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*/
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#define OMAP_KERNEL_IO_VBASE (KERNEL_VM_BASE + KERNEL_VM_SIZE)
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#if defined(OMAP_3530) || defined(OMAP_4430)
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#if defined(OMAP_3530)
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#define OMAP_L4_CORE_VBASE OMAP_KERNEL_IO_VBASE
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#define OMAP_L4_PERIPHERAL_VBASE (OMAP_L4_CORE_VBASE + OMAP_L4_CORE_SIZE)
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#define OMAP_L4_WAKEUP_VBASE (OMAP_L4_PERIPHERAL_VBASE + OMAP_L4_PERIPHERAL_SIZE)
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#define OMAP_KERNEL_IO_VEND (OMAP_L4_WAKEUP_VBASE + OMAP_L4_WAKEUP_SIZE)
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#define CONSADDR_VA ((CONSADDR - OMAP_L4_PERIPHERAL_BASE) + OMAP_L4_PERIPHERAL_VBASE)
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#elif defined(OMAP_4430)
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#define OMAP_L4_CORE_VBASE OMAP_KERNEL_IO_VBASE
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#define OMAP_L4_PERIPHERAL_VBASE (OMAP_L4_CORE_VBASE + OMAP_L4_CORE_SIZE)
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#define OMAP_L4_ABE_VBASE (OMAP_L4_PERIPHERAL_VBASE + OMAP_L4_PERIPHERAL_SIZE)
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#define OMAP_KERNEL_IO_VEND (OMAP_L4_ABE_VBASE + OMAP_L4_ABE_SIZE)
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#define CONSADDR_VA ((CONSADDR - OMAP_L4_PERIPHERAL_BASE) + OMAP_L4_PERIPHERAL_VBASE)
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#elif defined(TI_AM335X)
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#define OMAP_L4_CORE_VBASE OMAP_KERNEL_IO_VBASE
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#define OMAP_L4_PERIPHERAL_VBASE (OMAP_L4_CORE_VBASE + OMAP_L4_CORE_SIZE)
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@ -1,4 +1,4 @@
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/* $NetBSD: beagle_machdep.c,v 1.17 2012/08/22 22:18:22 matt Exp $ */
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/* $NetBSD: beagle_machdep.c,v 1.18 2012/08/29 18:05:41 matt Exp $ */
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/*
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* Machine dependent functions for kernel setup for TI OSK5912 board.
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@ -125,7 +125,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: beagle_machdep.c,v 1.17 2012/08/22 22:18:22 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: beagle_machdep.c,v 1.18 2012/08/29 18:05:41 matt Exp $");
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#include "opt_machdep.h"
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#include "opt_ddb.h"
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@ -137,15 +137,17 @@ __KERNEL_RCSID(0, "$NetBSD: beagle_machdep.c,v 1.17 2012/08/22 22:18:22 matt Exp
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#include "prcm.h"
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/device.h>
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#include <sys/exec.h>
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#include <sys/proc.h>
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#include <sys/kernel.h>
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#include <sys/ksyms.h>
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#include <sys/msgbuf.h>
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#include <sys/proc.h>
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#include <sys/reboot.h>
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#include <sys/termios.h>
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#include <sys/ksyms.h>
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#include <uvm/uvm_extern.h>
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@ -161,9 +163,6 @@ __KERNEL_RCSID(0, "$NetBSD: beagle_machdep.c,v 1.17 2012/08/22 22:18:22 matt Exp
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#endif
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#include <machine/bootconfig.h>
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#include <sys/bus.h>
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#include <machine/cpu.h>
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#include <machine/frame.h>
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#include <arm/armreg.h>
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#include <arm/undefined.h>
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@ -232,6 +231,12 @@ static void kgdb_port_init(void);
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static void setup_real_page_tables(void);
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static void init_clocks(void);
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#if defined(OMAP_3530) || defined(TI_DM37XX)
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static void omap3_cpu_clk(void);
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#endif
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#if defined(OMAP_4430)
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static void omap4_cpu_clk(void);
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#endif
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bs_protos(bs_notimpl);
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@ -366,9 +371,7 @@ static const struct pmap_devmap devmap[] = {
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.pd_prot = VM_PROT_READ|VM_PROT_WRITE,
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.pd_cache = PTE_NOCACHE
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},
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#if defined(OMAP_L4_WAKEUP_BASE) \
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&& (OMAP_L4_WAKEUP_BASE < OMAP_L4_CORE_BASE \
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|| OMAP_L4_CORE_BASE + OMAP_L4_CORE_SIZE <= OMAP_L4_WAKEUP_BASE)
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#if defined(OMAP_L4_WAKEUP_BASE) && defined(OMAP_L4_WAKEUP_VBASE)
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{
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/*
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* Map all 256KB of the L4 Wakeup area
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@ -393,6 +396,19 @@ static const struct pmap_devmap devmap[] = {
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.pd_prot = VM_PROT_READ|VM_PROT_WRITE,
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.pd_cache = PTE_NOCACHE
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},
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#endif
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#ifdef OMAP_L4_ABE_BASE
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{
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/*
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* Map all of the L4 Fast area
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* this gets us GPIO1, WDT2, GPT1, 32K and power/reset regs
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*/
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.pd_va = _A(OMAP_L4_ABE_VBASE),
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.pd_pa = _A(OMAP_L4_ABE_BASE),
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.pd_size = _S(OMAP_L4_ABE_SIZE),
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.pd_prot = VM_PROT_READ|VM_PROT_WRITE,
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.pd_cache = PTE_NOCACHE
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},
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#endif
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{0}
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};
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@ -458,7 +474,13 @@ initarm(void *arg)
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* peripherals and SDRAM. The temporary first level translation table
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* is at the end of SDRAM.
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*/
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#if defined(OMAP_3530) || defined(TI_DM37XX)
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omap3_cpu_clk(); // find our CPU speed.
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#endif
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#if defined(OMAP_4430)
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if (0)
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omap4_cpu_clk(); // find our CPU speed.
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#endif
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/* Heads up ... Setup the CPU / MMU / TLB functions. */
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if (set_cpufuncs())
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panic("cpu not recognized!");
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@ -977,3 +999,47 @@ printf("\t%#lx:%#lx\n", kernel_pt_table[pt_index].pv_va, kernel_pt_table[pt_inde
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printf("OK.\n");
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#endif
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}
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#if defined(OMAP_3530) || defined(TI_DM37XX)
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void
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omap3_cpu_clk(void)
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{
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const vaddr_t prm_base = OMAP2_PRM_BASE - OMAP_L4_CORE_BASE + OMAP_L4_CORE_VBASE;
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const uint32_t prm_clksel = *(volatile uint32_t *)(prm_base + PLL_MOD + OMAP3_PRM_CLKSEL);
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static const uint32_t prm_clksel_freqs[] = OMAP3_PRM_CLKSEL_FREQS;
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const uint32_t sys_clk = prm_clksel_freqs[__SHIFTOUT(prm_clksel, OMAP3_PRM_CLKSEL_CLKIN)];
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const vaddr_t cm_base = OMAP2_CM_BASE - OMAP_L4_CORE_BASE + OMAP_L4_CORE_VBASE;
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const uint32_t dpll1 = *(volatile uint32_t *)(cm_base + OMAP3_CM_CLKSEL1_PLL_MPU);
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const uint32_t dpll2 = *(volatile uint32_t *)(cm_base + OMAP3_CM_CLKSEL2_PLL_MPU);
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const uint32_t m = __SHIFTOUT(dpll1, OMAP3_CM_CLKSEL1_PLL_MPU_DPLL_MULT);
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const uint32_t n = __SHIFTOUT(dpll1, OMAP3_CM_CLKSEL1_PLL_MPU_DPLL_DIV);
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const uint32_t m2 = __SHIFTOUT(dpll2, OMAP3_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV);
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/*
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* MPU_CLK supplies ARM_FCLK which is twice the CPU frequency.
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*/
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curcpu()->ci_data.cpu_cc_freq = ((sys_clk * m) / ((n + 1) * m2 * 2)) * OMAP3_PRM_CLKSEL_MULT;
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}
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#endif /* OMAP_3530 || TI_DM37XX */
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#if defined(OMAP_4430)
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void
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omap4_cpu_clk(void)
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{
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const vaddr_t prm_base = OMAP2_PRM_BASE - OMAP_L4_CORE_BASE + OMAP_L4_CORE_VBASE;
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const vaddr_t cm_base = OMAP2_CM_BASE - OMAP_L4_CORE_BASE + OMAP_L4_CORE_VBASE;
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static const uint32_t cm_clksel_freqs[] = OMAP4_CM_CLKSEL_FREQS;
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const uint32_t prm_clksel = *(volatile uint32_t *)(prm_base + OMAP4_CM_SYS_CLKSEL);
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const uint32_t sys_clk = cm_clksel_freqs[__SHIFTOUT(prm_clksel, OMAP4_CM_SYS_CLKSEL_CLKIN)];
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const uint32_t dpll1 = *(volatile uint32_t *)(cm_base + OMAP4_CM_CLKSEL_DPLL_MPU);
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const uint32_t dpll2 = *(volatile uint32_t *)(cm_base + OMAP4_CM_DIV_M2_DPLL_MPU);
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const uint32_t m = __SHIFTOUT(dpll1, OMAP4_CM_CLKSEL_DPLL_MPU_DPLL_MULT);
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const uint32_t n = __SHIFTOUT(dpll1, OMAP4_CM_CLKSEL_DPLL_MPU_DPLL_DIV);
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const uint32_t m2 = __SHIFTOUT(dpll2, OMAP4_CM_DIV_M2_DPLL_MPU_DPLL_CLKOUT_DIV);
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/*
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* MPU_CLK supplies ARM_FCLK which is twice the CPU frequency.
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*/
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curcpu()->ci_data.cpu_cc_freq = ((sys_clk * 2 * m) / ((n + 1) * m2)) * OMAP4_CM_CLKSEL_MULT;
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}
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#endif /* OMAP_4400 */
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