* finalize 060 stuff.
For locore.s also nuke cacheop-functions now provided in m68k.
This commit is contained in:
leo
parent
327cf04b4b
commit
f796b57669
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@ -1,4 +1,4 @@
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/* $NetBSD: atari_init.c,v 1.29 1997/04/09 19:37:53 thorpej Exp $ */
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/* $NetBSD: atari_init.c,v 1.30 1997/06/05 19:45:29 leo Exp $ */
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/*
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* Copyright (c) 1995 Leo Weppelman
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@ -52,6 +52,7 @@
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#include <sys/core.h>
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#include <sys/kcore.h>
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#include <vm/pmap.h>
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#include <machine/vmparam.h>
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#include <machine/pte.h>
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#include <machine/cpu.h>
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@ -60,6 +61,10 @@
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#include <machine/scu.h>
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#include <machine/acia.h>
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#include <machine/kcore.h>
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#include <m68k/cpu.h>
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#include <m68k/cacheops.h>
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#include <atari/atari/intr.h>
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#include <atari/atari/stalloc.h>
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#include <atari/dev/ym2149reg.h>
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@ -67,6 +72,7 @@
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void start_c __P((int, u_int, u_int, u_int, char *));
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static void atari_hwinit __P((void));
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static void cpu_init_kcorehdr __P((u_long));
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static void initcpu __P((void));
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static void mmu030_setup __P((st_entry_t *, u_int, pt_entry_t *, u_int,
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pt_entry_t *, u_int, u_int));
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static void map_io_areas __P((pt_entry_t *, u_int, u_int));
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@ -137,7 +143,6 @@ u_long st_pool_virt, st_pool_phys;
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* Some of the code in here is `stolen' from Amiga MACH, and was
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* written by Bryan Ford and Niklas Hallqvist.
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*
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* Very crude 68040 support by Michael L. Hitch.
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*/
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void
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@ -209,6 +214,11 @@ char *esym_addr; /* Address of kernel '_esym' symbol */
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*/
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set_machtype();
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/*
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* Initialize cpu specific stuff
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*/
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initcpu();
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/*
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* We run the kernel from ST memory at the moment.
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* The kernel segment table is put just behind the loaded image.
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@ -889,6 +899,57 @@ mmu040_setup(sysseg, kstsize, pt, ptsize, sysptmap, sysptsize, kbase)
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}
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#endif /* M68040 */
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#if defined(M68060)
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int m68060_pcr_init = 0x21; /* make this patchable */
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#endif
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static void
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initcpu()
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{
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/* XXX should init '40 vecs here, too */
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#if defined(M68060)
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extern caddr_t vectab[256];
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#if defined(M060SP)
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extern u_int8_t FP_CALL_TOP[], I_CALL_TOP[];
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#else
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extern u_int8_t illinst;
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#endif
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extern u_int8_t fpfault;
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if (cputype == CPU_68060) {
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asm volatile ("movl %0,d0; .word 0x4e7b,0x0808" : :
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"d"(m68060_pcr_init):"d0" );
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#if defined(M060SP)
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/* integer support */
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vectab[61] = &I_CALL_TOP[128 + 0x00];
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/* floating point support */
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/*
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* XXX maybe we really should run-time check for the
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* stack frame format here:
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*/
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vectab[11] = &FP_CALL_TOP[128 + 0x30];
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vectab[55] = &FP_CALL_TOP[128 + 0x38];
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vectab[60] = &FP_CALL_TOP[128 + 0x40];
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vectab[54] = &FP_CALL_TOP[128 + 0x00];
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vectab[52] = &FP_CALL_TOP[128 + 0x08];
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vectab[53] = &FP_CALL_TOP[128 + 0x10];
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vectab[51] = &FP_CALL_TOP[128 + 0x18];
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vectab[50] = &FP_CALL_TOP[128 + 0x20];
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vectab[49] = &FP_CALL_TOP[128 + 0x28];
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#else
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vectab[61] = &illinst;
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#endif
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vectab[48] = &fpfault;
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}
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DCIS();
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#endif
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}
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#ifdef DEBUG
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void
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dump_segtable(stp)
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.40 1997/06/02 12:03:41 leo Exp $ */
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/* $NetBSD: locore.s,v 1.41 1997/06/05 19:45:32 leo Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -760,65 +760,75 @@ Lstart0:
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*/
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jmp Lstart2
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Lstart2:
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movl a0@+,a5@+ | copy the rest of the kernel
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movl a0@+,a5@+ | copy the rest of the kernel
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subl #4, d4
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jcc Lstart2
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Lstart3:
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lea tmpstk,sp | give ourselves a temporary stack
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lea tmpstk,sp | give ourselves a temporary stack
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/*
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* save the passed parameters. `prepass' them on the stack for
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* later catch by _start_c
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*/
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movl a1,sp@- | pass address of _esym
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movl d1,sp@- | pass stmem-size
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movl d0,sp@- | pass fastmem-size
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movl d5,sp@- | pass fastmem_start
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movl d2,sp@- | pass machine id
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movl d3,_boothowto | save reboot flags
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movl #ATARI_68030,d1 | 68030 type from loader
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movl a1,sp@- | pass address of _esym
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movl d1,sp@- | pass stmem-size
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movl d0,sp@- | pass fastmem-size
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movl d5,sp@- | pass fastmem_start
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movl d2,sp@- | pass machine id
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movl d3,_boothowto | save reboot flags
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/*
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* Set cputype and mmutype dependent on the machine-id passed
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* in from the loader. Also make sure that all caches are cleared.
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*/
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movl #ATARI_68030,d1 | 68030 type from loader
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andl d2,d1
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jeq Ltestfor020 | Not an 68030, try 68020
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movl #MMU_68030,_mmutype | Use 68030 MMU
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movl #CPU_68030,_cputype | and a 68030 CPU
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jra Ltestfor040 | skip to init.
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jeq Ltestfor020 | Not an 68030, try 68020
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movl #MMU_68030,_mmutype | Use 68030 MMU
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movl #CPU_68030,_cputype | and a 68030 CPU
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movl #CACHE_OFF,d0 | 68020/030 cache clear
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jra Lend_cpuset | skip to init.
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Ltestfor020:
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movl #ATARI_68020,d1 | 68020 type from loader
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movl #ATARI_68020,d1 | 68020 type from loader
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andl d2,d1
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jeq Ltestfor040
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movl #MMU_68851,_mmutype | Assume 68851 with 68020
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movl #CPU_68020,_cputype | and a 68020 CPU
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movl #MMU_68851,_mmutype | Assume 68851 with 68020
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movl #CPU_68020,_cputype | and a 68020 CPU
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movl #CACHE_OFF,d0 | 68020/030 cache clear
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jra Lend_cpuset | skip to init.
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Ltestfor040:
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movl #CACHE_OFF,d0 | 68020/030 cache
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movl #CACHE_OFF,d0 | 68020/030 cache
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movl #ATARI_68040,d1
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andl d1,d2
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andl d2,d1
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jeq Ltestfor060
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movl #MMU_68040,_mmutype | Use a 68040 MMU
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movl #CPU_68040,_cputype | and a 68040 CPU
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.word 0xf4f8 | cpusha bc - push and inval caches
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movl #CACHE40_OFF,d0 | 68040 cache disable
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jra Lstartnot060
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movl #MMU_68040,_mmutype | Use a 68040 MMU
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movl #CPU_68040,_cputype | and a 68040 CPU
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.word 0xf4f8 | cpusha bc - push and inval caches
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movl #CACHE40_OFF,d0 | 68040 cache disable
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jra Lend_cpuset | skip to init.
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Ltestfor060:
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movl #ATARI_68060,d1
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andl d1,d2
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jeq Lstartnot060
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andl d2,d1
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jeq Lend_cpuset
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movl #MMU_68040,_mmutype | Use a 68040 MMU
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movl #CPU_68060,_cputype | and a 68060 CPU
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.word 0xf4f8 | cpusha bc - push and inval caches
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movl #CACHE40_OFF,d0 | 68040 cache disable
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orl #IC60_CABC,d0 | and clear all 060 branch cache
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Lstartnot060:
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Lend_cpuset:
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movc d0,cacr | clear and disable on-chip cache(s)
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movl #Lvectab,a0 | set address of vector table
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movl #_vectab,a0 | set address of vector table
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movc a0,vbr
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/*
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* Initialize source/destination control registers for movs
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*/
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moveq #FC_USERD,d0 | user space
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movc d0,sfc | as source
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movc d0,dfc | and destination of transfers
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moveq #FC_USERD,d0 | user space
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movc d0,sfc | as source
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movc d0,dfc | and destination of transfers
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/*
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* let the C function initialize everything and enable the MMU
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@ -1464,162 +1474,6 @@ Ltbisnot060:
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rts
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/*
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* Invalidate supervisor side of TLB
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*/
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ENTRY(TBIAS)
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#ifdef DEBUG
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tstl fulltflush | being conservative?
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jne __TBIA | yes, flush everything
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#endif
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cmpl #MMU_68040,_mmutype
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jeq Ltbias040
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tstl _mmutype
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jpl Lmc68851c | 68851?
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pflush #4,#4 | flush supervisor TLB entries
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip d-cache
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rts
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Lmc68851c:
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pflushs #4,#4 | flush supervisor TLB entries
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rts
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Ltbias040:
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/* 68040 can't specify supervisor/user on pflusha, so we flush all */
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.word 0xf518 | pflusha
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rts
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/*
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* Invalidate user side of TLB
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*/
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ENTRY(TBIAU)
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#ifdef DEBUG
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tstl fulltflush | being conservative?
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jne __TBIA | yes, flush everything
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#endif
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cmpl #MMU_68040,_mmutype
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jeq Ltbiau040
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tstl _mmutype
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jpl Lmc68851d | 68851?
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pflush #0,#4 | flush user TLB entries
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip d-cache
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rts
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Lmc68851d:
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pflushs #0,#4 | flush user TLB entries
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rts
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Ltbiau040:
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/* 68040 can't specify supervisor/user on pflusha, so we flush all */
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.word 0xf518 | pflusha
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rts
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/*
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* Invalidate instruction cache
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*/
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ENTRY(ICIA)
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ENTRY(ICPA)
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#if defined(M68030) || defined(M68020)
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#if defined(M68040) || defined(M68060)
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cmpl #MMU_68040,_mmutype
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jeq Licia040
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#endif
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movl #IC_CLEAR,d0
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movc d0,cacr | invalidate i-cache
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rts
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Licia040:
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#endif
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#if defined(M68040)
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.word 0xf498 | cinva ic
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rts
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#endif
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/*
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* Invalidate data cache.
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* NOTE: we do not flush 68030 on-chip cache as there are no aliasing
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* problems with DC_WA. The only cases we have to worry about are context
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* switch and TLB changes, both of which are handled "in-line" in resume
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* and TBI*.
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*/
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ENTRY(DCIA)
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__DCIA:
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cmpl #MMU_68040,_mmutype
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jne Ldciax
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.word 0xf478 | cpusha dc
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Ldciax:
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rts
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ENTRY(DCIS)
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__DCIS:
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cmpl #MMU_68040,_mmutype
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jne Ldcisx
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.word 0xf478 | cpusha dc
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nop
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Ldcisx:
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rts
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ENTRY(DCIU)
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__DCIU:
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cmpl #MMU_68040,_mmutype
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jne Ldciux
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.word 0xf478 | cpusha dc
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Ldciux:
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rts
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/* Invalid single cache line */
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ENTRY(DCIAS)
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__DCIAS:
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cmpl #MMU_68040,_mmutype
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jne Ldciasx
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movl sp@(4),a0
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.word 0xf468 | cpushl dc,a0@
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Ldciasx:
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rts
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#ifdef M68040
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ENTRY(ICPL) /* invalidate instruction physical cache line */
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movl sp@(4),a0 | address
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.word 0xf488 | cinvl ic,a0@
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rts
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ENTRY(ICPP) /* invalidate instruction physical cache page */
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movl sp@(4),a0 | address
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.word 0xf490 | cinvp ic,a0@
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rts
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ENTRY(DCPL) /* invalidate data physical cache line */
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movl sp@(4),a0 | address
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.word 0xf448 | cinvl dc,a0@
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rts
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ENTRY(DCPP) /* invalidate data physical cache page */
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movl sp@(4),a0 | address
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.word 0xf450 | cinvp dc,a0@
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rts
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ENTRY(DCPA) /* invalidate data physical all */
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.word 0xf458 | cinva dc
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rts
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ENTRY(DCFL) /* data cache flush line */
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movl sp@(4),a0 | address
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.word 0xf468 | cpushl dc,a0@
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rts
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ENTRY(DCFP) /* data cache flush page */
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movl sp@(4),a0 | address
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.word 0xf470 | cpushp dc,a0@
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rts
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#endif /* M68040 */
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ENTRY(PCIA)
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#if defined(M68030) || defined(M68030)
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#if defined(M68040) || defined(M68060)
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cmpl #MMU_68040,_mmutype
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jeq Lpcia040
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#endif
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movl #DC_CLEAR,d0
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movc d0,cacr | invalidate on-chip d-cache
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rts
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#endif
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#if defined(M68040)
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ENTRY(DCFA)
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Lpcia040:
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.word 0xf478 | cpusha dc
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rts
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#endif
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ENTRY(ecacheon)
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rts
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