Use %r<n> for register names.
This commit is contained in:
eeh
parent
9cf81bef79
commit
f77f1feee5
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@ -1,4 +1,4 @@
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/* $NetBSD: walnut_start.S,v 1.7 2003/04/27 10:42:50 ragge Exp $ */
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/* $NetBSD: walnut_start.S,v 1.8 2003/08/03 23:26:55 eeh Exp $ */
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/* $OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $ */
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/*
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@ -68,6 +68,7 @@
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*/
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#undef PPC_4XX_NOCACHE
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#define _NOREGNAMES
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#include "opt_ddb.h"
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#include "opt_ipkdb.h"
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@ -147,17 +148,17 @@ __start:
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nop
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1:
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mr 31,3 /* Save address of PROM info_block */
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li 0,0
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mtmsr 0 /* Disable FPU/MMU/exceptions */
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mr %r31,%r3 /* Save address of PROM info_block */
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li %r0,0
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mtmsr %r0 /* Disable FPU/MMU/exceptions */
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isync
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/* PPC405GP errata, item #58.
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* Load string instructions may write incorrect data into the last GPR
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* targeted in the operation.
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* Workaround: set OCM0_DSCNTL[DSEN]=0 and OCM0_DSCNTL[DOF]=0 */
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mtdcr DCR_OCM0_DSCNTL, 0 /* Disable Data access to OCM */
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mtdcr DCR_OCM0_ISCNTL, 0 /* Disable Instruction access to OCM. Just in case */
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mtdcr DCR_OCM0_DSCNTL, %r0 /* Disable Data access to OCM */
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mtdcr DCR_OCM0_ISCNTL, %r0 /* Disable Instruction access to OCM. Just in case */
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/*
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* Cpu detect.
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*
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@ -165,38 +166,38 @@ __start:
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__start_cpu0:
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#ifdef PPC_4XX_NOCACHE
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/* Disable all caches for physical addresses */
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li 0,0
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li %r0,0
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#else
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/* Allow cacheing for only the first 2GB of RAM */
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lis 0,0xffff
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lis %r0,0xffff
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#endif
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mtdccr 0
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mticcr 0
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mtdccr %r0
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mticcr %r0
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/* Invalidate all TLB entries */
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tlbia
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sync
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isync
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/* get start of bss */
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lis 3,_C_LABEL(_edata)-4@ha
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addi 3,3,_C_LABEL(_edata)-4@l
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lis %r3,_C_LABEL(_edata)-4@ha
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addi %r3,%r3,_C_LABEL(_edata)-4@l
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/* get end of kernel memory */
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lis 8,_C_LABEL(end)@ha
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addi 8,8,_C_LABEL(end)@l
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lis %r8,_C_LABEL(end)@ha
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addi %r8,%r8,_C_LABEL(end)@l
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/* zero bss */
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li 4,0
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2: stwu 4,4(3)
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cmpw 3,8
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li %r4,0
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2: stwu %r4,%r4(3)
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cmpw %r3,%r8
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bne+ 2b
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#if NKSYMS || defined(DDB) || defined(LKM)
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/* If we had symbol table location we'd store it here and would've adjusted r8 here */
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lis 7,_C_LABEL(startsym)@ha
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addi 7,7,_C_LABEL(startsym)@l
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stw 8,0(7)
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lis 7,_C_LABEL(endsym)@ha
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addi 7,7,_C_LABEL(endsym)@l
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stw 8,0(7)
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lis %r7,_C_LABEL(startsym)@ha
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addi %r7,%r7,_C_LABEL(startsym)@l
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stw %r8,0(%r7)
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lis %r7,_C_LABEL(endsym)@ha
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addi %r7,%r7,_C_LABEL(endsym)@l
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stw %r8,0(%r7)
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#endif
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/*
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@ -205,60 +206,60 @@ __start_cpu0:
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* XXX: Skip TLB 0 for now, due to unresolved TLB 0 replacement
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* and hard hangs
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*/
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li 0,1
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mtpid 0
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li %r0,1
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mtpid %r0
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sync
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li 0,0
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li %r0,0
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#ifdef PPC_4XX_NOCACHE
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li 4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
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li %r4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
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#else
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li 4,TLB_EX|TLB_WR /* |TLB_W */
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li %r4,TLB_EX|TLB_WR /* |TLB_W */
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#endif
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li 3,TLB_VALID|TLB_PG_16M
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tlbwe 4,0,1 /* Load the data(Low) portion of the entry */
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tlbwe 3,0,0 /* Load the tag(High) portion of the entry */
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li %r3,TLB_VALID|TLB_PG_16M
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tlbwe %r4,%r0,1 /* Load the data(Low) portion of the entry */
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tlbwe %r3,%r0,0 /* Load the tag(High) portion of the entry */
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#if 1
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/* Damn. Have to be able to access all real memory.... Hardcode for 32M for now. */
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li 0,1
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lis 4,0x01000000@h
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ori 3,4,0
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li %r0,1
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lis %r4,0x01000000@h
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ori %r3,%r4,0
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#ifdef PPC_4XX_NOCACHE
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addi 4,4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
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addi %r4,%r4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
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#else
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addi 4,4,TLB_EX|TLB_WR /* |TLB_W */
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addi %r4,%r4,TLB_EX|TLB_WR /* |TLB_W */
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#endif
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addi 3,3,TLB_VALID|TLB_PG_16M
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tlbwe 4,0,1 /* Load the data(Low) portion of the entry */
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tlbwe 3,0,0 /* Load the tag(High) portion of the entry */
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addi %r3,%r3,TLB_VALID|TLB_PG_16M
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tlbwe %r4,%r0,1 /* Load the data(Low) portion of the entry */
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tlbwe %r3,%r0,0 /* Load the tag(High) portion of the entry */
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#endif
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/* set up a TLB mapping to cover uart0 */
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lis 3,0xef000000@h /* Load the virtual address */
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ori 4,3,0 /* Load the physical address */
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lis %r3,0xef000000@h /* Load the virtual address */
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ori %r4,%r3,0 /* Load the physical address */
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clrrwi 4,4,10 /* Mask off the real page number */
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clrrwi %r4,%r4,10 /* Mask off the real page number */
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/* write, execute, cache inhibit, guarded */
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ori 4,4,(TLB_WR|TLB_EX|TLB_I|TLB_G)
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ori %r4,%r4,(TLB_WR|TLB_EX|TLB_I|TLB_G)
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clrrwi 3,3,10 /* Mask off the effective page number */
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ori 3,3,(TLB_VALID|TLB_PG_16M)
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clrrwi %r3,%r3,10 /* Mask off the effective page number */
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ori %r3,%r3,(TLB_VALID|TLB_PG_16M)
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li 0,2
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li %r0,2
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tlbwe 4,0,1 /* Load the data portion of the entry */
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tlbwe 3,0,0 /* Load the tag portion of the entry */
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tlbwe %r4,%r0,1 /* Load the data portion of the entry */
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tlbwe %r3,%r0,0 /* Load the tag portion of the entry */
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/* END of TLB setup */
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INIT_CPUINFO(8,1,9,0)
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mr 4,8
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mr %r4,%r8
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lis 3,__start@ha
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addi 3,3,__start@l
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lis %r3,__start@ha
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addi %r3,%r3,__start@l
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mr 6,31 /* info_block address */
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mr %r6,%r31 /* info_block address */
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bl _C_LABEL(initppc)
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bl _C_LABEL(main)
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@ -1,4 +1,4 @@
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/* $NetBSD: 4xx_locore.S,v 1.3 2003/07/25 10:12:42 scw Exp $ */
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/* $NetBSD: 4xx_locore.S,v 1.4 2003/08/03 23:26:55 eeh Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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@ -89,9 +89,9 @@
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.globl _C_LABEL(ppc4xx_reset)
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_C_LABEL(ppc4xx_reset):
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mfspr 3,SPR_DBCR0
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oris 3,r13,DBCR0_RST_SYSTEM@h
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mtspr SPR_DBCR0,3
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mfspr %r3,SPR_DBCR0
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oris %r3,%r13,DBCR0_RST_SYSTEM@h
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mtspr SPR_DBCR0,%r3
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ba 0
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#if 0
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@ -101,17 +101,17 @@ _C_LABEL(ppc4xx_reset):
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/*
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* void bcopy(const void *src, void *dst, size_t len);
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*
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* swap r3 and r4 and fall through to memcopy.
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* swap %r3 and %r4 and fall through to memcopy.
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*/
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.globl _C_LABEL(bcopy)
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_C_LABEL(bcopy):
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mr r0,r3
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mr r3,r4
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mr r4,r0
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mr %r0,%r3
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mr %r3,%r4
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mr %r4,%r0
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/* FALLTHROUGH */
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/*
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* void * memcpy(void *dst (r3), const void *src (r4), size_t len (r5));
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* void * memcpy(void *dst (%r3), const void *src (%r4), size_t len (%r5));
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*
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* Copy memory (obviously)
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*
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@ -121,71 +121,71 @@ _C_LABEL(bcopy):
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*
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* Register use:
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*
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* r1 stack (of course)
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* r3 dst
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* r4 src
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* r5 len
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* r6 tmp
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* r7 holds 32
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* r8 holds dst
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* r24-r31 block move regs
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* %r1 stack (of course)
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* %r3 dst
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* %r4 src
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* %r5 len
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* %r6 tmp
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* %r7 holds 32
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* %r8 holds dst
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* %r24-%r31 block move regs
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*
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*/
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ENTRY(memcpy)
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stwu r1,-(10*4)(r1) /* Allocate some RAM to save 8 regs to. */
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cmpwi r5, 32 /* Less than 32 bytes ? */
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stmw r24,8(r1) /* Save ALL regs (could be optimized) */
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stwu %r1,-(10*4)(%r1) /* Allocate some RAM to save 8 regs to. */
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cmpwi %r5, 32 /* Less than 32 bytes ? */
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stmw %r24,8(%r1) /* Save ALL regs (could be optimized) */
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mr r8,r3 /* save dst */
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li r7,32
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mr %r8,%r3 /* save dst */
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li %r7,32
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dcbt 0,r4 /* Start bringing in cache line. */
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dcbt %r0,%r4 /* Start bringing in cache line. */
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blt 1f /* Finish up */
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neg r6,r3 /* Find how far unaligned we are... */
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andi. r6,r6,31 /* Cache-align dest. */
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mtxer r6
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sub r5,r5,r6 /* subtract count */
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lswx r24,0,r4 /* Load some. */
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add r4,r4,r6
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dcbt 0,r4 /* Fetch next line */
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stswx r24,0,r3 /* Store some */
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add r3,r3,r6
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addic. r6,r5,-32 /* Pre-decrement next line */
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neg %r6,%r3 /* Find how far unaligned we are... */
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andi. %r6,%r6,31 /* Cache-align dest. */
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mtxer %r6
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sub %r5,%r5,%r6 /* subtract count */
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lswx %r24,%r0,%r4 /* Load some. */
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add %r4,%r4,%r6
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dcbt %r0,%r4 /* Fetch next line */
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stswx %r24,%r0,%r3 /* Store some */
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add %r3,%r3,%r6
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addic. %r6,%r5,-32 /* Pre-decrement next line */
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ble 1f /* Less than 32-bytes? finishup */
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/* Dest should not be cache line aligned. */
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/* XXX need gas 2.11 to grok dcba insn */
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#ifdef GAS_2_11
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dcba 0,r3 /* Allocate a line */
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dcba %r0,%r3 /* Allocate a line */
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#else
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.long 0x7c001dec /* dcba 0,r3 */
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#endif
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0:
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dcbt r7,r4 /* Bring in the next line, too */
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dcbt %r7,%r4 /* Bring in the next line, too */
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lswi r24,r4,32
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addi r4,r4,32 /* Inc src */
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mr r5,r6
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lswi %r24,%r4,32
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addi %r4,%r4,32 /* Inc src */
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mr %r5,%r6
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addic. r6,r5,-32
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stswi r24,r3,32
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addi r3,r3,32 /* Inc dst */
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addic. %r6,%r5,-32
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stswi %r24,%r3,32
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addi %r3,%r3,32 /* Inc dst */
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#ifdef GAS_2_11
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dcba 0,r3 /* Allocate another line */
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dcba 0,%r3 /* Allocate another line */
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#else
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.long 0x7c071dec /* dcba r7,r3 */
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.long 0x7c071dec /* dcba %r7,%r3 */
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#endif
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bgt 0b
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1:
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mtxer r5 /* Store byte count */
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lswx r24,0,r4 /* Load up to 32 bytes */
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stswx r24,0,r3 /* Store up to 32 bytes */
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mtxer %r5 /* Store byte count */
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lswx %r24,%r0,%r4 /* Load up to 32 bytes */
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stswx %r24,%r0,%r3 /* Store up to 32 bytes */
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mr r3,r8 /* Return dst */
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mr %r3,%r8 /* Return dst */
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lmw r24,8(r1)
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addi r1,r1,(10*4)
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lmw %r24,8(%r1)
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addi %r1,%r1,(10*4)
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blr
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: 4xx_trap_subr.S,v 1.3 2003/03/11 10:40:16 hannken Exp $ */
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/* $NetBSD: 4xx_trap_subr.S,v 1.4 2003/08/03 23:26:55 eeh Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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@ -79,18 +79,18 @@ _C_LABEL(errata51size) = .-_C_LABEL(errata51handler)
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.globl _C_LABEL(tlbdmiss4xx),_C_LABEL(tlbdm4size)
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_C_LABEL(tlbdmiss4xx):
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STANDARD_PROLOG(tlbsave)
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mfdear r30 /* Get fault address */
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mfesr r31
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stmw r30,16+tlbsave(0)
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mfdear %r30 /* Get fault address */
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mfesr %r31
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stmw %r30,16+tlbsave(0)
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bla s4xx_miss
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_C_LABEL(tlbdm4size) = .-_C_LABEL(tlbdmiss4xx)
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.globl _C_LABEL(tlbimiss4xx),_C_LABEL(tlbim4size)
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_C_LABEL(tlbimiss4xx):
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STANDARD_PROLOG(tlbsave)
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mfsrr0 r30 /* XXX Get fault address */
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mfesr r31
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stmw r30,16+tlbsave(0)
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mfsrr0 %r30 /* XXX Get fault address */
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mfesr %r31
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stmw %r30,16+tlbsave(0)
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bla s4xx_miss
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_C_LABEL(tlbim4size) = .-_C_LABEL(tlbimiss4xx)
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@ -98,12 +98,12 @@ s4xx_miss:
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.globl _C_LABEL(pmap_tlbmiss)
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/* If the kernel stack would fault, don't use it. */
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mfpid r30
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li r31,KERNEL_PID
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mtpid r31
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li r31,-FRAMELEN
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tlbsx. r31,r31,r1
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mtpid r30
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mfpid %r30
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li %r31,KERNEL_PID
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mtpid %r31
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li %r31,-FRAMELEN
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tlbsx. %r31,%r31,%r1
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mtpid %r30
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beq 1f
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/*
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@ -117,22 +117,22 @@ s4xx_miss:
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*/
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/* Switch to tlbstack */
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addi r30,r1,-FRAMELEN
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lis r1,tlbstack@ha
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addi r1,r1,tlbstack@l
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stw r30,4(1)
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addi %r30,%r1,-FRAMELEN
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lis %r1,tlbstack@ha
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addi %r1,%r1,tlbstack@l
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stw %r30,4(1)
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FRAME_SETUP(tlbsave)
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/* Take an explicit fault at (kernelstack,pid) */
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lwz r3, tlbstack+4(0)
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li r4,KERNEL_PID
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lwz %r3, tlbstack+4(0)
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li %r4,KERNEL_PID
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bl _C_LABEL(pmap_tlbmiss)
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/*
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* We can retry the old fault or switch stacks and
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* take it now. It's easier to retry.
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*/
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mr. r3,r3
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mr. %r3,%r3
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beq 2f
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/* kernel stack not in the pmap? we should panic */
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@ -140,15 +140,15 @@ s4xx_miss:
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ba trapagain
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1:
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FRAME_SETUP(tlbsave)
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lwz r3,FRAME_DEAR+8(1)
|
||||
lwz r4,FRAME_PID+8(1)
|
||||
lwz %r3,FRAME_DEAR+8(1)
|
||||
lwz %r4,FRAME_PID+8(1)
|
||||
bl _C_LABEL(pmap_tlbmiss)
|
||||
mr. r3,r3
|
||||
mr. %r3,%r3
|
||||
beq 2f
|
||||
|
||||
/* XXX DEBUG -- make sure we're not on tlbstack */
|
||||
addi r7,r1,-tlbsave
|
||||
twllei r7,(tlbstacksize)
|
||||
addi %r7,%r1,-tlbsave
|
||||
twllei %r7,(tlbstacksize)
|
||||
|
||||
/* PTE not found, time to cause a fault */
|
||||
ba trapagain
|
||||
|
|
|
|||
Loading…
Reference in New Issue