augustss
parent
c6ef57702d
commit
f76fb48283
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@ -1,4 +1,4 @@
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/* $NetBSD: ess.c,v 1.5 1998/07/31 23:54:09 augustss Exp $ */
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/* $NetBSD: ess.c,v 1.6 1998/08/04 13:14:42 augustss Exp $ */
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/*
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* Copyright 1997
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@ -71,9 +71,7 @@
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/*
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* TODO (falling priority):
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* - add looping DMA (copy from sbdsp.c).
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* - avoid using wired in IRQ/DRQ levels.
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* - look over how the two channels are set up, it's rather messy now.
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* - add looping DMA for input.
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*/
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#include <sys/param.h>
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@ -86,7 +84,7 @@
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <machine/pio.h>
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#include <machine/bus.h>
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#include <sys/audioio.h>
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#include <dev/audio_if.h>
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@ -138,6 +136,7 @@ int ess_set_out_channels __P((void *, int));
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int ess_round_blocksize __P((void *, int));
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int ess_dma_init_output __P((void *, void *, int));
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int ess_dma_output __P((void *, void *, int, void (*)(void *), void *));
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int ess_dma_input __P((void *, void *, int, void (*)(void *), void *));
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int ess_halt_output __P((void *));
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@ -210,12 +209,12 @@ struct audio_device ess_device = {
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struct audio_hw_if ess_hw_if = {
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ess_open,
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ess_close,
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NULL,
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ess_drain,
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ess_query_encoding,
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ess_set_params,
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ess_round_blocksize,
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NULL,
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NULL,
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ess_dma_init_output,
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NULL,
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ess_dma_output,
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ess_dma_input,
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@ -543,7 +542,7 @@ ess_setup(sc)
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{
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ess_config_irq(sc);
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ess_config_drq(sc);
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if (sc->sc_out.drq >= 4)
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if (IS16BITDRQ(sc->sc_out.drq))
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ess_set_mreg_bits(sc, ESS_MREG_AUDIO2_CTRL1,
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ESS_AUDIO2_CTRL1_XFER_SIZE);
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else
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@ -921,7 +920,7 @@ ess_open(addr, flags)
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if (sc->sc_open != 0 || ess_reset(sc) != 0)
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return ENXIO;
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ess_setup(sc);
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ess_setup(sc); /* because we did a reset */
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sc->sc_open = 1;
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@ -941,14 +940,28 @@ ess_close(addr)
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sc->sc_open = 0;
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ess_speaker_off(sc);
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sc->spkr_state = SPKR_OFF;
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sc->sc_in.intr = 0;
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sc->sc_out.intr = 0;
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ess_halt_output(sc);
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ess_halt_input(sc);
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sc->sc_in.intr = 0;
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sc->sc_out.intr = 0;
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DPRINTF(("ess_close: closed\n"));
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}
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/*
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* Wait for FIFO to drain, and analog section to settle.
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* XXX should check FIFO full bit.
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*/
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int
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ess_drain(addr)
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void *addr;
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{
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extern int hz; /* XXX */
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tsleep(addr, PWAIT | PCATCH, "essdr", hz/100); /* XXX */
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return (0);
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}
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int
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ess_speaker_ctl(addr, newstate)
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void *addr;
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@ -1278,6 +1291,21 @@ ess_set_out_channels(addr, channels)
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return (0);
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}
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int
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ess_dma_init_output(addr, buf, cc)
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void *addr;
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void *buf;
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int cc;
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{
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struct ess_softc *sc = addr;
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DPRINTF(("ess_dma_init_output: buf=%p cc=%d chan=%d\n",
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buf, cc, sc->sc_out.drq));
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isa_dmastart(sc->sc_ic, sc->sc_out.drq, buf,
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cc, NULL, DMAMODE_WRITE | DMAMODE_LOOP, BUS_DMA_NOWAIT);
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return 0;
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}
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int
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ess_dma_output(addr, p, cc, intr, arg)
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void *addr;
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@ -1296,45 +1324,30 @@ ess_dma_output(addr, p, cc, intr, arg)
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}
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#endif
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isa_dmastart(sc->sc_ic, sc->sc_out.drq, p, cc,
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NULL, DMAMODE_WRITE, BUS_DMA_NOWAIT);
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sc->sc_out.active = 1;
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sc->sc_out.intr = intr;
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sc->sc_out.arg = arg;
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sc->sc_out.dmaflags = DMAMODE_WRITE;
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sc->sc_out.dmaaddr = p;
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if (sc->sc_out.active)
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return (0);
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if (sc->sc_out.dmacnt != cc) {
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sc->sc_out.dmacnt = cc;
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DPRINTF(("ess_dma_output: set up DMA\n"));
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/*
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* If doing 16-bit DMA transfers, then the number of
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* transfers required is half the number of bytes to
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* be transferred.
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*/
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if (sc->sc_out.drq >= 4)
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cc >>= 1;
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sc->sc_out.active = 1;
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/*
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* Program transfer count registers with 2's
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* complement of count.
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*/
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cc = -cc;
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ess_write_mix_reg(sc, ESS_MREG_XFER_COUNTLO, cc);
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ess_write_mix_reg(sc, ESS_MREG_XFER_COUNTHI, cc >> 8);
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}
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if (IS16BITDRQ(sc->sc_out.drq))
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cc >>= 1; /* use word count for 16 bit DMA */
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/* Program transfer count registers with 2's complement of count. */
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cc = -cc;
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ess_write_mix_reg(sc, ESS_MREG_XFER_COUNTLO, cc);
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ess_write_mix_reg(sc, ESS_MREG_XFER_COUNTHI, cc >> 8);
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/* REVISIT: is it really necessary to clear then set these bits to get
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the next lot of DMA to happen? Would it be sufficient to set the bits
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the first time round and leave it at that? (No, because the chip automatically clears the FIFO_ENABLE bit after the DMA is complete.)
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*/
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/* Start auto-init DMA */
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ess_set_mreg_bits(sc, ESS_MREG_AUDIO2_CTRL1,
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ESS_AUDIO2_CTRL1_DAC_ENABLE);/* REVISIT: once only */
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ess_set_mreg_bits(sc, ESS_MREG_AUDIO2_CTRL1,
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ESS_AUDIO2_CTRL1_FIFO_ENABLE);
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ESS_AUDIO2_CTRL1_DAC_ENABLE |
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ESS_AUDIO2_CTRL1_FIFO_ENABLE |
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ESS_AUDIO2_CTRL1_AUTO_INIT);
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#if 0
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/* REVISIT: seems like the 888 and 1888 have an interlock that
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/* XXX
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* seems like the 888 and 1888 have an interlock that
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* prevents audio2 channel from working if audio1 channel is not
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* connected to the FIFO.
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*/
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@ -1370,8 +1383,6 @@ ess_dma_input(addr, p, cc, intr, arg)
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sc->sc_in.active = 1;
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sc->sc_in.intr = intr;
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sc->sc_in.arg = arg;
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sc->sc_in.dmaflags = DMAMODE_READ;
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sc->sc_in.dmaaddr = p;
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if (sc->sc_in.dmacnt != cc)
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{
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@ -1382,7 +1393,7 @@ ess_dma_input(addr, p, cc, intr, arg)
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* transfers required is half the number of bytes to
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* be transferred.
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*/
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if (sc->sc_out.drq >= 4)
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if (IS16BITDRQ(sc->sc_out.drq))
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cc >>= 1;
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/*
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DPRINTF(("ess_halt_output: sc=%p\n", sc));
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#if 0
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ess_clear_mreg_bits(sc, ESS_MREG_AUDIO2_CTRL2,
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ESS_AUDIO2_CTRL2_DMA_ENABLE);
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#else
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ess_clear_mreg_bits(sc, ESS_MREG_AUDIO2_CTRL1,
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ESS_AUDIO2_CTRL1_FIFO_ENABLE);
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#endif
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return (0);
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}
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@ -1444,13 +1460,11 @@ ess_intr_output(arg)
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/* clear interrupt on Audio channel 2 */
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ess_clear_mreg_bits(sc, ESS_MREG_AUDIO2_CTRL2,
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ESS_AUDIO2_CTRL2_IRQ_LATCH);
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sc->sc_out.nintr++;
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if (sc->sc_out.intr != 0) {
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isa_dmadone(sc->sc_ic, sc->sc_out.drq);
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if (sc->sc_out.intr != 0)
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(*sc->sc_out.intr)(sc->sc_out.arg);
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} else
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else
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return (0);
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return (1);
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@ -1992,7 +2006,7 @@ ess_reset(sc)
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bus_space_handle_t ioh = sc->sc_ioh;
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sc->sc_in.intr = 0;
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sc->sc_in.dmacnt = 0;
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if (sc->sc_in.active) {
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isa_dmaabort(sc->sc_ic, sc->sc_in.drq);
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sc->sc_in.active = 0;
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@ -32,7 +32,7 @@
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*/
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/*
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** @(#) $RCSfile: essreg.h,v $ $Revision: 1.2 $ (SHARK) $Date: 1998/07/31 15:17:18 $
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** @(#) $RCSfile: essreg.h,v $ $Revision: 1.3 $ (SHARK) $Date: 1998/08/04 13:14:42 $
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**
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**++
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**
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@ -242,7 +242,9 @@
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#define ESS_MREG_XFER_COUNTLO 0x74 /* low-byte of DMA transfer size */
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#define ESS_MREG_XFER_COUNTHI 0x76 /* high-byte of DMA transfer size */
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#define ESS_MREG_AUDIO2_CTRL1 0x78 /* control register 1 for Audio2: */
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#define ESS_AUDIO2_CTRL1_TYPE_8BYTE 0xC0
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#define ESS_AUDIO2_CTRL1_XFER_SIZE 0x20 /* 0=8-bit/1=16-bit */
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#define ESS_AUDIO2_CTRL1_AUTO_INIT 0x10
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#define ESS_AUDIO2_CTRL1_FIFO_ENABLE 0x02 /* 0=disable/1=enable */
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#define ESS_AUDIO2_CTRL1_DAC_ENABLE 0x01 /* 0=disable/1=enable */
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#define ESS_MREG_AUDIO2_CTRL2 0x7A /* control register 2 for Audio2: */
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@ -32,7 +32,7 @@
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*/
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/*
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** @(#) $RCSfile: essvar.h,v $ $Revision: 1.3 $ (SHARK) $Date: 1998/07/31 15:17:18 $
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** @(#) $RCSfile: essvar.h,v $ $Revision: 1.4 $ (SHARK) $Date: 1998/08/04 13:14:42 $
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**
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**++
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**
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@ -92,6 +92,7 @@
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struct ess_audio_channel
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{
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int drq; /* DMA channel */
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#define IS16BITDRQ(drq) ((drq) >= 4)
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int irq; /* IRQ line for this DMA channel */
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int ist;
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void *ih; /* interrupt vectoring */
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@ -101,11 +102,9 @@ struct ess_audio_channel
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/* Status information */
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int active; /* boolean: channel in use? */
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int dmaflags; /* value last passed to isa_dmastart */
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caddr_t dmaaddr; /* value last passed to isa_dmastart */
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vm_size_t dmacnt; /* value last passed to isa_dmastart */
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u_int channels; /* 1:mono, 2:stereo */
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u_int dmacnt;
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};
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struct ess_softc
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