Basic unwind support for HPPA.
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joerg
parent
7c2e5bb200
commit
f76ae5ef4f
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@ -1,4 +1,4 @@
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# $NetBSD: bsd.own.mk,v 1.798 2014/04/15 18:40:34 joerg Exp $
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# $NetBSD: bsd.own.mk,v 1.799 2014/04/19 21:21:24 joerg Exp $
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# This needs to be before bsd.init.mk
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.if defined(BSD_MK_COMPAT_FILE)
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@ -100,6 +100,7 @@ HAVE_LIBGCC?= yes
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.endif
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_LIBC_UNWIND_SUPPORT.alpha= yes
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_LIBC_UNWIND_SUPPORT.hppa= yes
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_LIBC_UNWIND_SUPPORT.i386= yes
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_LIBC_UNWIND_SUPPORT.m68k= yes
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_LIBC_UNWIND_SUPPORT.powerpc= yes
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@ -720,6 +720,79 @@ private:
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uint64_t fpreg[31];
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};
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enum {
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DWARF_HPPA_R1 = 1,
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DWARF_HPPA_R31 = 31,
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DWARF_HPPA_FR4L = 32,
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DWARF_HPPA_FR31H = 87,
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REGNO_HPPA_PC = 0,
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REGNO_HPPA_R1 = 1,
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REGNO_HPPA_R2 = 2,
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REGNO_HPPA_R30 = 30,
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REGNO_HPPA_R31 = 31,
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REGNO_HPPA_FR4L = 32,
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REGNO_HPPA_FR31H = 87,
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};
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class Registers_HPPA {
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public:
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enum {
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LAST_REGISTER = REGNO_HPPA_FR31H,
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LAST_RESTORE_REG = REGNO_HPPA_FR31H,
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RETURN_REG = REGNO_HPPA_R2,
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RETURN_OFFSET = -3, // strictly speaking, this is a mask
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};
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__dso_hidden Registers_HPPA();
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static int dwarf2regno(int num) {
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if (num >= DWARF_HPPA_R1 && num <= DWARF_HPPA_R31)
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return REGNO_HPPA_R1 + (num - DWARF_HPPA_R1);
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if (num >= DWARF_HPPA_FR4L && num <= DWARF_HPPA_FR31H)
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return REGNO_HPPA_FR4L + (num - DWARF_HPPA_FR31H);
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return LAST_REGISTER + 1;
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}
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bool validRegister(int num) const {
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return num >= REGNO_HPPA_PC && num <= REGNO_HPPA_R31;
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}
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uint64_t getRegister(int num) const {
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assert(validRegister(num));
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return reg[num];
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}
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void setRegister(int num, uint64_t value) {
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assert(validRegister(num));
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reg[num] = value;
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}
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uint64_t getIP() const { return reg[REGNO_HPPA_PC]; }
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void setIP(uint64_t value) { reg[REGNO_HPPA_PC] = value; }
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uint64_t getSP() const { return reg[REGNO_HPPA_R30]; }
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void setSP(uint64_t value) { reg[REGNO_HPPA_R30] = value; }
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bool validFloatVectorRegister(int num) const {
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return num >= REGNO_HPPA_FR4L && num <= REGNO_HPPA_FR31H;
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}
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void copyFloatVectorRegister(int num, uint64_t addr_) {
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assert(validFloatVectorRegister(num));
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const void *addr = reinterpret_cast<const void *>(addr_);
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memcpy(fpreg + (num - REGNO_HPPA_FR4L), addr, sizeof(fpreg[0]));
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}
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__dso_hidden void jumpto() const __dead;
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private:
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uint32_t reg[REGNO_HPPA_R31 + 1];
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uint32_t fpreg[56];
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};
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#if __i386__
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typedef Registers_x86 NativeUnwindRegisters;
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#elif __x86_64__
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@ -740,6 +813,8 @@ typedef Registers_SPARC64 NativeUnwindRegisters;
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typedef Registers_SPARC NativeUnwindRegisters;
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#elif __alpha__
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typedef Registers_Alpha NativeUnwindRegisters;
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#elif __hppa__
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typedef Registers_HPPA NativeUnwindRegisters;
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#endif
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} // namespace _Unwind
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@ -732,3 +732,137 @@ LEAF_NOPROFILE(_ZNK7_Unwind15Registers_Alpha6jumptoEv, 1)
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ret $31, ($26), 1
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END(_ZNK7_Unwind15Registers_Alpha6jumptoEv)
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#endif
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#if defined(__hppa__)
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LEAF_ENTRY_NOPROFILE(_ZN7_Unwind14Registers_HPPAC1Ev)
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stw %r2, 0(%r26)
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stw %r1, 4(%r26)
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stw %r2, 8(%r26)
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stw %r3, 12(%r26)
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stw %r4, 16(%r26)
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stw %r5, 20(%r26)
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stw %r6, 24(%r26)
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stw %r7, 28(%r26)
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stw %r8, 32(%r26)
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stw %r9, 36(%r26)
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stw %r10, 40(%r26)
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stw %r11, 44(%r26)
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stw %r12, 48(%r26)
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stw %r13, 52(%r26)
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stw %r14, 56(%r26)
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stw %r15, 60(%r26)
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stw %r16, 64(%r26)
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stw %r17, 68(%r26)
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stw %r18, 72(%r26)
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stw %r19, 76(%r26)
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stw %r20, 80(%r26)
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stw %r21, 84(%r26)
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stw %r22, 88(%r26)
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stw %r23, 92(%r26)
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stw %r24, 96(%r26)
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stw %r25, 100(%r26)
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stw %r26, 104(%r26)
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stw %r27, 108(%r26)
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stw %r28, 112(%r26)
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stw %r29, 116(%r26)
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stw %r30, 120(%r26)
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stw %r31, 124(%r26)
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ldi 128, %r19
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addl %r19, %r26, %r19
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fstds,ma %fr4, 8(%r19)
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fstds,ma %fr5, 8(%r19)
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fstds,ma %fr6, 8(%r19)
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fstds,ma %fr7, 8(%r19)
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fstds,ma %fr8, 8(%r19)
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fstds,ma %fr9, 8(%r19)
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fstds,ma %fr10, 8(%r19)
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fstds,ma %fr11, 8(%r19)
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fstds,ma %fr12, 8(%r19)
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fstds,ma %fr13, 8(%r19)
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fstds,ma %fr14, 8(%r19)
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fstds,ma %fr15, 8(%r19)
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fstds,ma %fr16, 8(%r19)
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fstds,ma %fr17, 8(%r19)
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fstds,ma %fr18, 8(%r19)
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fstds,ma %fr19, 8(%r19)
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fstds,ma %fr20, 8(%r19)
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fstds,ma %fr21, 8(%r19)
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fstds,ma %fr22, 8(%r19)
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fstds,ma %fr23, 8(%r19)
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fstds,ma %fr24, 8(%r19)
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fstds,ma %fr25, 8(%r19)
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fstds,ma %fr19, 8(%r19)
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fstds,ma %fr27, 8(%r19)
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fstds,ma %fr28, 8(%r19)
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fstds,ma %fr29, 8(%r19)
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fstds,ma %fr30, 8(%r19)
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fstds,ma %fr31, 8(%r19)
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ldw 76(%r26), %r19
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bv,n %r0(%r2)
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EXIT(_ZN7_Unwind14Registers_HPPAC1Ev)
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LEAF_ENTRY_NOPROFILE(_ZNK7_Unwind14Registers_HPPA6jumptoEv)
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ldi 128, %r19
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addl %r19, %r26, %r19
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fldds,ma 8(%r19), %fr4
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fldds,ma 8(%r19), %fr5
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fldds,ma 8(%r19), %fr6
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fldds,ma 8(%r19), %fr7
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fldds,ma 8(%r19), %fr8
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fldds,ma 8(%r19), %fr9
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fldds,ma 8(%r19), %fr10
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fldds,ma 8(%r19), %fr11
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fldds,ma 8(%r19), %fr12
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fldds,ma 8(%r19), %fr13
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fldds,ma 8(%r19), %fr14
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fldds,ma 8(%r19), %fr15
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fldds,ma 8(%r19), %fr16
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fldds,ma 8(%r19), %fr17
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fldds,ma 8(%r19), %fr18
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fldds,ma 8(%r19), %fr19
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fldds,ma 8(%r19), %fr20
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fldds,ma 8(%r19), %fr21
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fldds,ma 8(%r19), %fr22
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fldds,ma 8(%r19), %fr23
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fldds,ma 8(%r19), %fr24
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fldds,ma 8(%r19), %fr25
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fldds,ma 8(%r19), %fr26
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fldds,ma 8(%r19), %fr27
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fldds,ma 8(%r19), %fr28
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fldds,ma 8(%r19), %fr29
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fldds,ma 8(%r19), %fr30
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fldds,ma 8(%r19), %fr31
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ldw 0(%r26), %r2
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ldw 4(%r26), %r1
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ldw 12(%r26), %r3
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ldw 16(%r26), %r4
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ldw 20(%r26), %r5
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ldw 24(%r26), %r6
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ldw 28(%r26), %r7
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ldw 32(%r26), %r8
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ldw 36(%r26), %r9
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ldw 40(%r26), %r10
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ldw 44(%r26), %r11
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ldw 48(%r26), %r12
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ldw 52(%r26), %r13
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ldw 56(%r26), %r14
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ldw 60(%r26), %r15
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ldw 64(%r26), %r16
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ldw 68(%r26), %r17
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ldw 72(%r26), %r18
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ldw 76(%r26), %r19
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ldw 80(%r26), %r20
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ldw 84(%r26), %r21
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ldw 88(%r26), %r22
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ldw 92(%r26), %r23
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ldw 96(%r26), %r24
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ldw 100(%r26), %r25
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ldw 108(%r26), %r27
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ldw 112(%r26), %r28
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ldw 116(%r26), %r29
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ldw 120(%r26), %r30
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ldw 124(%r26), %r31
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ldw 104(%r26), %r26
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bv,n %r0(%r2)
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EXIT(_ZNK7_Unwind14Registers_HPPA6jumptoEv)
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#endif
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