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Add support for 16550 chips without an Enhanced Register Set.

This commit is contained in:
matt 2008-10-24 04:43:08 +00:00
parent f5d7ce3d2f
commit f759cc96ec
2 changed files with 17 additions and 11 deletions
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27
sys/dev/ic/com.c
View File

@ -434,25 +434,26 @@ com_attach_subr(struct com_softc *sc)
* setting DLAB enable gives access to the EFR on
* these chips.
*/
lcr = CSR_READ_1(regsp, COM_REG_LCR);
CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
CSR_WRITE_1(regsp, COM_REG_EFR, 0);
if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
CSR_WRITE_1(regsp, COM_REG_LCR,
lcr | LCR_DLAB);
if (type != COM_TYPE_16550_NOERS) {
lcr = CSR_READ_1(regsp, COM_REG_LCR);
CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
CSR_WRITE_1(regsp, COM_REG_EFR, 0);
if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
CSR_WRITE_1(regsp, COM_REG_LCR,
lcr | LCR_DLAB);
CLR(sc->sc_hwflags, COM_HW_FIFO);
sc->sc_fifolen = 0;
} else {
SET(sc->sc_hwflags, COM_HW_FLOW);
sc->sc_fifolen = 32;
}
CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
} else
#endif
sc->sc_fifolen = 16;
#ifdef COM_16650
CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
if (sc->sc_fifolen == 0)
fifo_msg = "st16650, broken fifo";
else if (sc->sc_fifolen == 32)
@ -1454,7 +1455,9 @@ com_loadchannelregs(struct com_softc *sc)
}
if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) {
if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */
if (sc->sc_type != COM_TYPE_AU1x00
&& sc->sc_type != COM_TYPE_16550_NOERS) {
/* no EFR on alchemy */
CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr);
CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
}
@ -2146,9 +2149,11 @@ cominit(struct com_regs *regsp, int rate, int frequency, int type,
rate = comspeed(rate, frequency, type);
if (type != COM_TYPE_AU1x00) {
/* no EFR on alchemy */
CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
CSR_WRITE_1(regsp, COM_REG_EFR, 0);
/* no EFR on alchemy */
if (type != COM_TYPE_16550_NOERS) {
CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
CSR_WRITE_1(regsp, COM_REG_EFR, 0);
}
CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB);
CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff);
CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8);

1
sys/dev/ic/comvar.h
View File

@ -207,6 +207,7 @@ struct com_softc {
#define COM_TYPE_PXA2x0 2 /* Intel PXA2x0 processor built-in */
#define COM_TYPE_AU1x00 3 /* AMD/Alchemy Au1x000 proc. built-in */
#define COM_TYPE_OMAP 4 /* TI OMAP processor built-in */
#define COM_TYPE_16550_NOERS 5 /* like a 16550, no ERS */
/* power management hooks */
int (*enable)(struct com_softc *);