Pull some changes for newer chips from FreeBSD:
- pull MACSTAT and CMDSTOP quirks for 8168/8111 chips - always set CPLUSCMD_PCI_MRW on reset - set VLANSTRIP and RXCSUM_ENB bits on CPLUS register per if_capenable Tested on 8111C and 8111D by several users, and no bad side effect on my old 8169S.
This commit is contained in:
tsutsui
parent
fd43b78759
commit
f6e36a0172
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@ -1,4 +1,4 @@
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/* $NetBSD: rtl8169.c,v 1.116 2009/04/13 12:38:06 tsutsui Exp $ */
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/* $NetBSD: rtl8169.c,v 1.117 2009/04/29 15:10:57 tsutsui Exp $ */
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/*
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* Copyright (c) 1997, 1998-2003
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@ -33,7 +33,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.116 2009/04/13 12:38:06 tsutsui Exp $");
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__KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.117 2009/04/29 15:10:57 tsutsui Exp $");
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/* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */
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/*
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@ -593,19 +593,23 @@ re_attach(struct rtk_softc *sc)
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break;
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case RTK_HWREV_8168_SPIN1:
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sc->sc_rev = 21;
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sc->sc_quirk |= RTKQ_MACSTAT;
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break;
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case RTK_HWREV_8168_SPIN2:
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sc->sc_rev = 22;
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sc->sc_quirk |= RTKQ_MACSTAT;
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break;
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case RTK_HWREV_8168_SPIN3:
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sc->sc_rev = 23;
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sc->sc_quirk |= RTKQ_MACSTAT;
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break;
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case RTK_HWREV_8168C:
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case RTK_HWREV_8168C_SPIN2:
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case RTK_HWREV_8168CP:
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case RTK_HWREV_8168D:
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sc->sc_rev = 24;
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sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD;
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sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
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RTKQ_MACSTAT | RTKQ_CMDSTOP;
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/*
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* From FreeBSD driver:
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*
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@ -625,8 +629,8 @@ re_attach(struct rtk_softc *sc)
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case RTK_HWREV_8102EL:
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case RTK_HWREV_8102EL_SPIN2:
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sc->sc_rev = 25;
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sc->sc_quirk |=
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RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_NOJUMBO;
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sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
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RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO;
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break;
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case RTK_HWREV_8100E:
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case RTK_HWREV_8100E_SPIN2:
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@ -1719,6 +1723,7 @@ re_init(struct ifnet *ifp)
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const uint8_t *enaddr;
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uint32_t rxcfg = 0;
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uint32_t reg;
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uint16_t cfg;
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int error;
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if ((error = re_enable(sc)) != 0)
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@ -1736,32 +1741,27 @@ re_init(struct ifnet *ifp)
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* RX checksum offload. We must configure the C+ register
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* before all others.
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*/
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reg = 0;
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/*
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* XXX: Realtek docs say bits 0 and 1 are reserved, for 8169S/8110S.
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* FreeBSD drivers set these bits anyway (for 8139C+?).
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* So far, it works.
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*/
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cfg = RE_CPLUSCMD_PCI_MRW;
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/*
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* XXX: For old 8169 set bit 14.
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* For 8169S/8110S and above, do not set bit 14.
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*/
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if ((sc->sc_quirk & RTKQ_8169NONS) != 0)
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reg |= (0x1 << 14) | RTK_CPLUSCMD_PCI_MRW;
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cfg |= (0x1 << 14);
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if (1) {/* not for 8169S ? */
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reg |=
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RTK_CPLUSCMD_VLANSTRIP |
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(ifp->if_capenable &
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(IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx |
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IFCAP_CSUM_UDPv4_Rx) ?
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RTK_CPLUSCMD_RXCSUM_ENB : 0);
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}
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if ((ifp->if_capenable & ETHERCAP_VLAN_HWTAGGING) != 0)
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cfg |= RE_CPLUSCMD_VLANSTRIP;
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if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx |
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IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0)
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cfg |= RE_CPLUSCMD_RXCSUM_ENB;
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if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) {
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cfg |= RE_CPLUSCMD_MACSTAT_DIS;
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cfg |= RE_CPLUSCMD_TXENB;
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} else
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cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB;
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CSR_WRITE_2(sc, RTK_CPLUS_CMD,
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reg | RTK_CPLUSCMD_RXENB | RTK_CPLUSCMD_TXENB);
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CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg);
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/* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */
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if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0)
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@ -1981,8 +1981,14 @@ re_stop(struct ifnet *ifp, int disable)
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mii_down(&sc->mii);
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CSR_WRITE_1(sc, RTK_COMMAND, 0x00);
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if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0)
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CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB |
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RTK_CMD_RX_ENB);
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else
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CSR_WRITE_1(sc, RTK_COMMAND, 0x00);
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DELAY(1000);
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CSR_WRITE_2(sc, RTK_IMR, 0x0000);
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CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
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if (sc->re_head != NULL) {
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m_freem(sc->re_head);
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@ -1,4 +1,4 @@
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/* $NetBSD: rtl81x9reg.h,v 1.37 2009/04/13 12:33:05 tsutsui Exp $ */
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/* $NetBSD: rtl81x9reg.h,v 1.38 2009/04/29 15:10:57 tsutsui Exp $ */
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/*
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* Copyright (c) 1997, 1998
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@ -309,6 +309,7 @@
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#define RTK_CMD_TX_ENB 0x0004
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#define RTK_CMD_RX_ENB 0x0008
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#define RTK_CMD_RESET 0x0010
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#define RTK_CMD_STOPREQ 0x0080
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/*
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* EEPROM control register
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@ -403,12 +404,21 @@
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/* C+ mode command register */
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#define RTK_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
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#define RTK_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
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#define RTK_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
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#define RTK_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
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#define RTK_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
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#define RTK_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
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#define RE_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
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#define RE_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
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#define RE_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
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#define RE_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
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#define RE_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
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#define RE_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
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#define RE_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */
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#define RE_CPLUSCMD_ASF 0x0100 /* 8168C/CP */
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#define RE_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */
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#define RE_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */
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#define RE_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */
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#define RE_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */
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#define RE_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */
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#define RE_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */
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#define RE_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */
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/* C+ early transmit threshold */
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@ -1,4 +1,4 @@
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/* $NetBSD: rtl81x9var.h,v 1.46 2009/04/26 02:25:57 tsutsui Exp $ */
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/* $NetBSD: rtl81x9var.h,v 1.47 2009/04/29 15:10:57 tsutsui Exp $ */
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/*
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* Copyright (c) 1997, 1998
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@ -192,6 +192,8 @@ struct rtk_softc {
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#define RTKQ_DESCV2 0x00000020 /* has V2 TX/RX descriptor */
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#define RTKQ_NOJUMBO 0x00000040 /* no jumbo MTU support */
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#define RTKQ_NOEECMD 0x00000080 /* unusable EEPROM command */
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#define RTKQ_MACSTAT 0x00000100 /* set MACSTAT_DIS on init */
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#define RTKQ_CMDSTOP 0x00000200 /* set STOPREQ on stop */
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bus_dma_tag_t sc_dmat;
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