Instrument atw(4) delays so that I can experiment and shorten the
conservative delays that I derived from the reference driver.
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f63e03e538
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@ -1,4 +1,4 @@
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/* $NetBSD: atw.c,v 1.69 2004/07/23 07:07:55 dyoung Exp $ */
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/* $NetBSD: atw.c,v 1.70 2004/07/23 07:20:44 dyoung Exp $ */
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/*-
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* Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc.
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@ -41,7 +41,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.69 2004/07/23 07:07:55 dyoung Exp $");
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__KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.70 2004/07/23 07:20:44 dyoung Exp $");
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#include "bpfilter.h"
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@ -141,6 +141,15 @@ __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.69 2004/07/23 07:07:55 dyoung Exp $");
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#define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */
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int atw_voodoo = VOODOO_DUR_11_ROUNDING;
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int atw_pseudo_milli = 1;
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int atw_magic_delay1 = 100 * 1000;
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int atw_magic_delay2 = 100 * 1000;
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/* more magic multi-millisecond delays (units: microseconds) */
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int atw_nar_delay = 20 * 1000;
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int atw_magic_delay4 = 10 * 1000;
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int atw_rf_delay1 = 10 * 1000;
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int atw_rf_delay2 = 5 * 1000;
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int atw_plcphd_delay = 2 * 1000;
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int atw_bbp_io_enable_delay = 20 * 1000;
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int atw_bbp_io_disable_delay = 2 * 1000;
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int atw_writewep_delay = 1000;
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@ -937,7 +946,7 @@ atw_reset(struct atw_softc *sc)
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uint32_t lpc;
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ATW_WRITE(sc, ATW_NAR, 0x0);
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DELAY(20 * 1000);
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DELAY(atw_nar_delay);
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/* Reference driver has a cryptic remark indicating that this might
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* power-on the chip. I know that it turns off power-saving....
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@ -946,14 +955,14 @@ atw_reset(struct atw_softc *sc)
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ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR);
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for (i = 0; i < 50; i++) {
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for (i = 0; i < 50000 / atw_pseudo_milli; i++) {
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if (ATW_READ(sc, ATW_PAR) == 0)
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break;
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DELAY(1000);
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DELAY(atw_pseudo_milli);
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}
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/* ... and then pause 100ms longer for good measure. */
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DELAY(100 * 1000);
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DELAY(atw_magic_delay1);
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DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i));
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@ -977,12 +986,12 @@ atw_reset(struct atw_softc *sc)
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*/
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ATW_WRITE(sc, ATW_FRCTL, 0x0);
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DELAY(100 * 1000);
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DELAY(atw_magic_delay2);
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/* Recall EEPROM. */
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ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD);
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DELAY(10 * 1000);
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DELAY(atw_magic_delay4);
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lpc = ATW_READ(sc, ATW_LPC);
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@ -1102,9 +1111,9 @@ atw_rf_reset(struct atw_softc *sc)
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/* XXX this resets an Intersil RF front-end? */
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/* TBD condition on Intersil RFType? */
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ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN);
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DELAY(10 * 1000);
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DELAY(atw_rf_delay1);
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ATW_WRITE(sc, ATW_SYNRF, 0);
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DELAY(5 * 1000);
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DELAY(atw_rf_delay2);
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}
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/* Set 16 TU max duration for the contention-free period (CFP). */
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@ -1489,7 +1498,7 @@ atw_tune(struct atw_softc *sc)
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chan);
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ATW_WRITE(sc, ATW_NAR, sc->sc_opmode);
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DELAY(20 * 1000);
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DELAY(atw_nar_delay);
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ATW_WRITE(sc, ATW_RDR, 0x1);
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if (rc == 0)
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@ -1789,7 +1798,7 @@ out:
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reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK),
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ATW_PLCPHD_SERVICE_MASK);
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ATW_WRITE(sc, ATW_PLCPHD, reg);
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DELAY(2 * 1000);
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DELAY(atw_plcphd_delay);
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return rc;
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}
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@ -1809,9 +1818,9 @@ atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val)
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LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) |
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LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);
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for (i = 10; --i >= 0; ) {
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for (i = 20000 / atw_pseudo_milli; --i >= 0; ) {
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ATW_WRITE(sc, ATW_BBPCTL, reg);
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DELAY(2000);
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DELAY(2 * atw_pseudo_milli);
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if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0)
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break;
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}
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@ -2033,7 +2042,7 @@ setit:
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ATW_WRITE(sc, ATW_MAR0, hashes[0]);
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ATW_WRITE(sc, ATW_MAR1, hashes[1]);
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ATW_WRITE(sc, ATW_NAR, sc->sc_opmode);
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DELAY(20 * 1000);
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DELAY(atw_nar_delay);
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DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname,
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ATW_READ(sc, ATW_NAR), sc->sc_opmode));
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@ -2704,7 +2713,7 @@ atw_stop(struct ifnet *ifp, int disable)
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/* Stop the transmit and receive processes. */
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sc->sc_opmode = 0;
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ATW_WRITE(sc, ATW_NAR, 0);
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DELAY(20 * 1000);
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DELAY(atw_nar_delay);
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ATW_WRITE(sc, ATW_TDBD, 0);
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ATW_WRITE(sc, ATW_TDBP, 0);
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ATW_WRITE(sc, ATW_RDB, 0);
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@ -2934,7 +2943,7 @@ atw_intr(void *arg)
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* the transmit process.
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*/
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ATW_WRITE(sc, ATW_NAR, sc->sc_opmode);
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DELAY(20 * 1000);
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DELAY(atw_nar_delay);
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ATW_WRITE(sc, ATW_RDR, 0x1);
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/* XXX Log every Nth underrun from
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* XXX now on?
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@ -3011,13 +3020,13 @@ atw_idle(struct atw_softc *sc, u_int32_t bits)
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}
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ATW_WRITE(sc, ATW_NAR, opmode);
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DELAY(20 * 1000);
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DELAY(atw_nar_delay);
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for (i = 0; i < 10; i++) {
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for (i = 0; i < 1000; i++) {
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stsr = ATW_READ(sc, ATW_STSR);
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if ((stsr & ackmask) == ackmask)
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break;
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DELAY(1000);
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DELAY(10);
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}
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ATW_WRITE(sc, ATW_STSR, stsr & ackmask);
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