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repair algor support a bit.

This commit is contained in:
soda 2000-06-09 05:38:13 +00:00
parent 1258a24612
commit f626d8a91c
4 changed files with 126 additions and 120 deletions
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4
sys/arch/arc/algor/algor.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: algor.h,v 1.3 2000/02/22 11:25:56 soda Exp $ */
/* $NetBSD: algor.h,v 1.4 2000/06/09 05:38:13 soda Exp $ */
/* $OpenBSD: algor.h,v 1.4 1998/03/16 09:38:23 pefo Exp $ */
/*
@ -146,7 +146,7 @@ struct algor_int_desc {
};
int algor_intrnull __P((void *));
void *algor_pci_intr_establish __P((int, int, intr_handler_t, void *, void *));
void *algor_pci_intr_establish __P((int, int, intr_handler_t, void *));
void algor_pci_intr_disestablish __P((void *));

75
sys/arch/arc/algor/algorbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: algorbus.c,v 1.3 2000/02/22 11:25:56 soda Exp $ */
/* $NetBSD: algorbus.c,v 1.4 2000/06/09 05:38:13 soda Exp $ */
/* $OpenBSD: algorbus.c,v 1.6 1999/01/11 05:11:09 millert Exp $ */
/*
@ -63,9 +63,8 @@ int algorprint(void *, const char *);
struct cfattach algor_ca = {
sizeof(struct algor_softc), algormatch, algorattach
};
struct cfdriver algor_cd = {
NULL, "algor", DV_DULL, NULL, 0
};
extern struct cfdriver algor_cd;
void algor_intr_establish __P((struct confargs *, int (*)(void *), void *));
void algor_intr_disestablish __P((struct confargs *));
@ -75,6 +74,11 @@ int algor_iointr __P((unsigned, struct clockframe *));
int algor_clkintr __P((unsigned, struct clockframe *));
int algor_errintr __P((unsigned, struct clockframe *));
#define ALGOR_IPL_BIO 0
#define ALGOR_IPL_NET 1
#define ALGOR_IPL_TTY 2
#define ALGOR_IPL_CLOCK 3
int p4032_imask = 0;
int p4032_ixr0 = 0; /* Routing for local and panic ints. */
int p4032_ixr1 = 0; /* Routing for pci and ide ints. */
@ -116,36 +120,36 @@ struct algor_dev {
};
struct algor_dev algor_4032_cpu[] = {
{{ "dallas_rtc", 0, 0, },
P4032_IM_RTC, IPL_CLOCK, 0xc000, algor_intrnull, (void *)P4032_CLOCK, },
P4032_IM_RTC, ALGOR_IPL_CLOCK, 0xc000, algor_intrnull, (void *)P4032_CLOCK, },
{{ "com", 1, 0, },
P4032_IM_COM1, IPL_TTY, 0x00c0, algor_intrnull, (void *)P4032_COM1, },
P4032_IM_COM1, ALGOR_IPL_TTY, 0x00c0, algor_intrnull, (void *)P4032_COM1, },
{{ "com", 2, 0, },
P4032_IM_COM2, IPL_TTY, 0x0300, algor_intrnull, (void *)P4032_COM2, },
P4032_IM_COM2, ALGOR_IPL_TTY, 0x0300, algor_intrnull, (void *)P4032_COM2, },
{{ "lpt", 3, 0, },
P4032_IM_CENTR,IPL_TTY, 0x0c00, algor_intrnull, (void *)P4032_CENTR, },
P4032_IM_CENTR,ALGOR_IPL_TTY, 0x0c00, algor_intrnull, (void *)P4032_CENTR, },
{{ NULL, -1, NULL, },
0, 0x0000, NULL, (void *)NULL, },
};
struct algor_dev algor_5064_cpu[] = {
{{ "dallas_rtc", 0, 0, },
P4032_IM_RTC, IPL_CLOCK, 0xc000, algor_intrnull, (void *)P5064_CLOCK, },
P4032_IM_RTC, ALGOR_IPL_CLOCK, 0xc000, algor_intrnull, (void *)P5064_CLOCK, },
{{ "com", 1, 0, },
P4032_IM_COM1, IPL_TTY, 0x00c0, algor_intrnull, (void *)P5064_COM1, },
P4032_IM_COM1, ALGOR_IPL_TTY, 0x00c0, algor_intrnull, (void *)P5064_COM1, },
{{ "com", 2, 0, },
P4032_IM_COM2, IPL_TTY, 0x0300, algor_intrnull, (void *)P5064_COM2, },
P4032_IM_COM2, ALGOR_IPL_TTY, 0x0300, algor_intrnull, (void *)P5064_COM2, },
{{ "lpt", 3, 0, },
P4032_IM_CENTR,IPL_TTY, 0x0c00, algor_intrnull, (void *)P5064_CENTR, },
P4032_IM_CENTR,ALGOR_IPL_TTY, 0x0c00, algor_intrnull, (void *)P5064_CENTR, },
{{ NULL, -1, NULL, },
0, 0x0000, NULL, (void *)NULL, },
};
/* IPL routing values */
static int ipxrtab[] = {
0x00000000, /* IPL_BIO */
0x55555555, /* IPL_NET */
0xaaaaaaaa, /* IPL_TTY */
0xffffffff, /* IPL_CLOCK */
0x00000000, /* ALGOR_IPL_BIO */
0x55555555, /* ALGOR_IPL_NET */
0xaaaaaaaa, /* ALGOR_IPL_TTY */
0xffffffff, /* ALGOR_IPL_CLOCK */
};
@ -171,8 +175,8 @@ algormatch(parent, match, aux)
/* Make sure that unit exists. */
if (match->cf_unit != 0
|| (system_type - ALGOR_CLASS) > nalgor_cpu_devs
|| algor_cpu_devs[system_type - ALGOR_CLASS] == NULL)
|| (cputype - ALGOR_CLASS) > nalgor_cpu_devs
|| algor_cpu_devs[cputype - ALGOR_CLASS] == NULL)
return (0);
return (1);
@ -191,7 +195,7 @@ algorattach(parent, self, aux)
printf("\n");
/* keep our CPU device description handy */
sc->sc_devs = algor_cpu_devs[system_type - ALGOR_CLASS];
sc->sc_devs = algor_cpu_devs[cputype - ALGOR_CLASS];
/* set up interrupt handlers */
set_intr(MIPS_INT_MASK_1, algor_iointr, 3);
@ -227,7 +231,7 @@ algorprint(aux, pnp)
if (pnp)
printf("%s at %s", ca->ca_name, pnp);
printf(" slot %ld offset 0x%lx", ca->ca_slot, ca->ca_offset);
printf(" slot %d offset 0x%x", ca->ca_slot, ca->ca_offset);
return (UNCONF);
}
@ -237,7 +241,7 @@ algor_cvtaddr(ca)
{
struct algor_softc *sc = algor_cd.cd_devs[0];
return(sc->sc_devs[ca->ca_slot].ps_base + ca->ca_offset);
return((caddr_t)sc->sc_devs[ca->ca_slot].ps_base + ca->ca_offset);
}
@ -261,7 +265,7 @@ algor_intr_establish(ca, handler, arg)
int_table[slot].param = arg;
}
p4032_ixr0 |= ipxrtab[ipl] & dev->ps_route;
switch(system_type) {
switch(cputype) {
case ALGOR_P4032:
outb(P4032_IXR0, p4032_ixr0);
outb(P4032_IXR1, p4032_ixr0 >> 8);
@ -285,25 +289,32 @@ algor_intr_establish(ca, handler, arg)
}
void *
algor_pci_intr_establish(ih, level, handler, arg, name)
algor_pci_intr_establish(ih, level, handler, arg)
int ih;
int level;
intr_handler_t handler;
void *arg;
void *name;
{
int imask;
int route;
int slot;
if(level < IPL_BIO || level >= IPL_CLOCK) {
panic("pci intr: ipl level out of range");
#ifdef __GNUC__
imask = route = 0; /* XXX: shut up gcc warning */
#endif
switch (level) {
case IPL_BIO: level = ALGOR_IPL_BIO; break;
case IPL_NET: level = ALGOR_IPL_NET; break;
case IPL_TTY: level = ALGOR_IPL_TTY; break;
case IPL_CLOCK: level = ALGOR_IPL_CLOCK;break;
default: panic("pci intr: ipl level %d out of range", level);
}
if(ih < 0 || ih >= 12 || ih == 7 || ih == 8) {
panic("pci intr: irq out of range");
panic("pci intr: irq %d out of range", ih);
}
switch(system_type) {
switch(cputype) {
case ALGOR_P4032:
imask = (0x00001000 << ih);
route = (0x3 << (ih+ih));
@ -334,7 +345,7 @@ algor_pci_intr_establish(ih, level, handler, arg, name)
int_table[slot].param = arg;
p4032_ixr1 |= ipxrtab[level] & route;
switch(system_type) {
switch(cputype) {
case ALGOR_P4032:
outb(P4032_IXR2, p4032_ixr1);
break;
@ -435,7 +446,7 @@ algor_clkintr(mask, cf)
struct clockframe *cf;
{
/* Ack clock interrupt */
if(system_type == ALGOR_P4032) {
if(cputype == ALGOR_P4032) {
outb(P4032_CLOCK, MC_REGC);
(void) inb(P4032_CLOCK + 4);
}
@ -447,9 +458,9 @@ algor_clkintr(mask, cf)
hardclock(cf);
/* Re-enable clock interrupts */
splx(MIPS_INT_MASK_0 << IPL_CLOCK | MIPS_SR_INT_IE);
splx(MIPS_INT_MASK_0 << ALGOR_IPL_CLOCK | MIPS_SR_INT_IE);
return(~(MIPS_INT_MASK_0 << IPL_CLOCK)); /* Keep clock interrupts enabled */
return(~(MIPS_INT_MASK_0 << ALGOR_IPL_CLOCK)); /* Keep clock interrupts enabled */
}
/*

153
sys/arch/arc/pci/pbcpcibus.c
View File

@ -1,8 +1,8 @@
/* $NetBSD: pbcpcibus.c,v 1.4 2000/06/09 05:38:15 soda Exp $ */
/* $OpenBSD: pbcpcibus.c,v 1.7 1998/03/25 11:52:48 pefo Exp $ */
/* $OpenBSD: pbcpcibus.c,v 1.4 1997/04/19 17:20:02 pefo Exp $ */
/*
* Copyright (c) 1997 Per Fogelstrom
* Copyright (c) 1997, 1998 Per Fogelstrom, Opsycon AB
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -64,32 +64,31 @@ void pbcpcibrattach __P((struct device *, struct device *, void *));
void pbc_attach_hook __P((struct device *, struct device *,
struct pcibus_attach_args *));
int pbc_bus_maxdevs __P((void *, int));
pcitag_t pbc_make_tag __P((void *, int, int, int));
void pbc_decompose_tag __P((void *, pcitag_t, int *, int *, int *));
pcireg_t pbc_conf_read __P((void *, pcitag_t, int));
void pbc_conf_write __P((void *, pcitag_t, int, pcireg_t));
int pbc_bus_maxdevs __P((pci_chipset_tag_t, int));
pcitag_t pbc_make_tag __P((pci_chipset_tag_t, int, int, int));
void pbc_decompose_tag __P((pci_chipset_tag_t, pcitag_t, int *, int *,
int *));
pcireg_t pbc_conf_read __P((pci_chipset_tag_t, pcitag_t, int));
void pbc_conf_write __P((pci_chipset_tag_t, pcitag_t, int, pcireg_t));
int pbc_intr_map __P((void *, pcitag_t, int, int, pci_intr_handle_t *));
const char *pbc_intr_string __P((void *, pci_intr_handle_t));
void *pbc_intr_establish __P((void *, pci_intr_handle_t,
int, int (*func)(void *), void *, char *));
void pbc_intr_disestablish __P((void *, void *));
int pbc_ether_hw_addr __P((u_int8_t *));
int pbc_intr_map __P((pci_chipset_tag_t, pcitag_t, int, int,
pci_intr_handle_t *));
const char *pbc_intr_string __P((pci_chipset_tag_t, pci_intr_handle_t));
void *pbc_intr_establish __P((pci_chipset_tag_t, pci_intr_handle_t,
int, int (*)(void *), void *));
void pbc_intr_disestablish __P((pci_chipset_tag_t, void *));
struct cfattach pbcpcibr_ca = {
sizeof(struct pcibr_softc), pbcpcibrmatch, pbcpcibrattach,
};
struct cfdriver pbcpcibr_cd = {
NULL, "pbcpcibr", DV_DULL,
};
extern struct cfdriver pbcpcibr_cd;
static int pbcpcibrprint __P((void *, const char *pnp));
struct pcibr_config pbc_config;
static int pbc_version;
#ifdef __OpenBSD__
/*
* Code from "pci/if_de.c" used to calculate crc32 of ether rom data.
* Another example can be found in document EC-QPQWA-TE from DEC.
@ -108,6 +107,7 @@ srom_crc32(const unsigned char *databuf, size_t datalen)
}
return (crc);
}
#endif
int
@ -131,39 +131,35 @@ pbcpcibrattach(parent, self, aux)
void *aux;
{
struct pcibr_softc *sc = (struct pcibr_softc *)self;
struct pcibr_config *lcp;
struct pcibus_attach_args pba;
switch(cputype) {
case ALGOR_P4032:
case ALGOR_P5064:
V96X_PCI_BASE0 = V96X_PCI_BASE0 & 0xffff0000;
lcp = sc->sc_pcibr = &pbc_config;
sc->sc_bus_space.bus_base = V96X_PCI_MEM_SPACE;
sc->sc_bus_space.bus_sparse1 = 0;
sc->sc_bus_space.bus_sparse2 = 0;
sc->sc_bus_space.bus_sparse4 = 0;
sc->sc_bus_space.bus_sparse8 = 0;
lcp->lc_pc.pc_conf_v = lcp;
lcp->lc_pc.pc_attach_hook = pbc_attach_hook;
lcp->lc_pc.pc_bus_maxdevs = pbc_bus_maxdevs;
lcp->lc_pc.pc_make_tag = pbc_make_tag;
lcp->lc_pc.pc_decompose_tag = pbc_decompose_tag;
lcp->lc_pc.pc_conf_read = pbc_conf_read;
lcp->lc_pc.pc_conf_write = pbc_conf_write;
lcp->lc_pc.pc_ether_hw_addr = pbc_ether_hw_addr;
lcp->lc_pc.pc_sync_cache = mips3_HitFlushDCache;
lcp->lc_pc.pc_intr_v = lcp;
lcp->lc_pc.pc_intr_map = pbc_intr_map;
lcp->lc_pc.pc_intr_string = pbc_intr_string;
lcp->lc_pc.pc_intr_establish = pbc_intr_establish;
lcp->lc_pc.pc_intr_disestablish = pbc_intr_disestablish;
pbc_version = V96X_PCI_CC_REV;
arc_bus_space_init(&sc->sc_bus_space, "pbcpci",
0LL, MIPS_KSEG1_START,
V96X_PCI_MEM_SPACE, MIPS_KSEG2_START - MIPS_KSEG1_START);
_bus_dma_tag_init(&sc->sc_dmat);
if (pbc_version < V96X_VREV_C0) {
/* XXX - Is this OK? */
/* BUG in early V962PBC's: Use aparture II */
sc->sc_dmat.dma_offset = 0xc0000000;
}
sc->sc_pc.pc_attach_hook = pbc_attach_hook;
sc->sc_pc.pc_bus_maxdevs = pbc_bus_maxdevs;
sc->sc_pc.pc_make_tag = pbc_make_tag;
sc->sc_pc.pc_conf_read = pbc_conf_read;
sc->sc_pc.pc_conf_write = pbc_conf_write;
sc->sc_pc.pc_intr_map = pbc_intr_map;
sc->sc_pc.pc_intr_string = pbc_intr_string;
sc->sc_pc.pc_intr_establish = pbc_intr_establish;
sc->sc_pc.pc_intr_disestablish = pbc_intr_disestablish;
printf(": V3 V962, Revision %x.\n", pbc_version);
break;
}
@ -171,7 +167,9 @@ pbcpcibrattach(parent, self, aux)
pba.pba_busname = "pci";
pba.pba_iot = &sc->sc_bus_space;
pba.pba_memt = &sc->sc_bus_space;
pba.pba_pc = &lcp->lc_pc;
pba.pba_dmat = &sc->sc_dmat;
pba.pba_pc = &sc->sc_pc;
pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
pba.pba_bus = 0;
config_found(self, &pba, pbcpcibrprint);
@ -190,6 +188,7 @@ pbcpcibrprint(aux, pnp)
return(UNCONF);
}
#ifdef __OpenBSD__
/*
* Get PCI physical address from given viritual address.
*/
@ -205,7 +204,7 @@ vtophysaddr(dp, va)
va = (vaddr_t)curproc->p_addr + (va & ~UADDR);
}
if(va < VM_MIN_KERNEL_ADDRESS) {
pa = MIPS_CACHED_TO_PHYS(va);
pa = MIPS_KSEG0_TO_PHYS(va);
}
else if (!pmap_extract(vm_map_pmap(phys_map), va, &pa)) {
panic("pbcpcibus.c:vtophysaddr(): pmap_extract %p", va);
@ -216,6 +215,7 @@ vtophysaddr(dp, va)
}
return(pa);
}
#endif
void
pbc_attach_hook(parent, self, pba)
@ -225,24 +225,24 @@ pbc_attach_hook(parent, self, pba)
}
int
pbc_bus_maxdevs(cpv, busno)
void *cpv;
pbc_bus_maxdevs(pc, busno)
pci_chipset_tag_t pc;
int busno;
{
return(16);
}
pcitag_t
pbc_make_tag(cpv, bus, dev, fnc)
void *cpv;
pbc_make_tag(pc, bus, dev, fnc)
pci_chipset_tag_t pc;
int bus, dev, fnc;
{
return (bus << 16) | (dev << 11) | (fnc << 8);
}
void
pbc_decompose_tag(cpv, tag, busp, devp, fncp)
void *cpv;
pbc_decompose_tag(pc, tag, busp, devp, fncp)
pci_chipset_tag_t pc;
pcitag_t tag;
int *busp, *devp, *fncp;
{
@ -255,8 +255,8 @@ pbc_decompose_tag(cpv, tag, busp, devp, fncp)
}
pcireg_t
pbc_conf_read(cpv, tag, offset)
void *cpv;
pbc_conf_read(pc, tag, offset)
pci_chipset_tag_t pc;
pcitag_t tag;
int offset;
{
@ -265,11 +265,15 @@ pbc_conf_read(cpv, tag, offset)
int bus, device, func, ad_low;
int s;
#ifdef __GNUC__
addr = 0; /* XXX: shut up gcc warning */
#endif
if(offset & 3 || offset < 0 || offset >= 0x100) {
printf ("pci_conf_read: bad reg %x\n", offset);
return(~0);
}
pbc_decompose_tag(cpv, tag, &bus, &device, &func);
pbc_decompose_tag(pc, tag, &bus, &device, &func);
ad_low = 0;
switch (cputype) {
@ -309,8 +313,6 @@ pbc_conf_read(cpv, tag, offset)
/* clear aborts */
V96X_PCI_STAT |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT;
/* high 12 bits of address go in map register, and set for conf space */
V96X_LB_MAP0 = ((addr >> 16) & V96X_LB_MAPx_MAP_ADR) | V96X_LB_TYPE_CONF;
wbflush();
/* low 20 bits of address are in the actual address */
@ -332,8 +334,8 @@ pbc_conf_read(cpv, tag, offset)
}
void
pbc_conf_write(cpv, tag, offset, data)
void *cpv;
pbc_conf_write(pc, tag, offset, data)
pci_chipset_tag_t pc;
pcitag_t tag;
int offset;
pcireg_t data;
@ -342,7 +344,10 @@ pbc_conf_write(cpv, tag, offset, data)
int bus, device, func, ad_low;
int s;
pbc_decompose_tag(cpv, tag, &bus, &device, &func);
#ifdef __GNUC__
addr = 0; /* XXX: shut up gcc warning */
#endif
pbc_decompose_tag(pc, tag, &bus, &device, &func);
ad_low = 0;
switch (cputype) {
@ -382,8 +387,6 @@ pbc_conf_write(cpv, tag, offset, data)
/* clear aborts */
V96X_PCI_STAT |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT;
/* high 12 bits of address go in map register, and set for conf space */
V96X_LB_MAP0 = ((addr >> 16) & V96X_LB_MAPx_MAP_ADR) | V96X_LB_TYPE_CONF;
wbflush();
/* low 20 bits of address are in the actual address */
@ -406,6 +409,7 @@ pbc_conf_write(cpv, tag, offset, data)
splx(s);
}
#ifdef __OpenBSD__
/*
* Build the serial rom info normaly stored in an EEROM on
* PCI DEC21x4x boards. Cheapo designs skips the rom so
@ -465,16 +469,15 @@ pbc_ether_hw_addr(p)
p[127] = i >> 8;
return(1); /* Got it! */
}
#endif
int
pbc_intr_map(lcv, bustag, buspin, line, ihp)
void *lcv;
pbc_intr_map(pc, bustag, buspin, line, ihp)
pci_chipset_tag_t pc;
pcitag_t bustag;
int buspin, line;
pci_intr_handle_t *ihp;
{
struct pcibr_config *lcp = lcv;
pci_chipset_tag_t pc = &lcp->lc_pc;
int device, pirq;
if (buspin == 0) {
@ -488,7 +491,7 @@ pbc_intr_map(lcv, bustag, buspin, line, ihp)
return 1;
}
pci_decompose_tag(pc, bustag, NULL, &device, NULL);
pbc_decompose_tag(pc, bustag, NULL, &device, NULL);
pirq = buspin - 1;
switch(device) {
@ -519,31 +522,31 @@ pbc_intr_map(lcv, bustag, buspin, line, ihp)
}
const char *
pbc_intr_string(lcv, ih)
void *lcv;
pbc_intr_string(pc, ih)
pci_chipset_tag_t pc;
pci_intr_handle_t ih;
{
static char str[16];
sprintf(str, "pciirq%d", ih);
sprintf(str, "pciirq%ld", ih);
return(str);
}
void *
pbc_intr_establish(lcv, ih, level, func, arg, name)
void *lcv;
pbc_intr_establish(pc, ih, level, func, arg)
pci_chipset_tag_t pc;
pci_intr_handle_t ih;
int level;
int (*func) __P((void *));
void *arg;
char *name;
{
return algor_pci_intr_establish(ih, level, func, arg, name);
return algor_pci_intr_establish(ih, level, func, arg);
}
void
pbc_intr_disestablish(lcv, cookie)
void *lcv, *cookie;
pbc_intr_disestablish(pc, cookie)
pci_chipset_tag_t pc;
void *cookie;
{
algor_pci_intr_disestablish(cookie);
}

14
sys/arch/arc/pci/pcibrvar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pcibrvar.h,v 1.2 2000/01/23 21:02:00 soda Exp $ */
/* $NetBSD: pcibrvar.h,v 1.3 2000/06/09 05:38:15 soda Exp $ */
/* $OpenBSD: pcibrvar.h,v 1.2 1997/04/10 16:29:32 pefo Exp $ */
/*
@ -33,17 +33,9 @@
*
*/
struct pcibr_config {
bus_space_tag_t lc_iot;
bus_space_tag_t lc_memt;
struct arc_pci_chipset lc_pc;
int pci_init_done;
};
struct pcibr_softc {
struct device sc_dev;
struct pcibr_config *sc_pcibr;
struct arc_bus_space sc_bus_space; /* Same for I/O and Mem */
struct arc_bus_dma_tag sc_dmat;
struct arc_pci_chipset sc_pc;
};