No mac has a VAC.
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briggs
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.24 1996/05/05 06:54:19 briggs Exp $ */
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/* $NetBSD: pmap.c,v 1.25 1996/05/07 01:45:22 briggs Exp $ */
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/*
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* Copyright (c) 1991, 1993
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@ -175,14 +175,6 @@ int pmapdebug = 0x2000;
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#define PDB_WIRING 0x4000
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#define PDB_PVDUMP 0x8000
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#ifdef HAVEVAC
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int pmapvacflush = 0;
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#define PVF_ENTER 0x01
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#define PVF_REMOVE 0x02
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#define PVF_PROTECT 0x04
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#define PVF_TOTAL 0x80
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#endif
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#if defined(M68040)
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int dowriteback = 1; /* 68040: enable writeback caching */
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int dokwriteback = 1; /* 68040: enable writeback caching of kernel AS */
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@ -291,9 +283,6 @@ extern int numranges;
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extern unsigned long low[8];
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extern unsigned long high[8];
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#ifdef HAVEVAC
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int pmap_aliasmask; /* seperation at which VA aliasing ok */
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#endif
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#if defined(M68040)
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int protostfree; /* prototype (default) free ST map */
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#endif
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@ -878,29 +867,6 @@ pmap_remove(pmap, sva, eva)
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pte = pmap_pte(pmap, sva);
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while (sva < nssva) {
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if (pmap_pte_v(pte)) {
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#ifdef HAVEVAC
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if (pmap_aliasmask) {
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/*
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* Purge kernel side of VAC to ensure
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* we get the correct state of any
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* hardware maintained bits.
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*/
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if (firstpage) {
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DCIS();
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#ifdef PMAPSTATS
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remove_stats.sflushes++;
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#endif
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}
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/*
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* Remember if we may need to
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* flush the VAC due to a non-CI
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* mapping.
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*/
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if (!needcflush && !pmap_pte_ci(pte))
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needcflush = TRUE;
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}
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#endif
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pmap_remove_mapping(pmap, sva, pte, flags);
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firstpage = FALSE;
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}
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@ -913,42 +879,6 @@ pmap_remove(pmap, sva, eva)
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*/
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if (firstpage)
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return;
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#ifdef HAVEVAC
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/*
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* In a couple of cases, we don't need to worry about flushing
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* the VAC:
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* 1. if this is a kernel mapping,
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* we have already done it
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* 2. if it is a user mapping not for the current process,
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* it won't be there
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*/
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if (pmap_aliasmask &&
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(pmap == pmap_kernel() || pmap != curproc->p_vmspace->vm_map.pmap))
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needcflush = FALSE;
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#ifdef DEBUG
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if (pmap_aliasmask && (pmapvacflush & PVF_REMOVE)) {
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if (pmapvacflush & PVF_TOTAL)
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DCIA();
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else if (pmap == pmap_kernel())
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DCIS();
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else
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DCIU();
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} else
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#endif
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if (needcflush) {
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if (pmap == pmap_kernel()) {
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DCIS();
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#ifdef PMAPSTATS
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remove_stats.sflushes++;
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#endif
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} else {
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DCIU();
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#ifdef PMAPSTATS
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remove_stats.uflushes++;
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#endif
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}
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}
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#endif
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}
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/*
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@ -1066,18 +996,6 @@ pmap_protect(pmap, sva, eva, prot)
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pte = pmap_pte(pmap, sva);
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while (sva < nssva) {
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if (pmap_pte_v(pte) && pmap_pte_prot_chg(pte, isro)) {
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#ifdef HAVEVAC
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/*
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* Purge kernel side of VAC to ensure we
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* get the correct state of any hardware
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* maintained bits.
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*
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* XXX do we need to clear the VAC in
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* general to reflect the new protection?
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*/
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if (firstpage && pmap_aliasmask)
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DCIS();
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#endif
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#if defined(M68040)
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/*
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* Clear caches if making RO (see section
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@ -1110,16 +1028,6 @@ pmap_protect(pmap, sva, eva, prot)
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sva += NBPG;
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}
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}
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#if defined(HAVEVAC) && defined(DEBUG)
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if (pmap_aliasmask && (pmapvacflush & PVF_PROTECT)) {
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if (pmapvacflush & PVF_TOTAL)
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DCIA();
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else if (pmap == pmap_kernel())
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DCIS();
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else
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DCIU();
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}
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#endif
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}
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void
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@ -1319,56 +1227,6 @@ pmap_enter(pmap, va, pa, prot, wired)
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#ifdef PMAPSTATS
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if (!npv->pv_next)
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enter_stats.secondpv++;
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#endif
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#ifdef HAVEVAC
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/*
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* Since there is another logical mapping for the
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* same page we may need to cache-inhibit the
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* descriptors on those CPUs with external VACs.
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* We don't need to CI if:
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*
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* - No two mappings belong to the same user pmaps.
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* Since the cache is flushed on context switches
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* there is no problem between user processes.
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*
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* - Mappings within a single pmap are a certain
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* magic distance apart. VAs at these appropriate
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* boundaries map to the same cache entries or
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* otherwise don't conflict.
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*
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* To keep it simple, we only check for these special
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* cases if there are only two mappings, otherwise we
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* punt and always CI.
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*
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* Note that there are no aliasing problems with the
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* on-chip data-cache when the WA bit is set.
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*/
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if (pmap_aliasmask) {
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if (pv->pv_flags & PV_CI) {
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#ifdef DEBUG
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if (pmapdebug & PDB_CACHE)
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printf("enter: pa %x already CI'ed\n",
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pa);
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#endif
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checkpv = cacheable = FALSE;
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} else if (npv->pv_next ||
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((pmap == pv->pv_pmap ||
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pmap == pmap_kernel() ||
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pv->pv_pmap == pmap_kernel()) &&
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((pv->pv_va & pmap_aliasmask) !=
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(va & pmap_aliasmask)))) {
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#ifdef DEBUG
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if (pmapdebug & PDB_CACHE)
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printf("enter: pa %x CI'ing all\n",
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pa);
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#endif
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cacheable = FALSE;
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pv->pv_flags |= PV_CI;
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#ifdef PMAPSTATS
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enter_stats.ci++;
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#endif
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}
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}
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#endif
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}
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splx(s);
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@ -1392,14 +1250,6 @@ pmap_enter(pmap, va, pa, prot, wired)
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pmap->pm_stats.wired_count++;
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validate:
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#ifdef HAVEVAC
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/*
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* Purge kernel side of VAC to ensure we get correct state
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* of HW bits so we don't clobber them.
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*/
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if (pmap_aliasmask)
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DCIS();
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#endif
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/*
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* Build the new PTE.
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*/
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@ -1433,37 +1283,6 @@ validate:
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*pte = npte;
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if (!wired && active_pmap(pmap))
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TBIS(va);
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#ifdef HAVEVAC
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/*
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* The following is executed if we are entering a second
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* (or greater) mapping for a physical page and the mappings
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* may create an aliasing problem. In this case we must
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* cache inhibit the descriptors involved and flush any
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* external VAC.
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*/
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if (checkpv && !cacheable) {
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pmap_changebit(pa, PG_CI, TRUE);
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DCIA();
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#ifdef PMAPSTATS
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enter_stats.flushes++;
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#endif
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#ifdef DEBUG
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if ((pmapdebug & (PDB_CACHE|PDB_PVDUMP)) ==
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(PDB_CACHE|PDB_PVDUMP))
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pmap_pvdump(pa);
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#endif
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}
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#ifdef DEBUG
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else if (pmapvacflush & PVF_ENTER) {
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if (pmapvacflush & PVF_TOTAL)
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DCIA();
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else if (pmap == pmap_kernel())
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DCIS();
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else
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DCIU();
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}
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#endif
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#endif
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#ifdef DEBUG
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if ((pmapdebug & PDB_WIRING) && pmap != pmap_kernel())
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pmap_check_wiring("enter", trunc_page(pmap_pte(pmap, va)));
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@ -1860,30 +1679,6 @@ pmap_remove_mapping(pmap, va, pte, flags)
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if (*pte == PG_NV)
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return;
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}
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#ifdef HAVEVAC
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if (pmap_aliasmask && (flags & PRM_CFLUSH)) {
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/*
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* Purge kernel side of VAC to ensure we get the correct
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* state of any hardware maintained bits.
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*/
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DCIS();
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#ifdef PMAPSTATS
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remove_stats.sflushes++;
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#endif
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/*
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* If this is a non-CI user mapping for the current process,
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* flush the VAC. Note that the kernel side was flushed
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* above so we don't worry about non-CI kernel mappings.
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*/
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if (pmap == curproc->p_vmspace->vm_map.pmap &&
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!pmap_pte_ci(pte)) {
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DCIU();
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#ifdef PMAPSTATS
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remove_stats.uflushes++;
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#endif
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}
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}
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#endif
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pa = pmap_pte_pa(pte);
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#ifdef DEBUG
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opte = *pte;
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@ -1974,25 +1769,6 @@ pmap_remove_mapping(pmap, va, pte, flags)
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pmap_free_pv(npv);
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pv = pa_to_pvh(pa);
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}
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#ifdef HAVEVAC
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/*
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* If only one mapping left we no longer need to cache inhibit
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*/
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if (pmap_aliasmask &&
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pv->pv_pmap && pv->pv_next == NULL && (pv->pv_flags & PV_CI)) {
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#ifdef DEBUG
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if (pmapdebug & PDB_CACHE)
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printf("remove: clearing CI for pa %x\n", pa);
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#endif
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pv->pv_flags &= ~PV_CI;
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pmap_changebit(pa, PG_CI, FALSE);
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#ifdef DEBUG
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if ((pmapdebug & (PDB_CACHE|PDB_PVDUMP)) ==
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(PDB_CACHE|PDB_PVDUMP))
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pmap_pvdump(pa);
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#endif
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}
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#endif
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/*
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* If this was a PT page we must also remove the
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* mapping from the associated segment table.
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@ -2105,13 +1881,6 @@ pmap_testbit(pa, bit)
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splx(s);
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return(TRUE);
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}
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#ifdef HAVEVAC
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/*
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* Flush VAC to get correct state of any hardware maintained bits.
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*/
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if (pmap_aliasmask && (bit & (PG_U|PG_M)))
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DCIS();
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#endif
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/*
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* Not found, check current mappings returning
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* immediately if found.
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@ -2140,7 +1909,9 @@ pmap_changebit(pa, bit, setem)
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register pt_entry_t *pte, npte;
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vm_offset_t va;
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int s;
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#if defined(M68040)
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boolean_t firstpage = TRUE;
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#endif
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#ifdef PMAPSTATS
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struct chgstats *chgp;
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#endif
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@ -2169,7 +1940,6 @@ pmap_changebit(pa, bit, setem)
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pmap_attributes[pmap_page_index(pa)] &= ~bit;
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/*
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* Loop over all current mappings setting/clearing as appropos
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* If setting RO do we need to clear the VAC?
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*/
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if (pv->pv_pmap != NULL) {
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#ifdef DEBUG
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@ -2192,16 +1962,6 @@ pmap_changebit(pa, bit, setem)
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}
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pte = pmap_pte(pv->pv_pmap, va);
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#ifdef HAVEVAC
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/*
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* Flush VAC to ensure we get correct state of HW bits
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* so we don't clobber them.
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*/
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if (firstpage && pmap_aliasmask) {
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firstpage = FALSE;
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DCIS();
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}
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#endif
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if (setem)
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npte = *pte | bit;
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else
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@ -2240,16 +2000,6 @@ pmap_changebit(pa, bit, setem)
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}
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#endif
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}
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#if defined(HAVEVAC) && defined(DEBUG)
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if (setem && bit == PG_RO && (pmapvacflush & PVF_PROTECT)) {
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if ((pmapvacflush & PVF_TOTAL) || toflush == 3)
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DCIA();
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else if (toflush == 2)
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DCIS();
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else
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DCIU();
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}
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#endif
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}
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splx(s);
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}
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