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rk3399_pcie: do reset timing according to PCI Express Base Specification

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Don't do link training or configuration space accesses within the time
allowed by the standard for the downstream card to come out of reset
after deasserting PERST#.

This fixes detection issues seen with a dual port wm(4) NIC,
an ASMedia SATA card and also Pericom bridges (but they need more work
to be useful).
This commit is contained in:
tnn 2020-10-08 22:14:00 +00:00
parent 8b9659189f
commit f4e80fd638
1 changed files with 7 additions and 5 deletions
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12
sys/arch/arm/rockchip/rk3399_pcie.c
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@ -1,4 +1,4 @@
/* $NetBSD: rk3399_pcie.c,v 1.10 2020/06/17 06:51:08 thorpej Exp $ */
/* $NetBSD: rk3399_pcie.c,v 1.11 2020/10/08 22:14:00 tnn Exp $ */
/*
* Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
*
@ -17,7 +17,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(1, "$NetBSD: rk3399_pcie.c,v 1.10 2020/06/17 06:51:08 thorpej Exp $");
__KERNEL_RCSID(1, "$NetBSD: rk3399_pcie.c,v 1.11 2020/10/08 22:14:00 tnn Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -278,7 +278,7 @@ again:
reset_assert(phandle, "mgmt-sticky");
reset_assert(phandle, "pipe");
delay(10);
delay(1000); /* TPERST. use 1ms */
reset_deassert(phandle, "pm");
reset_deassert(phandle, "aclk");
@ -311,11 +311,12 @@ again:
reset_deassert(phandle, "mgmt");
reset_deassert(phandle, "pipe");
fdtbus_gpio_write(ep_gpio, 1);
delay(20000); /* 20 ms according to PCI-e BS "Conventional Reset" */
/* Start link training. */
HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_LINK_TRAIN_EN);
fdtbus_gpio_write(ep_gpio, 1);
for (timo = 500; timo > 0; timo--) {
status = HREAD4(sc, PCIE_CLIENT_BASIC_STATUS1);
if (PCBS1_LINK_ST(status) == PCBS1_LS_DL_DONE)
@ -346,6 +347,7 @@ again:
goto again;
}
}
delay(80000); /* wait 100 ms before CSR access. already waited 20. */
fdtbus_gpio_release(ep_gpio);