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First whack at making single-stepping work through switch and return 

statements.
This commit is contained in:
mycroft 1998-11-25 06:41:26 +00:00
parent 26a93b8985
commit f4b034d33a
3 changed files with 111 additions and 17 deletions
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93
sys/arch/arm32/arm32/db_interface.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: db_interface.c,v 1.23 1998/08/29 03:21:33 mark Exp $ */
/* $NetBSD: db_interface.c,v 1.24 1998/11/25 06:41:26 mycroft Exp $ */
/*
* Copyright (c) 1996 Scott K. Stevens
@ -60,6 +60,7 @@ int db_access_svc_sp __P((struct db_variable *, db_expr_t *, int));
int db_access_und_sp __P((struct db_variable *, db_expr_t *, int));
int db_access_abt_sp __P((struct db_variable *, db_expr_t *, int));
int db_access_irq_sp __P((struct db_variable *, db_expr_t *, int));
u_int db_fetch_reg __P((int, db_regs_t *));
struct db_variable db_regs[] = {
{ "spsr", (long *)&DDB_TF->tf_spsr, FCN_NULL, },
@ -389,6 +390,49 @@ db_machine_init()
db_machine_commands_install(arm32_db_command_table);
}
u_int
db_fetch_reg(reg, db_regs)
int reg;
db_regs_t *db_regs;
{
switch (reg) {
case 0:
return (db_regs->ddb_tf.tf_r0);
case 1:
return (db_regs->ddb_tf.tf_r1);
case 2:
return (db_regs->ddb_tf.tf_r2);
case 3:
return (db_regs->ddb_tf.tf_r3);
case 4:
return (db_regs->ddb_tf.tf_r4);
case 5:
return (db_regs->ddb_tf.tf_r5);
case 6:
return (db_regs->ddb_tf.tf_r6);
case 7:
return (db_regs->ddb_tf.tf_r7);
case 8:
return (db_regs->ddb_tf.tf_r8);
case 9:
return (db_regs->ddb_tf.tf_r9);
case 10:
return (db_regs->ddb_tf.tf_r10);
case 11:
return (db_regs->ddb_tf.tf_r11);
case 12:
return (db_regs->ddb_tf.tf_r12);
case 13:
return (get_stackptr(PSR_SVC32_MODE));
case 14:
return (db_regs->ddb_tf.tf_svc_lr);
case 15:
return (db_regs->ddb_tf.tf_pc);
default:
panic("db_fetch_reg: botch");
}
}
u_int
branch_taken(insn, pc, db_regs)
@ -396,10 +440,47 @@ branch_taken(insn, pc, db_regs)
u_int pc;
db_regs_t *db_regs;
{
int branch;
u_int addr, nregs;
branch = ((insn << 2) & 0x03ffffff);
if (branch & 0x02000000)
branch |= 0xfc000000;
return(pc + 8 + branch);
switch ((insn >> 24) & 0xf) {
case 0xa: /* b ... */
case 0xb: /* bl ... */
addr = ((insn << 2) & 0x03ffffff);
if (addr & 0x02000000)
addr |= 0xfc000000;
return (pc + 8 + addr);
case 0x7: /* ldr pc, [pc, reg, lsl #2] */
addr = db_fetch_reg(insn & 0xf, db_regs);
addr = pc + 8 + (addr << 2);
db_read_bytes(addr, 4, (char *)&addr);
return (addr);
case 0x1: /* mov pc, reg */
addr = db_fetch_reg(insn & 0xf, db_regs);
return (addr);
case 0x8: /* ldmxx reg, {..., pc} */
case 0x9:
addr = db_fetch_reg((insn >> 16) & 0xf, db_regs);
nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555);
nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333);
nregs = (nregs + (nregs >> 4)) & 0x0f0f;
nregs = (nregs + (nregs >> 8)) & 0x001f;
switch ((insn >> 23) & 0x3) {
case 0x0: /* ldmda */
addr = addr - 0;
break;
case 0x1: /* ldmia */
addr = addr + 0 + ((nregs - 1) << 2);
break;
case 0x2: /* ldmdb */
addr = addr - 4;
break;
case 0x3: /* ldmib */
addr = addr + 4 + ((nregs - 1) << 2);
break;
}
db_read_bytes(addr, 4, (char *)&addr);
return (addr);
default:
panic("branch_taken: botch");
}
}

4
sys/arch/arm32/arm32/disassem.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: disassem.c,v 1.8 1998/01/20 00:51:24 mark Exp $ */
/* $NetBSD: disassem.c,v 1.9 1998/11/25 06:41:26 mycroft Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe.
@ -211,7 +211,7 @@ static char *insn_block_transfers[] = {
};
static char *insn_stack_block_transfers[] = {
"fa", "ea", "fd", "fa"
"ed", "ea", "fd", "fa"
};
static char *op_shifts[] = {

31
sys/arch/arm32/include/db_machdep.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: db_machdep.h,v 1.9 1998/08/15 02:57:28 mark Exp $ */
/* $NetBSD: db_machdep.h,v 1.10 1998/11/25 06:41:27 mycroft Exp $ */
/*
* Copyright (c) 1996 Scott K Stevens
@ -66,18 +66,31 @@ db_regs_t ddb_regs; /* register state */
#define IS_BREAKPOINT_TRAP(type, code) ((type) == T_BREAKPOINT)
#define IS_WATCHPOINT_TRAP(type, code) (0)
#define inst_trap_return(ins) ((ins)&0)
#define inst_return(ins) ((ins)&0)
#define inst_trap_return(ins) (0)
/* ldmxx reg, {..., pc}
01800000 stack mode
000f0000 register
0000ffff register list */
/* mov pc, reg
0000000f register */
#define inst_return(ins) (((ins) & 0x0e108000) == 0x08108000 || \
((ins) & 0x0ff0fff0) == 0x01a0f000)
/* bl ...
00ffffff offset>>2 */
#define inst_call(ins) (((ins) & 0x0f000000) == 0x0b000000)
#define inst_branch(ins) (((ins) & 0x0f000000) == 0x0a000000)
#define inst_load(ins) 0
#define inst_store(ins) 0
/* b ...
00ffffff offset>>2 */
/* ldr pc, [pc, reg, lsl #2]
0000000f register */
#define inst_branch(ins) (((ins) & 0x0f000000) == 0x0a000000 || \
((ins) & 0x0fdffff0) == 0x079ff100)
#define inst_load(ins) (0)
#define inst_store(ins) (0)
#define inst_unconditional_flow_transfer(ins) \
((((ins) & INSN_COND_MASK) == INSN_COND_AL) && \
(inst_call(ins) | inst_branch(ins)))
((((ins) & INSN_COND_MASK) == INSN_COND_AL) && inst_branch(ins))
#define getreg_val (0)
#define next_instr_address(pc, bd) ((bd) ? (pc) : (pc + INSN_SIZE))
#define next_instr_address(pc, bd) ((bd) ? (pc) : ((pc) + INSN_SIZE))
#define DB_MACHINE_COMMANDS