Add a driver for the Dallas Semiconductor RTC found on CATS motherboards.
This commit is contained in:
mark
parent
18ccba3b4e
commit
f452e15aff
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/* $NetBSD: ds1687reg.h,v 1.1 1998/10/05 01:20:57 mark Exp $ */
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/*
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* Copyright (c) 1998 Mark Brinicombe.
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* Copyright (c) 1998 Causality Limited.
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* All rights reserved.
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*
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* Written by Mark Brinicombe, Causality Limited
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY CAUASLITY LIMITED ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#define RTC_ADDR 0x72
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#define RTC_ADDR_REG 0x00
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#define RTC_DATA_REG 0x01
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#define RTC_SECONDS 0x00
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#define RTC_SECONDS_ALARM 0x01
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#define RTC_MINUTES 0x02
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#define RTC_MINUTES_ALARM 0x03
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#define RTC_HOURS 0x04
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#define RTC_HOURS_ALARM 0x05
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#define RTC_DAYOFWEEK 0x06
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#define RTC_DAYOFMONTH 0x07
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#define RTC_MONTH 0x08
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#define RTC_YEAR 0x09
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#define RTC_REG_A 0x0a
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#define RTC_REG_A_UIP 0x80 /* Update In Progress */
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#define RTC_REG_A_DV2 0x40 /* Countdown CHain */
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#define RTC_REG_A_DV1 0x20 /* Oscillator Enable */
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#define RTC_REG_A_DV0 0x10 /* Bank Select */
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#define RTC_REG_A_BANK_MASK RTC_REG_A_DV0
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#define RTC_REG_A_BANK1 RTC_REG_A_DV0
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#define RTC_REG_A_BANK0 0x00
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#define RTC_REG_A_RS_MASK 0x0f /* Rate select mask */
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#define RTC_REG_A_RS_NONE 0x00
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#define RTC_REG_A_RS_256HZ_1 0x01
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#define RTC_REG_A_RS_128HZ_1 0x02
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#define RTC_REG_A_RS_8192HZ 0x03
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#define RTC_REG_A_RS_4096HZ 0x04
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#define RTC_REG_A_RS_2048HZ 0x05
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#define RTC_REG_A_RS_1024HZ 0x06
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#define RTC_REG_A_RS_512HZ 0x07
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#define RTC_REG_A_RS_256HZ 0x08
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#define RTC_REG_A_RS_128HZ 0x09
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#define RTC_REG_A_RS_64HZ 0x0A
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#define RTC_REG_A_RS_32HZ 0x0B
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#define RTC_REG_A_RS_16HZ 0x0C
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#define RTC_REG_A_RS_8HZ 0x0D
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#define RTC_REG_A_RS_4HZ 0x0E
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#define RTC_REG_A_RS_2HZ 0x0F
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#define RTC_REG_B 0x0b
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#define RTC_REG_B_SET 0x80 /* Inhibit update */
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#define RTC_REG_B_PIE 0x40 /* Periodic Interrupt Enable */
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#define RTC_REG_B_AIE 0x20 /* Alarm Interrupt Enable */
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#define RTC_REG_B_UIE 0x10 /* Updated Ended Interrupt Enable */
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#define RTC_REG_B_SQWE 0x08 /* Square Wave Enable */
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#define RTC_REG_B_DM 0x04 /* Data Mode */
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#define RTC_REG_B_BINARY RTC_REG_B_DM
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#define RTC_REG_B_BCD 0
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#define RTC_REG_B_24_12 0x02 /* Hour format */
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#define RTC_REG_B_24_HOUR RTC_REG_B_24_12
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#define RTC_REG_B_12_HOUR 0
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#define RTC_REG_B_DSE 0x01 /* Daylight Savings Enable */
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#define RTC_REG_C 0x0c
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#define RTC_REG_C_IRQF 0x80 /* Interrupt Request Flag */
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#define RTC_REG_C_PF 0x40 /* Periodic Interrupt Flag */
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#define RTC_REG_C_AF 0x20 /* Alarm Interrupt Flag */
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#define RTC_REG_C_UF 0x10 /* Update Ended Flags */
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#define RTC_REG_D 0x0d
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#define RTC_REG_D_VRT 0x80 /* Valid RAM and Time */
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#define RTC_PC_RAM_START 0x0e
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#define RTC_PC_RAM_SIZE 50
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#define RTC_BANK0_RAM_START 0x40
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#define RTC_BANK0_RAM_SIZE 0x40
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#define RTC_MODEL 0x40
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#define RTC_SERIAL_1 0x41
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#define RTC_SERIAL_2 0x42
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#define RTC_SERIAL_3 0x43
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#define RTC_SERIAL_4 0x44
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#define RTC_SERIAL_5 0x45
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#define RTC_SERIAL_6 0x46
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#define RTC_CRC 0x47
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#define RTC_CENTURY 0x48
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#define RTC_DATE_ALARM 0x49
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#define RTC_REG_4A 0x4a
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#define RTC_REG_4A_VRT2 0x80
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#define RTC_REG_4A_INCR 0x40
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#define RTC_REG_4A_PAB 0x08
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#define RTC_REG_4A_RF 0x04
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#define RTC_REG_4B 0x4b
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#define RTC_EXT_RAM_ADDRESS 0x50
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#define RTC_EXT_RAM_DATA 0x53
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#define RTC_EXT_RAM_START 0x00
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#define RTC_EXT_RAM_SIZE 0x80
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@ -0,0 +1,260 @@
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/* $NetBSD: dsrtc.c,v 1.1 1998/10/05 01:20:58 mark Exp $ */
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/*
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* Copyright (c) 1998 Mark Brinicombe.
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* Copyright (c) 1998 Causality Limited.
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* All rights reserved.
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*
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* Written by Mark Brinicombe, Causality Limited
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY CAUASLITY LIMITED ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/conf.h>
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#include <sys/device.h>
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#include <machine/rtc.h>
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#include <arm32/dev/todclockvar.h>
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#include <arm32/isa/ds1687reg.h>
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#include <dev/isa/isavar.h>
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#define NRTC_PORTS 2
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struct dsrtc_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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};
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void dsrtcattach __P((struct device *parent, struct device *self, void *aux));
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int dsrtcmatch __P((struct device *parent, struct cfdata *cf, void *aux));
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int ds1687_read __P((struct dsrtc_softc *sc, int addr));
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void ds1687_write __P((struct dsrtc_softc *sc, int addr, int data));
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int ds1687_ram_read __P((struct dsrtc_softc *sc, int addr));
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void ds1687_ram_write __P((struct dsrtc_softc *sc, int addr, int data));
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int
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ds1687_read(sc, addr)
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struct dsrtc_softc *sc;
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int addr;
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{
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, RTC_ADDR_REG, addr);
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return(bus_space_read_1(sc->sc_iot, sc->sc_ioh, RTC_DATA_REG));
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}
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void
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ds1687_write(sc, addr, data)
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struct dsrtc_softc *sc;
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int addr;
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int data;
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{
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, RTC_ADDR_REG, addr);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, RTC_DATA_REG, data);
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}
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void
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ds1687_bank_select(sc, bank)
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struct dsrtc_softc *sc;
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int bank;
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{
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int data;
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data = ds1687_read(sc, RTC_REG_A);
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data &= ~RTC_REG_A_BANK_MASK;
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if (bank)
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data |= RTC_REG_A_BANK1;
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ds1687_write(sc, RTC_REG_A, data);
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}
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#if 0
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/* Nothing uses these yet */
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int
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ds1687_ram_read(sc, addr)
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struct dsrtc_softc *sc;
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int addr;
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{
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if (addr < RTC_PC_RAM_SIZE)
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return(ds1687_read(sc, RTC_PC_RAM_START + addr));
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addr -= RTC_PC_RAM_SIZE;
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if (addr < RTC_BANK0_RAM_SIZE)
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return(ds1687_read(sc, RTC_BANK0_RAM_START + addr));
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addr -= RTC_BANK0_RAM_SIZE;
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if (addr < RTC_EXT_RAM_SIZE) {
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int data;
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ds1687_bank_select(sc, 1);
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ds1687_write(sc, RTC_EXT_RAM_ADDRESS, addr);
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data = ds1687_read(sc, RTC_EXT_RAM_DATA);
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ds1687_bank_select(sc, 0);
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return(data);
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}
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return(-1);
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}
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void
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ds1687_ram_write(sc, addr, val)
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struct dsrtc_softc *sc;
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int addr;
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int val;
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{
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if (addr < RTC_PC_RAM_SIZE)
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return(ds1687_write(sc, RTC_PC_RAM_START + addr, val));
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addr -= RTC_PC_RAM_SIZE;
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if (addr < RTC_BANK0_RAM_SIZE)
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return(ds1687_write(sc, RTC_BANK0_RAM_START + addr, val));
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addr -= RTC_BANK0_RAM_SIZE;
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if (addr < RTC_EXT_RAM_SIZE) {
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ds1687_bank_select(sc, 1);
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ds1687_write(sc, RTC_EXT_RAM_ADDRESS, addr);
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ds1687_write(sc, RTC_EXT_RAM_DATA, val);
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ds1687_bank_select(sc, 0);
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}
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}
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#endif
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static int
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dsrtc_write(arg, rtc)
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void *arg;
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rtc_t *rtc;
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{
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struct dsrtc_softc *sc = arg;
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ds1687_write(sc, RTC_SECONDS, rtc->rtc_sec);
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ds1687_write(sc, RTC_MINUTES, rtc->rtc_min);
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ds1687_write(sc, RTC_HOURS, rtc->rtc_hour);
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ds1687_write(sc, RTC_DAYOFMONTH, rtc->rtc_day);
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ds1687_write(sc, RTC_MONTH, rtc->rtc_mon);
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ds1687_write(sc, RTC_YEAR, rtc->rtc_year);
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ds1687_bank_select(sc, 1);
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ds1687_write(sc, RTC_CENTURY, rtc->rtc_cen);
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ds1687_bank_select(sc, 0);
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return(1);
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}
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static int
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dsrtc_read(arg, rtc)
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void *arg;
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rtc_t *rtc;
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{
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struct dsrtc_softc *sc = arg;
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rtc->rtc_micro = 0;
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rtc->rtc_centi = 0;
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rtc->rtc_sec = ds1687_read(sc, RTC_SECONDS);
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rtc->rtc_min = ds1687_read(sc, RTC_MINUTES);
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rtc->rtc_hour = ds1687_read(sc, RTC_HOURS);
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rtc->rtc_day = ds1687_read(sc, RTC_DAYOFMONTH);
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rtc->rtc_mon = ds1687_read(sc, RTC_MONTH);
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rtc->rtc_year = ds1687_read(sc, RTC_YEAR);
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ds1687_bank_select(sc, 1);
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rtc->rtc_cen = ds1687_read(sc, RTC_CENTURY);
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ds1687_bank_select(sc, 0);
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return(1);
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}
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/* device and attach structures */
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struct cfattach dsrtc_ca = {
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sizeof(struct dsrtc_softc), dsrtcmatch, dsrtcattach
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};
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/*
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* dsrtcmatch()
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*
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* Validate the IIC address to make sure its an RTC we understand
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*/
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int
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dsrtcmatch(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct isa_attach_args *ia = aux;
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/* Disallow wildcarded i/o address. */
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if (ia->ia_iobase == ISACF_PORT_DEFAULT)
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return (0);
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ia->ia_iosize = NRTC_PORTS;
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ia->ia_msize = 0;
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return(1);
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}
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/*
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* dsrtcattach()
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*
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* Attach the rtc device
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*/
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void
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dsrtcattach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct dsrtc_softc *sc = (struct dsrtc_softc *)self;
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struct isa_attach_args *ia = aux;
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struct todclock_attach_args ta;
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sc->sc_iot = ia->ia_iot;
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if (bus_space_map(sc->sc_iot, ia->ia_iobase,
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NRTC_PORTS, 0, &sc->sc_ioh)) {
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printf(": cannot map I/O space\n");
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return;
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}
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ds1687_write(sc, RTC_REG_A, RTC_REG_A_DV1);
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ds1687_write(sc, RTC_REG_B, RTC_REG_B_BINARY | RTC_REG_B_24_HOUR);
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if (!(ds1687_read(sc, RTC_REG_D) & RTC_REG_D_VRT))
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printf(": lithium cell is dead, RTC unreliable");
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printf("\n");
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ta.ta_name = "todclock";
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ta.ta_rtc_arg = sc;
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ta.ta_rtc_write = dsrtc_write;
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ta.ta_rtc_read = dsrtc_read;
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ta.ta_flags = 0;
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config_found(self, &ta, NULL);
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}
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/* End of dsrtc.c */
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