remove EMODE support code.
- EMODE support doesn't work fine yet. - This code is broken for dreamcast. dramcast call sh4_icache_sync_all() before sh4_cache_config(). (at locore.S)
This commit is contained in:
nonaka
parent
7d6a4e53d1
commit
f3987f5dbb
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@ -1,4 +1,4 @@
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/* $NetBSD: cache_sh4.h,v 1.6 2005/06/29 16:51:20 christos Exp $ */
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/* $NetBSD: cache_sh4.h,v 1.7 2005/06/30 15:14:46 nonaka Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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@ -50,7 +50,7 @@
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#define SH4_CACHE_LINESZ 32
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#define SH4_CCR 0xff00001c
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#define SH4_CCR_EMODE 0x80000000
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#define SH4_CCR_EMODE 0x80000000
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#define SH4_CCR_IIX 0x00008000
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#define SH4_CCR_ICI 0x00000800
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#define SH4_CCR_ICE 0x00000100
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@ -106,12 +106,12 @@ do { \
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u_int32_t __e, __a; \
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\
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/* D-cache */ \
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for (__e = 0; __e < (sh_cache_size_dcache / SH4_CACHE_LINESZ); __e++) {\
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for (__e = 0; __e < (SH4_DCACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\
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__a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \
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(*(__volatile__ u_int32_t *)__a) &= ~(CCDA_U | CCDA_V); \
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} \
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/* I-cache */ \
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for (__e = 0; __e < (sh_cache_size_icache / SH4_CACHE_LINESZ); __e++) {\
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for (__e = 0; __e < (SH4_ICACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\
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__a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \
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(*(__volatile__ u_int32_t *)__a) &= ~(CCIA_V); \
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} \
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@ -123,7 +123,6 @@ do { \
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#define SH7751_CACHE_FLUSH() SH4_CACHE_FLUSH()
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#define SH7751R_CACHE_FLUSH() SH4_CACHE_FLUSH()
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#ifndef _LOCORE
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extern void sh4_cache_config(void);
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: cache_sh4.c,v 1.10 2005/06/29 16:56:58 christos Exp $ */
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/* $NetBSD: cache_sh4.c,v 1.11 2005/06/30 15:14:46 nonaka Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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@ -37,7 +37,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cache_sh4.c,v 1.10 2005/06/29 16:56:58 christos Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cache_sh4.c,v 1.11 2005/06/30 15:14:46 nonaka Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -48,9 +48,6 @@ __KERNEL_RCSID(0, "$NetBSD: cache_sh4.c,v 1.10 2005/06/29 16:56:58 christos Exp
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#define round_line(x) (((x) + 31) & ~31)
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#define trunc_line(x) ((x) & ~31)
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u_int32_t sh4_icache_mask;
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u_int32_t sh4_dcache_mask;
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void sh4_icache_sync_all(void);
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void sh4_icache_sync_range(vaddr_t, vsize_t);
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void sh4_icache_sync_range_index(vaddr_t, vsize_t);
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@ -67,79 +64,26 @@ static __inline__ void cache_sh4_op_8lines_32(vaddr_t, vaddr_t, u_int32_t,
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u_int32_t);
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void
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sh4_cache_config(void)
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sh4_cache_config()
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{
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jsize_t icache_size;
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size_t dcache_size;
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int ways;
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u_int32_t r;
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/* Determine cache size */
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switch (cpu_product) {
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default:
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/* FALLTHROUGH */
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case CPU_PRODUCT_7750:
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case CPU_PRODUCT_7750S:
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case CPU_PRODUCT_7751:
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#if defined(SH4_CACHE_DISABLE_EMODE)
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case CPU_PRODUCT_7750R:
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case CPU_PRODUCT_7751R:
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#endif
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icache_size = 8 * 1024;
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dcache_size = 16 * 1024;
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ways = 1;
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r = 0x0000090b;
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break;
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#if !defined(SH4_CACHE_DISABLE_EMODE)
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case CPU_PRODUCT_7750R:
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case CPU_PRODUCT_7751R:
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icache_size = 16 * 1024;
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dcache_size = 32 * 1024;
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ways = 2;
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r = 0x8000090b;
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break;
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#endif
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}
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#if defined(SH4_ICACHE_DISABLE)
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r &= ~0x00000100;
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#endif
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#if defined(SH4_DCACHE_DISABLE)
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r &= ~0x00000001;
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#endif
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#if defined(SH4_DCACHE_WB_P0)
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r &= ~0x00000002;
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#endif
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#if defined(SH4_DCACHE_WB_P1)
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r |= 0x00000004;
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#endif
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sh_cache_unified = 0;
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sh_cache_ways = ways;
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sh_cache_line_size = 32;
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sh_cache_size_dcache = dcache_size;
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if (sh_cache_ram_mode)
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sh_cache_size_dcache /= 2;
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sh_cache_size_icache = icache_size;
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sh4_icache_mask = (sh_cache_size_icache / sh_cache_line_size) - 1;
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sh4_icache_mask <<= CCIA_ENTRY_SHIFT;
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sh4_dcache_mask = (sh_cache_size_dcache / sh_cache_line_size) - 1;
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sh4_dcache_mask <<= CCDA_ENTRY_SHIFT;
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/*
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* For now, P0, U0, P3 write-through P1 write-through
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* XXX will be obsoleted.
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*/
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sh4_icache_sync_all();
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RUN_P2;
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_reg_write_4(SH4_CCR, r);
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_reg_write_4(SH4_CCR, 0x0000090b);
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RUN_P1;
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r = _reg_read_4(SH4_CCR);
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sh_cache_unified = 0;
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sh_cache_enable_icache = (r & SH4_CCR_ICE);
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sh_cache_enable_dcache = (r & SH4_CCR_OCE);
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sh_cache_ways = 1;
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sh_cache_line_size = 32;
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sh_cache_write_through_p0_u0_p3 = (r & SH4_CCR_WT);
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sh_cache_write_through_p1 = !(r & SH4_CCR_CB);
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sh_cache_write_through = sh_cache_write_through_p0_u0_p3 &&
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@ -148,6 +92,11 @@ sh4_cache_config(void)
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sh_cache_index_mode_icache = (r & SH4_CCR_IIX);
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sh_cache_index_mode_dcache = (r & SH4_CCR_OIX);
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sh_cache_size_dcache = SH4_DCACHE_SIZE;
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if (sh_cache_ram_mode)
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sh_cache_size_dcache /= 2;
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sh_cache_size_icache = SH4_ICACHE_SIZE;
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sh_cache_ops._icache_sync_all = sh4_icache_sync_all;
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sh_cache_ops._icache_sync_range = sh4_icache_sync_range;
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sh_cache_ops._icache_sync_range_index = sh4_icache_sync_range_index;
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@ -197,16 +146,16 @@ cache_sh4_op_8lines_32(vaddr_t va, vaddr_t base, u_int32_t mask, u_int32_t bits)
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}
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void
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sh4_icache_sync_all(void)
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sh4_icache_sync_all()
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{
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vaddr_t va = 0;
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vaddr_t eva = sh_cache_size_icache;
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vaddr_t eva = SH4_ICACHE_SIZE;
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sh4_dcache_wbinv_all();
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RUN_P2;
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while (va < eva) {
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cache_sh4_op_8lines_32(va, SH4_CCIA, sh4_icache_mask, CCIA_V);
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cache_sh4_op_8lines_32(va, SH4_CCIA, CCIA_ENTRY_MASK, CCIA_V);
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va += 32 * 8;
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}
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RUN_P1;
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@ -224,7 +173,7 @@ sh4_icache_sync_range(vaddr_t va, vsize_t sz)
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RUN_P2;
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while (va < eva) {
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/* CCR.IIX has no effect on this entry specification */
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ccia = SH4_CCIA | CCIA_A | (va & sh4_icache_mask);
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ccia = SH4_CCIA | CCIA_A | (va & CCIA_ENTRY_MASK);
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_reg_write_4(ccia, va & CCIA_TAGADDR_MASK); /* V = 0 */
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va += 32;
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}
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@ -241,26 +190,26 @@ sh4_icache_sync_range_index(vaddr_t va, vsize_t sz)
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RUN_P2;
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while ((eva - va) >= (8 * 32)) {
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cache_sh4_op_8lines_32(va, SH4_CCIA, sh4_icache_mask, CCIA_V);
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cache_sh4_op_8lines_32(va, SH4_CCIA, CCIA_ENTRY_MASK, CCIA_V);
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va += 32 * 8;
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}
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while (va < eva) {
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cache_sh4_op_line_32(va, SH4_CCIA, sh4_icache_mask, CCIA_V);
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cache_sh4_op_line_32(va, SH4_CCIA, CCIA_ENTRY_MASK, CCIA_V);
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va += 32;
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}
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RUN_P1;
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}
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void
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sh4_dcache_wbinv_all(void)
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sh4_dcache_wbinv_all()
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{
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vaddr_t va = 0;
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vaddr_t eva = sh_cache_size_dcache;
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vaddr_t eva = SH4_DCACHE_SIZE;
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RUN_P2;
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while (va < eva) {
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cache_sh4_op_8lines_32(va, SH4_CCDA, sh4_dcache_mask,
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cache_sh4_op_8lines_32(va, SH4_CCDA, CCDA_ENTRY_MASK,
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(CCDA_U | CCDA_V));
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va += 32 * 8;
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}
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@ -287,13 +236,13 @@ sh4_dcache_wbinv_range_index(vaddr_t va, vsize_t sz)
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RUN_P2;
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while ((eva - va) >= (8 * 32)) {
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cache_sh4_op_8lines_32(va, SH4_CCDA, sh4_dcache_mask,
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cache_sh4_op_8lines_32(va, SH4_CCDA, CCDA_ENTRY_MASK,
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(CCDA_U | CCDA_V));
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va += 32 * 8;
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}
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while (va < eva) {
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cache_sh4_op_line_32(va, SH4_CCDA, sh4_dcache_mask,
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cache_sh4_op_line_32(va, SH4_CCDA, CCDA_ENTRY_MASK,
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(CCDA_U | CCDA_V));
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va += 32;
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}
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