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Not pic->pic_addroute but pic->pic_hwunmask should enable interrupts for MSI-X.

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pic->pic_addroute should not enable interrupt, because callers expect
interrupts have been disabled until they call pic->pic_hwunmask.

By the way, the old implement writes zero to Vector Control for MSI-X Table
Entries, howerver it must be read and updated.  Because, there are not only
Mask Bit but also ST lower and ST upper.
This commit is contained in:
knakahara 2020-12-11 07:49:39 +00:00
parent 28c9f023c7
commit f38b032d02
1 changed files with 2 additions and 4 deletions
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6
sys/arch/x86/pci/msipic.c
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@ -1,4 +1,4 @@
/* $NetBSD: msipic.c,v 1.23 2020/05/04 15:55:56 jdolecek Exp $ */ /* $NetBSD: msipic.c,v 1.24 2020/12/11 07:49:39 knakahara Exp $ */
/* /*
* Copyright (c) 2015 Internet Initiative Japan Inc. * Copyright (c) 2015 Internet Initiative Japan Inc.
@ -27,7 +27,7 @@
*/ */
#include <sys/cdefs.h> #include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: msipic.c,v 1.23 2020/05/04 15:55:56 jdolecek Exp $"); __KERNEL_RCSID(0, "$NetBSD: msipic.c,v 1.24 2020/12/11 07:49:39 knakahara Exp $");
#include "opt_intrdebug.h" #include "opt_intrdebug.h"
@ -598,8 +598,6 @@ msix_addroute(struct pic *pic, struct cpu_info *ci,
bus_space_write_4(bstag, bshandle, bus_space_write_4(bstag, bshandle,
entry_base + PCI_MSIX_TABLE_ENTRY_DATA, data); entry_base + PCI_MSIX_TABLE_ENTRY_DATA, data);
#endif /* !XENPV */ #endif /* !XENPV */
bus_space_write_4(bstag, bshandle,
entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 0);
BUS_SPACE_WRITE_FLUSH(bstag, bshandle); BUS_SPACE_WRITE_FLUSH(bstag, bshandle);
ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);