Use BEBOX_REG for mapped to BAT instead of bebox_mb_reg.
This commit is contained in:
kiyohara
parent
be078a8d7f
commit
f3244f97ee
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: machdep.c,v 1.101 2011/06/30 00:52:55 matt Exp $ */
|
||||
/* $NetBSD: machdep.c,v 1.102 2011/08/07 15:04:46 kiyohara Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
|
||||
|
|
@ -32,7 +32,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.101 2011/06/30 00:52:55 matt Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.102 2011/08/07 15:04:46 kiyohara Exp $");
|
||||
|
||||
#include "opt_compat_netbsd.h"
|
||||
#include "opt_ddb.h"
|
||||
|
|
@ -104,7 +104,6 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.101 2011/06/30 00:52:55 matt Exp $");
|
|||
* Global variables used here and there
|
||||
*/
|
||||
char bootinfo[BOOTINFO_MAXSIZE];
|
||||
paddr_t bebox_mb_reg; /* BeBox MotherBoard register */
|
||||
#define OFMEMREGIONS 32
|
||||
struct mem_region physmemr[OFMEMREGIONS], availmemr[OFMEMREGIONS];
|
||||
char bootpath[256];
|
||||
|
|
@ -167,12 +166,6 @@ initppc(u_long startkernel, u_long endkernel, u_int args, void *btinfo)
|
|||
void
|
||||
cpu_startup(void)
|
||||
{
|
||||
/*
|
||||
* BeBox Mother Board's Register Mapping
|
||||
*/
|
||||
bebox_mb_reg = (vaddr_t) mapiodev(BEBOX_INTR_REG, PAGE_SIZE, false);
|
||||
if (!bebox_mb_reg)
|
||||
panic("cpu_startup: no room for interrupt register");
|
||||
|
||||
/*
|
||||
* Do common VM initialization
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: pic_bebox.c,v 1.7 2011/06/05 16:52:23 matt Exp $ */
|
||||
/* $NetBSD: pic_bebox.c,v 1.8 2011/08/07 15:13:07 kiyohara Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2007 The NetBSD Foundation, Inc.
|
||||
|
|
@ -30,7 +30,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: pic_bebox.c,v 1.7 2011/06/05 16:52:23 matt Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: pic_bebox.c,v 1.8 2011/08/07 15:13:07 kiyohara Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/malloc.h>
|
||||
|
|
@ -38,18 +38,14 @@ __KERNEL_RCSID(0, "$NetBSD: pic_bebox.c,v 1.7 2011/06/05 16:52:23 matt Exp $");
|
|||
|
||||
#include <uvm/uvm_extern.h>
|
||||
|
||||
#include <machine/bebox.h>
|
||||
#include <machine/pio.h>
|
||||
|
||||
#include <arch/powerpc/pic/picvar.h>
|
||||
|
||||
extern paddr_t bebox_mb_reg;
|
||||
|
||||
#define BEBOX_INTR_MASK 0x0ffffffc
|
||||
#define BEBOX_SET_MASK 0x80000000
|
||||
#define BEBOX_INTR(x) (0x80000000 >> x)
|
||||
#define CPU0_INT_MASK 0x0f0
|
||||
#define CPU1_INT_MASK 0x1f0
|
||||
#define INT_STATE_REG 0x2f0
|
||||
|
||||
static void bebox_enable_irq(struct pic_ops *, int, int);
|
||||
static void bebox_disable_irq(struct pic_ops *, int);
|
||||
|
|
@ -66,7 +62,7 @@ setup_bebox_intr(void)
|
|||
KASSERT(pic != NULL);
|
||||
|
||||
pic->pic_numintrs = 32;
|
||||
pic->pic_cookie = (void *)bebox_mb_reg;
|
||||
pic->pic_cookie = (void *)BEBOX_REG;
|
||||
pic->pic_enable_irq = bebox_enable_irq;
|
||||
pic->pic_reenable_irq = bebox_enable_irq;
|
||||
pic->pic_disable_irq = bebox_disable_irq;
|
||||
|
|
@ -82,7 +78,7 @@ static void
|
|||
bebox_enable_irq(struct pic_ops *pic, int irq, int type)
|
||||
{
|
||||
|
||||
*(volatile unsigned int *)(bebox_mb_reg + CPU0_INT_MASK) =
|
||||
*(volatile unsigned int *)(BEBOX_REG + CPU0_INT_MASK) =
|
||||
BEBOX_SET_MASK | (1 << (31 - irq));
|
||||
}
|
||||
|
||||
|
|
@ -90,7 +86,7 @@ static void
|
|||
bebox_disable_irq(struct pic_ops *pic, int irq)
|
||||
{
|
||||
|
||||
*(volatile unsigned int *)(bebox_mb_reg + CPU0_INT_MASK) =
|
||||
*(volatile unsigned int *)(BEBOX_REG + CPU0_INT_MASK) =
|
||||
(1 << (31 - irq));
|
||||
}
|
||||
|
||||
|
|
@ -99,9 +95,9 @@ bebox_get_irq(struct pic_ops *pic, int mode)
|
|||
{
|
||||
unsigned int state;
|
||||
|
||||
state = *(volatile unsigned int *)(bebox_mb_reg + INT_STATE_REG);
|
||||
state = *(volatile unsigned int *)(BEBOX_REG + INT_SOURCE);
|
||||
state &= BEBOX_INTR_MASK;
|
||||
state &= *(volatile unsigned int *)(bebox_mb_reg + CPU0_INT_MASK);
|
||||
state &= *(volatile unsigned int *)(BEBOX_REG + CPU0_INT_MASK);
|
||||
if (state == 0)
|
||||
return 255;
|
||||
return __builtin_clz(state);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,66 @@
|
|||
/* $NetBSD: bebox.h,v 1.1 2011/08/07 15:04:45 kiyohara Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2011 KIYOHARA Takashi
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _BEBOX_H
|
||||
#define _BEBOX_H
|
||||
|
||||
/*
|
||||
* BeBox mainboard's Register
|
||||
*/
|
||||
#define BEBOX_REG 0x7ffff000
|
||||
|
||||
#define BEBOX_SET_MASK 0x80000000
|
||||
#define BEBOX_CLEAR_MASK 0x00000000
|
||||
|
||||
#define READ_BEBOX_REG(reg) *(uint32_t *)(BEBOX_REG + (reg))
|
||||
#define SET_BEBOX_REG(reg, v) \
|
||||
*(uint32_t *)(BEBOX_REG + (reg)) = ((v) | BEBOX_SET_MASK)
|
||||
#define CLEAR_BEBOX_REG(reg, v) \
|
||||
*(uint32_t *)(BEBOX_REG + (reg)) = ((v) | BEBOX_CLEAR_MASK)
|
||||
|
||||
#define CPU0_INT_MASK 0x0f0 /* Interrupt Mask for CPU0 */
|
||||
#define CPU1_INT_MASK 0x1f0 /* Interrupt Mask for CPU1 */
|
||||
#define INT_SOURCE 0x2f0 /* Interrupt Source */
|
||||
#define CPU_CONTROL 0x3f0 /* Inter-CPU Interrupt */
|
||||
#define CPU_RESET 0x4f0 /* Reset Control */
|
||||
#define INTR_VECTOR_REG 0xff0
|
||||
|
||||
/* Control */
|
||||
#define CPU0_SMI (1 << 30) /* SMI to CPU0 */
|
||||
#define CPU1_SMI (1 << 29) /* SMI to CPU1 */
|
||||
#define CPU1_INT (1 << 28) /* Interrupt to CPU1 (rev.1 only) */
|
||||
#define CPU0_TLBISYNC (1 << 27) /* tlbsync to CPU0 */
|
||||
#define CPU1_TLBISYNC (1 << 26) /* tlbsync to CPU1 */
|
||||
#define WHO_AM_I (1 << 25)
|
||||
|
||||
#define TLBISYNC_FROM(n) (1 << (CPU1_TLBISYNC + (n)))
|
||||
|
||||
/* Reset */
|
||||
#define CPU1_SRESET (1 << 30) /* Software Reset to CPU1 */
|
||||
#define CPU1_HRESET (1 << 29) /* Hardware Reset to CPU1 */
|
||||
|
||||
#endif /* _BEBOX_H */
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: intr.h,v 1.30 2011/06/17 23:36:17 matt Exp $ */
|
||||
/* $NetBSD: intr.h,v 1.31 2011/08/07 15:13:07 kiyohara Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
|
|
@ -40,15 +40,11 @@
|
|||
void enable_intr(void);
|
||||
void disable_intr(void);
|
||||
|
||||
extern paddr_t bebox_mb_reg;
|
||||
|
||||
#define ICU_LEN 32
|
||||
#define IRQ_SLAVE 2
|
||||
#define LEGAL_HWIRQ_P(x) ((u_int)(x) < ICU_LEN && (x) != IRQ_SLAVE)
|
||||
|
||||
#define BEBOX_INTR_REG 0x7ffff000
|
||||
#define INTR_VECTOR_REG 0xff0
|
||||
|
||||
#endif /* !_LOCORE */
|
||||
|
||||
#endif /* !_BEBOX_INTR_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue